[qemu.git] / hw / lm32_uart.c

/*
 *  QEMU model of the LatticeMico32 UART block.
 *
 *  Copyright (c) 2010 Michael Walle <[email protected]>
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 *
 *
 * Specification available at:
 *   http://www.latticesemi.com/documents/mico32uart.pdf
 */


#include "hw.h"
#include "sysbus.h"
#include "trace.h"
#include "qemu-char.h"
#include "qemu-error.h"

enum {
    R_RXTX = 0,
    R_IER,
    R_IIR,
    R_LCR,
    R_MCR,
    R_LSR,
    R_MSR,
    R_DIV,
    R_MAX
};

enum {
    IER_RBRI = (1<<0),
    IER_THRI = (1<<1),
    IER_RLSI = (1<<2),
    IER_MSI  = (1<<3),
};

enum {
    IIR_STAT = (1<<0),
    IIR_ID0  = (1<<1),
    IIR_ID1  = (1<<2),
};

enum {
    LCR_WLS0 = (1<<0),
    LCR_WLS1 = (1<<1),
    LCR_STB  = (1<<2),
    LCR_PEN  = (1<<3),
    LCR_EPS  = (1<<4),
    LCR_SP   = (1<<5),
    LCR_SB   = (1<<6),
};

enum {
    MCR_DTR  = (1<<0),
    MCR_RTS  = (1<<1),
};

enum {
    LSR_DR   = (1<<0),
    LSR_OE   = (1<<1),
    LSR_PE   = (1<<2),
    LSR_FE   = (1<<3),
    LSR_BI   = (1<<4),
    LSR_THRE = (1<<5),
    LSR_TEMT = (1<<6),
};

enum {
    MSR_DCTS = (1<<0),
    MSR_DDSR = (1<<1),
    MSR_TERI = (1<<2),
    MSR_DDCD = (1<<3),
    MSR_CTS  = (1<<4),
    MSR_DSR  = (1<<5),
    MSR_RI   = (1<<6),
    MSR_DCD  = (1<<7),
};

struct LM32UartState {
    SysBusDevice busdev;
    MemoryRegion iomem;
    CharDriverState *chr;
    qemu_irq irq;

    uint32_t regs[R_MAX];
};
typedef struct LM32UartState LM32UartState;

static void uart_update_irq(LM32UartState *s)
{
    unsigned int irq;

    if ((s->regs[R_LSR] & (LSR_OE | LSR_PE | LSR_FE | LSR_BI))
            && (s->regs[R_IER] & IER_RLSI)) {
        irq = 1;
        s->regs[R_IIR] = IIR_ID1 | IIR_ID0;
    } else if ((s->regs[R_LSR] & LSR_DR) && (s->regs[R_IER] & IER_RBRI)) {
        irq = 1;
        s->regs[R_IIR] = IIR_ID1;
    } else if ((s->regs[R_LSR] & LSR_THRE) && (s->regs[R_IER] & IER_THRI)) {
        irq = 1;
        s->regs[R_IIR] = IIR_ID0;
    } else if ((s->regs[R_MSR] & 0x0f) && (s->regs[R_IER] & IER_MSI)) {
        irq = 1;
        s->regs[R_IIR] = 0;
    } else {
        irq = 0;
        s->regs[R_IIR] = IIR_STAT;
    }

    trace_lm32_uart_irq_state(irq);
    qemu_set_irq(s->irq, irq);
}

static uint64_t uart_read(void *opaque, target_phys_addr_t addr,
                          unsigned size)
{
    LM32UartState *s = opaque;
    uint32_t r = 0;

    addr >>= 2;
    switch (addr) {
    case R_RXTX:
        r = s->regs[R_RXTX];
        s->regs[R_LSR] &= ~LSR_DR;
        uart_update_irq(s);
        break;
    case R_IIR:
    case R_LSR:
    case R_MSR:
        r = s->regs[addr];
        break;
    case R_IER:
    case R_LCR:
    case R_MCR:
    case R_DIV:
        error_report("lm32_uart: read access to write only register 0x"
                TARGET_FMT_plx, addr << 2);
        break;
    default:
        error_report("lm32_uart: read access to unknown register 0x"
                TARGET_FMT_plx, addr << 2);
        break;
    }

    trace_lm32_uart_memory_read(addr << 2, r);
    return r;
}

static void uart_write(void *opaque, target_phys_addr_t addr,
                       uint64_t value, unsigned size)
{
    LM32UartState *s = opaque;
    unsigned char ch = value;

    trace_lm32_uart_memory_write(addr, value);

    addr >>= 2;
    switch (addr) {
    case R_RXTX:
        if (s->chr) {
            qemu_chr_fe_write(s->chr, &ch, 1);
        }
        break;
    case R_IER:
    case R_LCR:
    case R_MCR:
    case R_DIV:
        s->regs[addr] = value;
        break;
    case R_IIR:
    case R_LSR:
    case R_MSR:
        error_report("lm32_uart: write access to read only register 0x"
                TARGET_FMT_plx, addr << 2);
        break;
    default:
        error_report("lm32_uart: write access to unknown register 0x"
                TARGET_FMT_plx, addr << 2);
        break;
    }
    uart_update_irq(s);
}

static const MemoryRegionOps uart_ops = {
    .read = uart_read,
    .write = uart_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
    .valid = {
        .min_access_size = 4,
        .max_access_size = 4,
    },
};

static void uart_rx(void *opaque, const uint8_t *buf, int size)
{
    LM32UartState *s = opaque;

    if (s->regs[R_LSR] & LSR_DR) {
        s->regs[R_LSR] |= LSR_OE;
    }

    s->regs[R_LSR] |= LSR_DR;
    s->regs[R_RXTX] = *buf;

    uart_update_irq(s);
}

static int uart_can_rx(void *opaque)
{
    LM32UartState *s = opaque;

    return !(s->regs[R_LSR] & LSR_DR);
}

static void uart_event(void *opaque, int event)
{
}

static void uart_reset(DeviceState *d)
{
    LM32UartState *s = container_of(d, LM32UartState, busdev.qdev);
    int i;

    for (i = 0; i < R_MAX; i++) {
        s->regs[i] = 0;
    }

    /* defaults */
    s->regs[R_LSR] = LSR_THRE | LSR_TEMT;
}

static int lm32_uart_init(SysBusDevice *dev)
{
    LM32UartState *s = FROM_SYSBUS(typeof(*s), dev);

    sysbus_init_irq(dev, &s->irq);

    memory_region_init_io(&s->iomem, &uart_ops, s, "uart", R_MAX * 4);
    sysbus_init_mmio(dev, &s->iomem);

    s->chr = qemu_char_get_next_serial();
    if (s->chr) {
        qemu_chr_add_handlers(s->chr, uart_can_rx, uart_rx, uart_event, s);
    }

    return 0;
}

static const VMStateDescription vmstate_lm32_uart = {
    .name = "lm32-uart",
    .version_id = 1,
    .minimum_version_id = 1,
    .minimum_version_id_old = 1,
    .fields      = (VMStateField[]) {
        VMSTATE_UINT32_ARRAY(regs, LM32UartState, R_MAX),
        VMSTATE_END_OF_LIST()
    }
};

static void lm32_uart_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);
    SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);

    k->init = lm32_uart_init;
    dc->reset = uart_reset;
    dc->vmsd = &vmstate_lm32_uart;
}

static TypeInfo lm32_uart_info = {
    .name          = "lm32-uart",
    .parent        = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(LM32UartState),
    .class_init    = lm32_uart_class_init,
};

static void lm32_uart_register(void)
{
    type_register_static(&lm32_uart_info);
}

device_init(lm32_uart_register)
Commit	Line	Data
770ae571 MW	1	/*
	2	* QEMU model of the LatticeMico32 UART block.
	3	*
	4	* Copyright (c) 2010 Michael Walle <[email protected]>
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
	9	* version 2 of the License, or (at your option) any later version.
	10	*
	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
	17	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
	18	*
	19	*
	20	* Specification available at:
	21	* http://www.latticesemi.com/documents/mico32uart.pdf
	22	*/
	23
	24
	25	#include "hw.h"
	26	#include "sysbus.h"
	27	#include "trace.h"
	28	#include "qemu-char.h"
	29	#include "qemu-error.h"
	30
	31	enum {
	32	R_RXTX = 0,
	33	R_IER,
	34	R_IIR,
	35	R_LCR,
	36	R_MCR,
	37	R_LSR,
	38	R_MSR,
	39	R_DIV,
	40	R_MAX
	41	};
	42
	43	enum {
	44	IER_RBRI = (1<<0),
	45	IER_THRI = (1<<1),
	46	IER_RLSI = (1<<2),
	47	IER_MSI = (1<<3),
	48	};
	49
	50	enum {
	51	IIR_STAT = (1<<0),
	52	IIR_ID0 = (1<<1),
	53	IIR_ID1 = (1<<2),
	54	};
	55
	56	enum {
	57	LCR_WLS0 = (1<<0),
	58	LCR_WLS1 = (1<<1),
	59	LCR_STB = (1<<2),
	60	LCR_PEN = (1<<3),
	61	LCR_EPS = (1<<4),
	62	LCR_SP = (1<<5),
	63	LCR_SB = (1<<6),
	64	};
65
66	enum {
67	MCR_DTR = (1<<0),
68	MCR_RTS = (1<<1),
69	};
70
71	enum {
72	LSR_DR = (1<<0),
73	LSR_OE = (1<<1),
74	LSR_PE = (1<<2),
75	LSR_FE = (1<<3),
76	LSR_BI = (1<<4),
77	LSR_THRE = (1<<5),
78	LSR_TEMT = (1<<6),
79	};
80
81	enum {
82	MSR_DCTS = (1<<0),
83	MSR_DDSR = (1<<1),
84	MSR_TERI = (1<<2),
85	MSR_DDCD = (1<<3),
86	MSR_CTS = (1<<4),
87	MSR_DSR = (1<<5),
88	MSR_RI = (1<<6),
89	MSR_DCD = (1<<7),
90	};
91
92	struct LM32UartState {
93	SysBusDevice busdev;
5f2be17a	94	MemoryRegion iomem;
770ae571 MW	95	CharDriverState *chr;
	96	qemu_irq irq;
	97
	98	uint32_t regs[R_MAX];
	99	};
	100	typedef struct LM32UartState LM32UartState;
	101
	102	static void uart_update_irq(LM32UartState *s)
	103	{
	104	unsigned int irq;
	105
	106	if ((s->regs[R_LSR] & (LSR_OE \| LSR_PE \| LSR_FE \| LSR_BI))
	107	&& (s->regs[R_IER] & IER_RLSI)) {
	108	irq = 1;
	109	s->regs[R_IIR] = IIR_ID1 \| IIR_ID0;
	110	} else if ((s->regs[R_LSR] & LSR_DR) && (s->regs[R_IER] & IER_RBRI)) {
	111	irq = 1;
	112	s->regs[R_IIR] = IIR_ID1;
	113	} else if ((s->regs[R_LSR] & LSR_THRE) && (s->regs[R_IER] & IER_THRI)) {
	114	irq = 1;
	115	s->regs[R_IIR] = IIR_ID0;
	116	} else if ((s->regs[R_MSR] & 0x0f) && (s->regs[R_IER] & IER_MSI)) {
	117	irq = 1;
	118	s->regs[R_IIR] = 0;
	119	} else {
	120	irq = 0;
	121	s->regs[R_IIR] = IIR_STAT;
	122	}
	123
	124	trace_lm32_uart_irq_state(irq);
	125	qemu_set_irq(s->irq, irq);
	126	}
	127
5f2be17a BC	128	static uint64_t uart_read(void *opaque, target_phys_addr_t addr,
5f2be17a BC	129	unsigned size)
770ae571 MW	130	{
	131	LM32UartState *s = opaque;
	132	uint32_t r = 0;
	133
	134	addr >>= 2;
	135	switch (addr) {
	136	case R_RXTX:
	137	r = s->regs[R_RXTX];
	138	s->regs[R_LSR] &= ~LSR_DR;
	139	uart_update_irq(s);
	140	break;
	141	case R_IIR:
	142	case R_LSR:
	143	case R_MSR:
	144	r = s->regs[addr];
	145	break;
	146	case R_IER:
	147	case R_LCR:
	148	case R_MCR:
	149	case R_DIV:
	150	error_report("lm32_uart: read access to write only register 0x"
	151	TARGET_FMT_plx, addr << 2);
	152	break;
	153	default:
dd3d6775	154	error_report("lm32_uart: read access to unknown register 0x"
770ae571 MW	155	TARGET_FMT_plx, addr << 2);
	156	break;
	157	}
	158
	159	trace_lm32_uart_memory_read(addr << 2, r);
	160	return r;
	161	}
	162
5f2be17a BC	163	static void uart_write(void *opaque, target_phys_addr_t addr,
5f2be17a BC	164	uint64_t value, unsigned size)
770ae571 MW	165	{
	166	LM32UartState *s = opaque;
	167	unsigned char ch = value;
	168
	169	trace_lm32_uart_memory_write(addr, value);
	170
	171	addr >>= 2;
	172	switch (addr) {
	173	case R_RXTX:
	174	if (s->chr) {
2cc6e0a1	175	qemu_chr_fe_write(s->chr, &ch, 1);
770ae571 MW	176	}
	177	break;
	178	case R_IER:
	179	case R_LCR:
	180	case R_MCR:
	181	case R_DIV:
	182	s->regs[addr] = value;
	183	break;
	184	case R_IIR:
	185	case R_LSR:
	186	case R_MSR:
	187	error_report("lm32_uart: write access to read only register 0x"
	188	TARGET_FMT_plx, addr << 2);
	189	break;
	190	default:
dd3d6775	191	error_report("lm32_uart: write access to unknown register 0x"
770ae571 MW	192	TARGET_FMT_plx, addr << 2);
	193	break;
	194	}
	195	uart_update_irq(s);
	196	}
	197
5f2be17a BC	198	static const MemoryRegionOps uart_ops = {
	199	.read = uart_read,
	200	.write = uart_write,
	201	.endianness = DEVICE_NATIVE_ENDIAN,
	202	.valid = {
	203	.min_access_size = 4,
	204	.max_access_size = 4,
	205	},
770ae571 MW	206	};
	207
	208	static void uart_rx(void opaque, const uint8_t buf, int size)
	209	{
	210	LM32UartState *s = opaque;
	211
	212	if (s->regs[R_LSR] & LSR_DR) {
	213	s->regs[R_LSR] \|= LSR_OE;
	214	}
	215
	216	s->regs[R_LSR] \|= LSR_DR;
	217	s->regs[R_RXTX] = *buf;
	218
	219	uart_update_irq(s);
	220	}
	221
	222	static int uart_can_rx(void *opaque)
	223	{
	224	LM32UartState *s = opaque;
	225
	226	return !(s->regs[R_LSR] & LSR_DR);
	227	}
	228
	229	static void uart_event(void *opaque, int event)
	230	{
	231	}
	232
	233	static void uart_reset(DeviceState *d)
	234	{
	235	LM32UartState *s = container_of(d, LM32UartState, busdev.qdev);
	236	int i;
	237
	238	for (i = 0; i < R_MAX; i++) {
	239	s->regs[i] = 0;
	240	}
	241
	242	/* defaults */
	243	s->regs[R_LSR] = LSR_THRE \| LSR_TEMT;
	244	}
	245
	246	static int lm32_uart_init(SysBusDevice *dev)
	247	{
	248	LM32UartState s = FROM_SYSBUS(typeof(s), dev);
770ae571 MW	249
	250	sysbus_init_irq(dev, &s->irq);
	251
5f2be17a	252	memory_region_init_io(&s->iomem, &uart_ops, s, "uart", R_MAX * 4);
750ecd44	253	sysbus_init_mmio(dev, &s->iomem);
770ae571	254
0beb4942	255	s->chr = qemu_char_get_next_serial();
770ae571 MW	256	if (s->chr) {
	257	qemu_chr_add_handlers(s->chr, uart_can_rx, uart_rx, uart_event, s);
	258	}
	259
	260	return 0;
	261	}
	262
	263	static const VMStateDescription vmstate_lm32_uart = {
	264	.name = "lm32-uart",
	265	.version_id = 1,
	266	.minimum_version_id = 1,
	267	.minimum_version_id_old = 1,
	268	.fields = (VMStateField[]) {
	269	VMSTATE_UINT32_ARRAY(regs, LM32UartState, R_MAX),
	270	VMSTATE_END_OF_LIST()
	271	}
	272	};
	273
999e12bb AL	274	static void lm32_uart_class_init(ObjectClass klass, void data)
999e12bb AL	275	{
39bffca2	276	DeviceClass *dc = DEVICE_CLASS(klass);
999e12bb AL	277	SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
	278
	279	k->init = lm32_uart_init;
39bffca2 AL	280	dc->reset = uart_reset;
39bffca2 AL	281	dc->vmsd = &vmstate_lm32_uart;
999e12bb AL	282	}
999e12bb AL	283
39bffca2 AL	284	static TypeInfo lm32_uart_info = {
	285	.name = "lm32-uart",
	286	.parent = TYPE_SYS_BUS_DEVICE,
	287	.instance_size = sizeof(LM32UartState),
	288	.class_init = lm32_uart_class_init,
770ae571 MW	289	};
	290
	291	static void lm32_uart_register(void)
	292	{
39bffca2	293	type_register_static(&lm32_uart_info);
770ae571 MW	294	}
	295
	296	device_init(lm32_uart_register)