[qemu.git] / hw / ide / pci.c

/*
 * QEMU IDE Emulation: PCI Bus support.
 *
 * Copyright (c) 2003 Fabrice Bellard
 * Copyright (c) 2006 Openedhand Ltd.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#include <hw/hw.h>
#include <hw/pc.h>
#include <hw/pci.h>
#include <hw/isa.h>
#include "block.h"
#include "dma.h"

#include <hw/ide/pci.h>

#define BMDMA_PAGE_SIZE 4096

static void bmdma_start_dma(IDEDMA *dma, IDEState *s,
                            BlockDriverCompletionFunc *dma_cb)
{
    BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);

    bm->unit = s->unit;
    bm->dma_cb = dma_cb;
    bm->cur_prd_last = 0;
    bm->cur_prd_addr = 0;
    bm->cur_prd_len = 0;
    bm->sector_num = ide_get_sector(s);
    bm->nsector = s->nsector;

    if (bm->status & BM_STATUS_DMAING) {
        bm->dma_cb(bmdma_active_if(bm), 0);
    }
}

/* return 0 if buffer completed */
static int bmdma_prepare_buf(IDEDMA *dma, int is_write)
{
    BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);
    IDEState *s = bmdma_active_if(bm);
    struct {
        uint32_t addr;
        uint32_t size;
    } prd;
    int l, len;

    qemu_sglist_init(&s->sg, s->nsector / (BMDMA_PAGE_SIZE / 512) + 1);
    s->io_buffer_size = 0;
    for(;;) {
        if (bm->cur_prd_len == 0) {
            /* end of table (with a fail safe of one page) */
            if (bm->cur_prd_last ||
                (bm->cur_addr - bm->addr) >= BMDMA_PAGE_SIZE)
                return s->io_buffer_size != 0;
            cpu_physical_memory_read(bm->cur_addr, (uint8_t *)&prd, 8);
            bm->cur_addr += 8;
            prd.addr = le32_to_cpu(prd.addr);
            prd.size = le32_to_cpu(prd.size);
            len = prd.size & 0xfffe;
            if (len == 0)
                len = 0x10000;
            bm->cur_prd_len = len;
            bm->cur_prd_addr = prd.addr;
            bm->cur_prd_last = (prd.size & 0x80000000);
        }
        l = bm->cur_prd_len;
        if (l > 0) {
            qemu_sglist_add(&s->sg, bm->cur_prd_addr, l);
            bm->cur_prd_addr += l;
            bm->cur_prd_len -= l;
            s->io_buffer_size += l;
        }
    }
    return 1;
}

/* return 0 if buffer completed */
static int bmdma_rw_buf(IDEDMA *dma, int is_write)
{
    BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);
    IDEState *s = bmdma_active_if(bm);
    struct {
        uint32_t addr;
        uint32_t size;
    } prd;
    int l, len;

    for(;;) {
        l = s->io_buffer_size - s->io_buffer_index;
        if (l <= 0)
            break;
        if (bm->cur_prd_len == 0) {
            /* end of table (with a fail safe of one page) */
            if (bm->cur_prd_last ||
                (bm->cur_addr - bm->addr) >= BMDMA_PAGE_SIZE)
                return 0;
            cpu_physical_memory_read(bm->cur_addr, (uint8_t *)&prd, 8);
            bm->cur_addr += 8;
            prd.addr = le32_to_cpu(prd.addr);
            prd.size = le32_to_cpu(prd.size);
            len = prd.size & 0xfffe;
            if (len == 0)
                len = 0x10000;
            bm->cur_prd_len = len;
            bm->cur_prd_addr = prd.addr;
            bm->cur_prd_last = (prd.size & 0x80000000);
        }
        if (l > bm->cur_prd_len)
            l = bm->cur_prd_len;
        if (l > 0) {
            if (is_write) {
                cpu_physical_memory_write(bm->cur_prd_addr,
                                          s->io_buffer + s->io_buffer_index, l);
            } else {
                cpu_physical_memory_read(bm->cur_prd_addr,
                                          s->io_buffer + s->io_buffer_index, l);
            }
            bm->cur_prd_addr += l;
            bm->cur_prd_len -= l;
            s->io_buffer_index += l;
        }
    }
    return 1;
}

static int bmdma_set_unit(IDEDMA *dma, int unit)
{
    BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);
    bm->unit = unit;

    return 0;
}

static int bmdma_add_status(IDEDMA *dma, int status)
{
    BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);
    bm->status |= status;

    return 0;
}

static int bmdma_set_inactive(IDEDMA *dma)
{
    BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);

    bm->status &= ~BM_STATUS_DMAING;
    bm->dma_cb = NULL;
    bm->unit = -1;

    return 0;
}

static void bmdma_restart_dma(BMDMAState *bm, enum ide_dma_cmd dma_cmd)
{
    IDEState *s = bmdma_active_if(bm);

    ide_set_sector(s, bm->sector_num);
    s->io_buffer_index = 0;
    s->io_buffer_size = 0;
    s->nsector = bm->nsector;
    s->dma_cmd = dma_cmd;
    bm->cur_addr = bm->addr;
    bm->dma_cb = ide_dma_cb;
    bmdma_start_dma(&bm->dma, s, bm->dma_cb);
}

/* TODO This should be common IDE code */
static void bmdma_restart_bh(void *opaque)
{
    BMDMAState *bm = opaque;
    IDEBus *bus = bm->bus;
    int is_read;
    int error_status;

    qemu_bh_delete(bm->bh);
    bm->bh = NULL;

    if (bm->unit == (uint8_t) -1) {
        return;
    }

    is_read = !!(bus->error_status & BM_STATUS_RETRY_READ);

    /* The error status must be cleared before resubmitting the request: The
     * request may fail again, and this case can only be distinguished if the
     * called function can set a new error status. */
    error_status = bus->error_status;
    bus->error_status = 0;

    if (error_status & BM_STATUS_DMA_RETRY) {
        if (error_status & BM_STATUS_RETRY_TRIM) {
            bmdma_restart_dma(bm, IDE_DMA_TRIM);
        } else {
            bmdma_restart_dma(bm, is_read ? IDE_DMA_READ : IDE_DMA_WRITE);
        }
    } else if (error_status & BM_STATUS_PIO_RETRY) {
        if (is_read) {
            ide_sector_read(bmdma_active_if(bm));
        } else {
            ide_sector_write(bmdma_active_if(bm));
        }
    } else if (error_status & BM_STATUS_RETRY_FLUSH) {
        ide_flush_cache(bmdma_active_if(bm));
    }
}

static void bmdma_restart_cb(void *opaque, int running, RunState state)
{
    IDEDMA *dma = opaque;
    BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);

    if (!running)
        return;

    if (!bm->bh) {
        bm->bh = qemu_bh_new(bmdma_restart_bh, &bm->dma);
        qemu_bh_schedule(bm->bh);
    }
}

static void bmdma_cancel(BMDMAState *bm)
{
    if (bm->status & BM_STATUS_DMAING) {
        /* cancel DMA request */
        bmdma_set_inactive(&bm->dma);
    }
}

static int bmdma_reset(IDEDMA *dma)
{
    BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);

#ifdef DEBUG_IDE
    printf("ide: dma_reset\n");
#endif
    bmdma_cancel(bm);
    bm->cmd = 0;
    bm->status = 0;
    bm->addr = 0;
    bm->cur_addr = 0;
    bm->cur_prd_last = 0;
    bm->cur_prd_addr = 0;
    bm->cur_prd_len = 0;
    bm->sector_num = 0;
    bm->nsector = 0;

    return 0;
}

static int bmdma_start_transfer(IDEDMA *dma)
{
    return 0;
}

static void bmdma_irq(void *opaque, int n, int level)
{
    BMDMAState *bm = opaque;

    if (!level) {
        /* pass through lower */
        qemu_set_irq(bm->irq, level);
        return;
    }

    bm->status |= BM_STATUS_INT;

    /* trigger the real irq */
    qemu_set_irq(bm->irq, level);
}

void bmdma_cmd_writeb(BMDMAState *bm, uint32_t val)
{
#ifdef DEBUG_IDE
    printf("%s: 0x%08x\n", __func__, val);
#endif

    /* Ignore writes to SSBM if it keeps the old value */
    if ((val & BM_CMD_START) != (bm->cmd & BM_CMD_START)) {
        if (!(val & BM_CMD_START)) {
            /*
             * We can't cancel Scatter Gather DMA in the middle of the
             * operation or a partial (not full) DMA transfer would reach
             * the storage so we wait for completion instead (we beahve
             * like if the DMA was completed by the time the guest trying
             * to cancel dma with bmdma_cmd_writeb with BM_CMD_START not
             * set).
             *
             * In the future we'll be able to safely cancel the I/O if the
             * whole DMA operation will be submitted to disk with a single
             * aio operation with preadv/pwritev.
             */
            if (bm->bus->dma->aiocb) {
                qemu_aio_flush();
                assert(bm->bus->dma->aiocb == NULL);
                assert((bm->status & BM_STATUS_DMAING) == 0);
            }
        } else {
            bm->cur_addr = bm->addr;
            if (!(bm->status & BM_STATUS_DMAING)) {
                bm->status |= BM_STATUS_DMAING;
                /* start dma transfer if possible */
                if (bm->dma_cb)
                    bm->dma_cb(bmdma_active_if(bm), 0);
            }
        }
    }

    bm->cmd = val & 0x09;
}

static uint64_t bmdma_addr_read(void *opaque, target_phys_addr_t addr,
                                unsigned width)
{
    BMDMAState *bm = opaque;
    uint32_t mask = (1ULL << (width * 8)) - 1;
    uint64_t data;

    data = (bm->addr >> (addr * 8)) & mask;
#ifdef DEBUG_IDE
    printf("%s: 0x%08x\n", __func__, (unsigned)*data);
#endif
    return data;
}

static void bmdma_addr_write(void *opaque, target_phys_addr_t addr,
                             uint64_t data, unsigned width)
{
    BMDMAState *bm = opaque;
    int shift = addr * 8;
    uint32_t mask = (1ULL << (width * 8)) - 1;

#ifdef DEBUG_IDE
    printf("%s: 0x%08x\n", __func__, (unsigned)data);
#endif
    bm->addr &= ~(mask << shift);
    bm->addr |= ((data & mask) << shift) & ~3;
}

MemoryRegionOps bmdma_addr_ioport_ops = {
    .read = bmdma_addr_read,
    .write = bmdma_addr_write,
    .endianness = DEVICE_LITTLE_ENDIAN,
};

static bool ide_bmdma_current_needed(void *opaque)
{
    BMDMAState *bm = opaque;

    return (bm->cur_prd_len != 0);
}

static bool ide_bmdma_status_needed(void *opaque)
{
    BMDMAState *bm = opaque;

    /* Older versions abused some bits in the status register for internal
     * error state. If any of these bits are set, we must add a subsection to
     * transfer the real status register */
    uint8_t abused_bits = BM_MIGRATION_COMPAT_STATUS_BITS;

    return ((bm->status & abused_bits) != 0);
}

static void ide_bmdma_pre_save(void *opaque)
{
    BMDMAState *bm = opaque;
    uint8_t abused_bits = BM_MIGRATION_COMPAT_STATUS_BITS;

    bm->migration_compat_status =
        (bm->status & ~abused_bits) | (bm->bus->error_status & abused_bits);
}

/* This function accesses bm->bus->error_status which is loaded only after
 * BMDMA itself. This is why the function is called from ide_pci_post_load
 * instead of being registered with VMState where it would run too early. */
static int ide_bmdma_post_load(void *opaque, int version_id)
{
    BMDMAState *bm = opaque;
    uint8_t abused_bits = BM_MIGRATION_COMPAT_STATUS_BITS;

    if (bm->status == 0) {
        bm->status = bm->migration_compat_status & ~abused_bits;
        bm->bus->error_status |= bm->migration_compat_status & abused_bits;
    }

    return 0;
}

static const VMStateDescription vmstate_bmdma_current = {
    .name = "ide bmdma_current",
    .version_id = 1,
    .minimum_version_id = 1,
    .minimum_version_id_old = 1,
    .fields      = (VMStateField []) {
        VMSTATE_UINT32(cur_addr, BMDMAState),
        VMSTATE_UINT32(cur_prd_last, BMDMAState),
        VMSTATE_UINT32(cur_prd_addr, BMDMAState),
        VMSTATE_UINT32(cur_prd_len, BMDMAState),
        VMSTATE_END_OF_LIST()
    }
};

const VMStateDescription vmstate_bmdma_status = {
    .name ="ide bmdma/status",
    .version_id = 1,
    .minimum_version_id = 1,
    .minimum_version_id_old = 1,
    .fields = (VMStateField []) {
        VMSTATE_UINT8(status, BMDMAState),
        VMSTATE_END_OF_LIST()
    }
};

static const VMStateDescription vmstate_bmdma = {
    .name = "ide bmdma",
    .version_id = 3,
    .minimum_version_id = 0,
    .minimum_version_id_old = 0,
    .pre_save  = ide_bmdma_pre_save,
    .fields      = (VMStateField []) {
        VMSTATE_UINT8(cmd, BMDMAState),
        VMSTATE_UINT8(migration_compat_status, BMDMAState),
        VMSTATE_UINT32(addr, BMDMAState),
        VMSTATE_INT64(sector_num, BMDMAState),
        VMSTATE_UINT32(nsector, BMDMAState),
        VMSTATE_UINT8(unit, BMDMAState),
        VMSTATE_END_OF_LIST()
    },
    .subsections = (VMStateSubsection []) {
        {
            .vmsd = &vmstate_bmdma_current,
            .needed = ide_bmdma_current_needed,
        }, {
            .vmsd = &vmstate_bmdma_status,
            .needed = ide_bmdma_status_needed,
        }, {
            /* empty */
        }
    }
};

static int ide_pci_post_load(void *opaque, int version_id)
{
    PCIIDEState *d = opaque;
    int i;

    for(i = 0; i < 2; i++) {
        /* current versions always store 0/1, but older version
           stored bigger values. We only need last bit */
        d->bmdma[i].unit &= 1;
        ide_bmdma_post_load(&d->bmdma[i], -1);
    }

    return 0;
}

const VMStateDescription vmstate_ide_pci = {
    .name = "ide",
    .version_id = 3,
    .minimum_version_id = 0,
    .minimum_version_id_old = 0,
    .post_load = ide_pci_post_load,
    .fields      = (VMStateField []) {
        VMSTATE_PCI_DEVICE(dev, PCIIDEState),
        VMSTATE_STRUCT_ARRAY(bmdma, PCIIDEState, 2, 0,
                             vmstate_bmdma, BMDMAState),
        VMSTATE_IDE_BUS_ARRAY(bus, PCIIDEState, 2),
        VMSTATE_IDE_DRIVES(bus[0].ifs, PCIIDEState),
        VMSTATE_IDE_DRIVES(bus[1].ifs, PCIIDEState),
        VMSTATE_END_OF_LIST()
    }
};

void pci_ide_create_devs(PCIDevice *dev, DriveInfo **hd_table)
{
    PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, dev);
    static const int bus[4]  = { 0, 0, 1, 1 };
    static const int unit[4] = { 0, 1, 0, 1 };
    int i;

    for (i = 0; i < 4; i++) {
        if (hd_table[i] == NULL)
            continue;
        ide_create_drive(d->bus+bus[i], unit[i], hd_table[i]);
    }
}

static const struct IDEDMAOps bmdma_ops = {
    .start_dma = bmdma_start_dma,
    .start_transfer = bmdma_start_transfer,
    .prepare_buf = bmdma_prepare_buf,
    .rw_buf = bmdma_rw_buf,
    .set_unit = bmdma_set_unit,
    .add_status = bmdma_add_status,
    .set_inactive = bmdma_set_inactive,
    .restart_cb = bmdma_restart_cb,
    .reset = bmdma_reset,
};

void bmdma_init(IDEBus *bus, BMDMAState *bm, PCIIDEState *d)
{
    qemu_irq *irq;

    if (bus->dma == &bm->dma) {
        return;
    }

    bm->dma.ops = &bmdma_ops;
    bus->dma = &bm->dma;
    bm->irq = bus->irq;
    irq = qemu_allocate_irqs(bmdma_irq, bm, 1);
    bus->irq = *irq;
    bm->pci_dev = d;
}
Commit	Line	Data
977e1244 GH	1	/*
	2	* QEMU IDE Emulation: PCI Bus support.
	3	*
	4	* Copyright (c) 2003 Fabrice Bellard
	5	* Copyright (c) 2006 Openedhand Ltd.
	6	*
	7	* Permission is hereby granted, free of charge, to any person obtaining a copy
	8	* of this software and associated documentation files (the "Software"), to deal
	9	* in the Software without restriction, including without limitation the rights
	10	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	11	* copies of the Software, and to permit persons to whom the Software is
	12	* furnished to do so, subject to the following conditions:
	13	*
	14	* The above copyright notice and this permission notice shall be included in
	15	* all copies or substantial portions of the Software.
	16	*
	17	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	18	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	19	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	20	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	21	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	22	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	23	* THE SOFTWARE.
	24	*/
59f2a787 GH	25	#include <hw/hw.h>
	26	#include <hw/pc.h>
	27	#include <hw/pci.h>
feef3102	28	#include <hw/isa.h>
977e1244	29	#include "block.h"
977e1244	30	#include "dma.h"
59f2a787	31
65c0f135	32	#include <hw/ide/pci.h>
977e1244	33
40a6238a AG	34	#define BMDMA_PAGE_SIZE 4096
	35
	36	static void bmdma_start_dma(IDEDMA dma, IDEState s,
	37	BlockDriverCompletionFunc *dma_cb)
	38	{
	39	BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);
	40
	41	bm->unit = s->unit;
	42	bm->dma_cb = dma_cb;
	43	bm->cur_prd_last = 0;
	44	bm->cur_prd_addr = 0;
	45	bm->cur_prd_len = 0;
	46	bm->sector_num = ide_get_sector(s);
	47	bm->nsector = s->nsector;
	48
	49	if (bm->status & BM_STATUS_DMAING) {
	50	bm->dma_cb(bmdma_active_if(bm), 0);
	51	}
	52	}
	53
	54	/* return 0 if buffer completed */
	55	static int bmdma_prepare_buf(IDEDMA *dma, int is_write)
	56	{
	57	BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);
	58	IDEState *s = bmdma_active_if(bm);
	59	struct {
	60	uint32_t addr;
	61	uint32_t size;
	62	} prd;
	63	int l, len;
	64
	65	qemu_sglist_init(&s->sg, s->nsector / (BMDMA_PAGE_SIZE / 512) + 1);
	66	s->io_buffer_size = 0;
	67	for(;;) {
	68	if (bm->cur_prd_len == 0) {
	69	/* end of table (with a fail safe of one page) */
	70	if (bm->cur_prd_last \|\|
	71	(bm->cur_addr - bm->addr) >= BMDMA_PAGE_SIZE)
	72	return s->io_buffer_size != 0;
	73	cpu_physical_memory_read(bm->cur_addr, (uint8_t *)&prd, 8);
	74	bm->cur_addr += 8;
	75	prd.addr = le32_to_cpu(prd.addr);
	76	prd.size = le32_to_cpu(prd.size);
	77	len = prd.size & 0xfffe;
	78	if (len == 0)
	79	len = 0x10000;
	80	bm->cur_prd_len = len;
	81	bm->cur_prd_addr = prd.addr;
	82	bm->cur_prd_last = (prd.size & 0x80000000);
	83	}
	84	l = bm->cur_prd_len;
	85	if (l > 0) {
	86	qemu_sglist_add(&s->sg, bm->cur_prd_addr, l);
	87	bm->cur_prd_addr += l;
	88	bm->cur_prd_len -= l;
	89	s->io_buffer_size += l;
	90	}
	91	}
	92	return 1;
	93	}
	94
	95	/* return 0 if buffer completed */
	96	static int bmdma_rw_buf(IDEDMA *dma, int is_write)
	97	{
98	BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);
99	IDEState *s = bmdma_active_if(bm);
100	struct {
101	uint32_t addr;
102	uint32_t size;
103	} prd;
104	int l, len;
105
106	for(;;) {
107	l = s->io_buffer_size - s->io_buffer_index;
108	if (l <= 0)
109	break;
110	if (bm->cur_prd_len == 0) {
111	/* end of table (with a fail safe of one page) */
112	if (bm->cur_prd_last \|\|
113	(bm->cur_addr - bm->addr) >= BMDMA_PAGE_SIZE)
114	return 0;
115	cpu_physical_memory_read(bm->cur_addr, (uint8_t *)&prd, 8);
116	bm->cur_addr += 8;
117	prd.addr = le32_to_cpu(prd.addr);
118	prd.size = le32_to_cpu(prd.size);
119	len = prd.size & 0xfffe;
120	if (len == 0)
121	len = 0x10000;
122	bm->cur_prd_len = len;
123	bm->cur_prd_addr = prd.addr;
124	bm->cur_prd_last = (prd.size & 0x80000000);
125	}
126	if (l > bm->cur_prd_len)
127	l = bm->cur_prd_len;
128	if (l > 0) {
129	if (is_write) {
130	cpu_physical_memory_write(bm->cur_prd_addr,
131	s->io_buffer + s->io_buffer_index, l);
132	} else {
133	cpu_physical_memory_read(bm->cur_prd_addr,
134	s->io_buffer + s->io_buffer_index, l);
135	}
136	bm->cur_prd_addr += l;
137	bm->cur_prd_len -= l;
138	s->io_buffer_index += l;
139	}
140	}
141	return 1;
142	}
143
144	static int bmdma_set_unit(IDEDMA *dma, int unit)
145	{
146	BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);
147	bm->unit = unit;
148
149	return 0;
150	}
151
152	static int bmdma_add_status(IDEDMA *dma, int status)
153	{
154	BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);
155	bm->status \|= status;
156
157	return 0;
158	}
159
160	static int bmdma_set_inactive(IDEDMA *dma)
161	{
162	BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);
163
164	bm->status &= ~BM_STATUS_DMAING;
165	bm->dma_cb = NULL;
166	bm->unit = -1;
167
168	return 0;
169	}
170
4e1e0051	171	static void bmdma_restart_dma(BMDMAState *bm, enum ide_dma_cmd dma_cmd)
40a6238a AG	172	{
	173	IDEState *s = bmdma_active_if(bm);
	174
	175	ide_set_sector(s, bm->sector_num);
	176	s->io_buffer_index = 0;
	177	s->io_buffer_size = 0;
	178	s->nsector = bm->nsector;
4e1e0051	179	s->dma_cmd = dma_cmd;
40a6238a	180	bm->cur_addr = bm->addr;
cd369c46	181	bm->dma_cb = ide_dma_cb;
40a6238a AG	182	bmdma_start_dma(&bm->dma, s, bm->dma_cb);
	183	}
	184
def93791	185	/* TODO This should be common IDE code */
40a6238a AG	186	static void bmdma_restart_bh(void *opaque)
	187	{
	188	BMDMAState *bm = opaque;
def93791	189	IDEBus *bus = bm->bus;
40a6238a	190	int is_read;
ee752da7	191	int error_status;
40a6238a AG	192
	193	qemu_bh_delete(bm->bh);
	194	bm->bh = NULL;
	195
def93791 KW	196	if (bm->unit == (uint8_t) -1) {
	197	return;
	198	}
40a6238a	199
def93791 KW	200	is_read = !!(bus->error_status & BM_STATUS_RETRY_READ);
def93791 KW	201
ee752da7 KW	202	/* The error status must be cleared before resubmitting the request: The
	203	* request may fail again, and this case can only be distinguished if the
	204	* called function can set a new error status. */
	205	error_status = bus->error_status;
	206	bus->error_status = 0;
	207
	208	if (error_status & BM_STATUS_DMA_RETRY) {
	209	if (error_status & BM_STATUS_RETRY_TRIM) {
d353fb72 CH	210	bmdma_restart_dma(bm, IDE_DMA_TRIM);
d353fb72 CH	211	} else {
d353fb72 CH	212	bmdma_restart_dma(bm, is_read ? IDE_DMA_READ : IDE_DMA_WRITE);
d353fb72 CH	213	}
ee752da7	214	} else if (error_status & BM_STATUS_PIO_RETRY) {
40a6238a AG	215	if (is_read) {
	216	ide_sector_read(bmdma_active_if(bm));
	217	} else {
	218	ide_sector_write(bmdma_active_if(bm));
	219	}
ee752da7	220	} else if (error_status & BM_STATUS_RETRY_FLUSH) {
40a6238a AG	221	ide_flush_cache(bmdma_active_if(bm));
	222	}
	223	}
	224
1dfb4dd9	225	static void bmdma_restart_cb(void *opaque, int running, RunState state)
40a6238a AG	226	{
	227	IDEDMA *dma = opaque;
	228	BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);
	229
	230	if (!running)
	231	return;
	232
	233	if (!bm->bh) {
	234	bm->bh = qemu_bh_new(bmdma_restart_bh, &bm->dma);
	235	qemu_bh_schedule(bm->bh);
	236	}
	237	}
	238
	239	static void bmdma_cancel(BMDMAState *bm)
	240	{
	241	if (bm->status & BM_STATUS_DMAING) {
	242	/* cancel DMA request */
	243	bmdma_set_inactive(&bm->dma);
	244	}
	245	}
	246
	247	static int bmdma_reset(IDEDMA *dma)
	248	{
	249	BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);
	250
	251	#ifdef DEBUG_IDE
	252	printf("ide: dma_reset\n");
	253	#endif
	254	bmdma_cancel(bm);
	255	bm->cmd = 0;
	256	bm->status = 0;
	257	bm->addr = 0;
	258	bm->cur_addr = 0;
	259	bm->cur_prd_last = 0;
	260	bm->cur_prd_addr = 0;
	261	bm->cur_prd_len = 0;
	262	bm->sector_num = 0;
	263	bm->nsector = 0;
	264
	265	return 0;
	266	}
	267
	268	static int bmdma_start_transfer(IDEDMA *dma)
	269	{
	270	return 0;
	271	}
	272
	273	static void bmdma_irq(void *opaque, int n, int level)
	274	{
	275	BMDMAState *bm = opaque;
	276
	277	if (!level) {
	278	/* pass through lower */
	279	qemu_set_irq(bm->irq, level);
	280	return;
	281	}
	282
1635eecc	283	bm->status \|= BM_STATUS_INT;
40a6238a AG	284
	285	/* trigger the real irq */
	286	qemu_set_irq(bm->irq, level);
	287	}
	288
a9deb8c6	289	void bmdma_cmd_writeb(BMDMAState *bm, uint32_t val)
977e1244	290	{
977e1244 GH	291	#ifdef DEBUG_IDE
	292	printf("%s: 0x%08x\n", __func__, val);
	293	#endif
c29947bb KW	294
	295	/* Ignore writes to SSBM if it keeps the old value */
	296	if ((val & BM_CMD_START) != (bm->cmd & BM_CMD_START)) {
	297	if (!(val & BM_CMD_START)) {
	298	/*
	299	* We can't cancel Scatter Gather DMA in the middle of the
	300	* operation or a partial (not full) DMA transfer would reach
	301	* the storage so we wait for completion instead (we beahve
	302	* like if the DMA was completed by the time the guest trying
	303	* to cancel dma with bmdma_cmd_writeb with BM_CMD_START not
	304	* set).
	305	*
	306	* In the future we'll be able to safely cancel the I/O if the
	307	* whole DMA operation will be submitted to disk with a single
	308	* aio operation with preadv/pwritev.
	309	*/
40a6238a	310	if (bm->bus->dma->aiocb) {
c29947bb	311	qemu_aio_flush();
2860e3eb KW	312	assert(bm->bus->dma->aiocb == NULL);
2860e3eb KW	313	assert((bm->status & BM_STATUS_DMAING) == 0);
c29947bb KW	314	}
c29947bb KW	315	} else {
b76876e6	316	bm->cur_addr = bm->addr;
c29947bb KW	317	if (!(bm->status & BM_STATUS_DMAING)) {
	318	bm->status \|= BM_STATUS_DMAING;
	319	/* start dma transfer if possible */
	320	if (bm->dma_cb)
40a6238a	321	bm->dma_cb(bmdma_active_if(bm), 0);
c29947bb	322	}
953844d1	323	}
977e1244	324	}
c29947bb KW	325
c29947bb KW	326	bm->cmd = val & 0x09;
977e1244 GH	327	}
977e1244 GH	328
a9deb8c6 AK	329	static uint64_t bmdma_addr_read(void *opaque, target_phys_addr_t addr,
a9deb8c6 AK	330	unsigned width)
977e1244	331	{
a9deb8c6	332	BMDMAState *bm = opaque;
9fbef1ac	333	uint32_t mask = (1ULL << (width * 8)) - 1;
a9deb8c6	334	uint64_t data;
977e1244	335
a9deb8c6	336	data = (bm->addr >> (addr * 8)) & mask;
977e1244	337	#ifdef DEBUG_IDE
9fbef1ac	338	printf("%s: 0x%08x\n", __func__, (unsigned)*data);
977e1244	339	#endif
a9deb8c6	340	return data;
977e1244 GH	341	}
977e1244 GH	342
a9deb8c6 AK	343	static void bmdma_addr_write(void *opaque, target_phys_addr_t addr,
a9deb8c6 AK	344	uint64_t data, unsigned width)
977e1244	345	{
a9deb8c6	346	BMDMAState *bm = opaque;
9fbef1ac AK	347	int shift = addr * 8;
9fbef1ac AK	348	uint32_t mask = (1ULL << (width * 8)) - 1;
977e1244	349
977e1244	350	#ifdef DEBUG_IDE
9fbef1ac	351	printf("%s: 0x%08x\n", __func__, (unsigned)data);
977e1244	352	#endif
9fbef1ac AK	353	bm->addr &= ~(mask << shift);
9fbef1ac AK	354	bm->addr \|= ((data & mask) << shift) & ~3;
977e1244 GH	355	}
977e1244 GH	356
a9deb8c6	357	MemoryRegionOps bmdma_addr_ioport_ops = {
9fbef1ac AK	358	.read = bmdma_addr_read,
9fbef1ac AK	359	.write = bmdma_addr_write,
a9deb8c6	360	.endianness = DEVICE_LITTLE_ENDIAN,
9fbef1ac	361	};
977e1244	362
5ee84c33 JQ	363	static bool ide_bmdma_current_needed(void *opaque)
	364	{
	365	BMDMAState *bm = opaque;
	366
	367	return (bm->cur_prd_len != 0);
	368	}
	369
def93791 KW	370	static bool ide_bmdma_status_needed(void *opaque)
	371	{
	372	BMDMAState *bm = opaque;
	373
	374	/* Older versions abused some bits in the status register for internal
	375	* error state. If any of these bits are set, we must add a subsection to
	376	* transfer the real status register */
	377	uint8_t abused_bits = BM_MIGRATION_COMPAT_STATUS_BITS;
	378
	379	return ((bm->status & abused_bits) != 0);
	380	}
	381
	382	static void ide_bmdma_pre_save(void *opaque)
	383	{
	384	BMDMAState *bm = opaque;
	385	uint8_t abused_bits = BM_MIGRATION_COMPAT_STATUS_BITS;
	386
	387	bm->migration_compat_status =
	388	(bm->status & ~abused_bits) \| (bm->bus->error_status & abused_bits);
	389	}
	390
	391	/* This function accesses bm->bus->error_status which is loaded only after
	392	* BMDMA itself. This is why the function is called from ide_pci_post_load
	393	* instead of being registered with VMState where it would run too early. */
	394	static int ide_bmdma_post_load(void *opaque, int version_id)
	395	{
	396	BMDMAState *bm = opaque;
	397	uint8_t abused_bits = BM_MIGRATION_COMPAT_STATUS_BITS;
	398
	399	if (bm->status == 0) {
	400	bm->status = bm->migration_compat_status & ~abused_bits;
	401	bm->bus->error_status \|= bm->migration_compat_status & abused_bits;
	402	}
	403
	404	return 0;
	405	}
	406
5ee84c33 JQ	407	static const VMStateDescription vmstate_bmdma_current = {
	408	.name = "ide bmdma_current",
	409	.version_id = 1,
	410	.minimum_version_id = 1,
	411	.minimum_version_id_old = 1,
	412	.fields = (VMStateField []) {
	413	VMSTATE_UINT32(cur_addr, BMDMAState),
	414	VMSTATE_UINT32(cur_prd_last, BMDMAState),
	415	VMSTATE_UINT32(cur_prd_addr, BMDMAState),
	416	VMSTATE_UINT32(cur_prd_len, BMDMAState),
	417	VMSTATE_END_OF_LIST()
	418	}
	419	};
	420
def93791 KW	421	const VMStateDescription vmstate_bmdma_status = {
	422	.name ="ide bmdma/status",
	423	.version_id = 1,
	424	.minimum_version_id = 1,
	425	.minimum_version_id_old = 1,
	426	.fields = (VMStateField []) {
	427	VMSTATE_UINT8(status, BMDMAState),
	428	VMSTATE_END_OF_LIST()
	429	}
	430	};
5ee84c33	431
407a4f30 JQ	432	static const VMStateDescription vmstate_bmdma = {
407a4f30 JQ	433	.name = "ide bmdma",
57338424	434	.version_id = 3,
407a4f30 JQ	435	.minimum_version_id = 0,
407a4f30 JQ	436	.minimum_version_id_old = 0,
def93791	437	.pre_save = ide_bmdma_pre_save,
407a4f30 JQ	438	.fields = (VMStateField []) {
407a4f30 JQ	439	VMSTATE_UINT8(cmd, BMDMAState),
def93791	440	VMSTATE_UINT8(migration_compat_status, BMDMAState),
407a4f30 JQ	441	VMSTATE_UINT32(addr, BMDMAState),
	442	VMSTATE_INT64(sector_num, BMDMAState),
	443	VMSTATE_UINT32(nsector, BMDMAState),
	444	VMSTATE_UINT8(unit, BMDMAState),
	445	VMSTATE_END_OF_LIST()
5ee84c33 JQ	446	},
	447	.subsections = (VMStateSubsection []) {
	448	{
	449	.vmsd = &vmstate_bmdma_current,
	450	.needed = ide_bmdma_current_needed,
def93791 KW	451	}, {
	452	.vmsd = &vmstate_bmdma_status,
	453	.needed = ide_bmdma_status_needed,
5ee84c33 JQ	454	}, {
	455	/* empty */
	456	}
977e1244	457	}
407a4f30	458	};
977e1244	459
407a4f30	460	static int ide_pci_post_load(void *opaque, int version_id)
977e1244 GH	461	{
977e1244 GH	462	PCIIDEState *d = opaque;
407a4f30	463	int i;
977e1244	464
977e1244	465	for(i = 0; i < 2; i++) {
407a4f30 JQ	466	/* current versions always store 0/1, but older version
	467	stored bigger values. We only need last bit */
	468	d->bmdma[i].unit &= 1;
def93791	469	ide_bmdma_post_load(&d->bmdma[i], -1);
977e1244	470	}
def93791	471
977e1244 GH	472	return 0;
	473	}
	474
407a4f30 JQ	475	const VMStateDescription vmstate_ide_pci = {
407a4f30 JQ	476	.name = "ide",
57338424	477	.version_id = 3,
407a4f30 JQ	478	.minimum_version_id = 0,
	479	.minimum_version_id_old = 0,
	480	.post_load = ide_pci_post_load,
	481	.fields = (VMStateField []) {
	482	VMSTATE_PCI_DEVICE(dev, PCIIDEState),
	483	VMSTATE_STRUCT_ARRAY(bmdma, PCIIDEState, 2, 0,
	484	vmstate_bmdma, BMDMAState),
	485	VMSTATE_IDE_BUS_ARRAY(bus, PCIIDEState, 2),
	486	VMSTATE_IDE_DRIVES(bus[0].ifs, PCIIDEState),
	487	VMSTATE_IDE_DRIVES(bus[1].ifs, PCIIDEState),
	488	VMSTATE_END_OF_LIST()
	489	}
	490	};
	491
3e7e1558	492	void pci_ide_create_devs(PCIDevice dev, DriveInfo *hd_table)
feef3102 GH	493	{
	494	PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, dev);
	495	static const int bus[4] = { 0, 0, 1, 1 };
	496	static const int unit[4] = { 0, 1, 0, 1 };
	497	int i;
	498
	499	for (i = 0; i < 4; i++) {
	500	if (hd_table[i] == NULL)
	501	continue;
1f850f10	502	ide_create_drive(d->bus+bus[i], unit[i], hd_table[i]);
feef3102 GH	503	}
feef3102 GH	504	}
40a6238a AG	505
	506	static const struct IDEDMAOps bmdma_ops = {
	507	.start_dma = bmdma_start_dma,
	508	.start_transfer = bmdma_start_transfer,
	509	.prepare_buf = bmdma_prepare_buf,
	510	.rw_buf = bmdma_rw_buf,
	511	.set_unit = bmdma_set_unit,
	512	.add_status = bmdma_add_status,
	513	.set_inactive = bmdma_set_inactive,
	514	.restart_cb = bmdma_restart_cb,
	515	.reset = bmdma_reset,
	516	};
	517
a9deb8c6	518	void bmdma_init(IDEBus bus, BMDMAState bm, PCIIDEState *d)
40a6238a AG	519	{
	520	qemu_irq *irq;
	521
	522	if (bus->dma == &bm->dma) {
	523	return;
	524	}
	525
	526	bm->dma.ops = &bmdma_ops;
	527	bus->dma = &bm->dma;
	528	bm->irq = bus->irq;
	529	irq = qemu_allocate_irqs(bmdma_irq, bm, 1);
	530	bus->irq = *irq;
a9deb8c6	531	bm->pci_dev = d;
40a6238a	532	}