[qemu.git] / hw / sd / milkymist-memcard.c

/*
 *  QEMU model of the Milkymist SD Card Controller.
 *
 *  Copyright (c) 2010 Michael Walle <[email protected]>
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 *
 *
 * Specification available at:
 *   http://milkymist.walle.cc/socdoc/memcard.pdf
 */

#include "qemu/osdep.h"
#include "hw/hw.h"
#include "hw/sysbus.h"
#include "sysemu/sysemu.h"
#include "trace.h"
#include "qemu/error-report.h"
#include "sysemu/block-backend.h"
#include "sysemu/blockdev.h"
#include "hw/sd/sd.h"

enum {
    ENABLE_CMD_TX   = (1<<0),
    ENABLE_CMD_RX   = (1<<1),
    ENABLE_DAT_TX   = (1<<2),
    ENABLE_DAT_RX   = (1<<3),
};

enum {
    PENDING_CMD_TX   = (1<<0),
    PENDING_CMD_RX   = (1<<1),
    PENDING_DAT_TX   = (1<<2),
    PENDING_DAT_RX   = (1<<3),
};

enum {
    START_CMD_TX    = (1<<0),
    START_DAT_RX    = (1<<1),
};

enum {
    R_CLK2XDIV = 0,
    R_ENABLE,
    R_PENDING,
    R_START,
    R_CMD,
    R_DAT,
    R_MAX
};

#define TYPE_MILKYMIST_MEMCARD "milkymist-memcard"
#define MILKYMIST_MEMCARD(obj) \
    OBJECT_CHECK(MilkymistMemcardState, (obj), TYPE_MILKYMIST_MEMCARD)

struct MilkymistMemcardState {
    SysBusDevice parent_obj;

    MemoryRegion regs_region;
    SDState *card;

    int command_write_ptr;
    int response_read_ptr;
    int response_len;
    int ignore_next_cmd;
    int enabled;
    uint8_t command[6];
    uint8_t response[17];
    uint32_t regs[R_MAX];
};
typedef struct MilkymistMemcardState MilkymistMemcardState;

static void update_pending_bits(MilkymistMemcardState *s)
{
    /* transmits are instantaneous, thus tx pending bits are never set */
    s->regs[R_PENDING] = 0;
    /* if rx is enabled the corresponding pending bits are always set */
    if (s->regs[R_ENABLE] & ENABLE_CMD_RX) {
        s->regs[R_PENDING] |= PENDING_CMD_RX;
    }
    if (s->regs[R_ENABLE] & ENABLE_DAT_RX) {
        s->regs[R_PENDING] |= PENDING_DAT_RX;
    }
}

static void memcard_sd_command(MilkymistMemcardState *s)
{
    SDRequest req;

    req.cmd = s->command[0] & 0x3f;
    req.arg = (s->command[1] << 24) | (s->command[2] << 16)
              | (s->command[3] << 8) | s->command[4];
    req.crc = s->command[5];

    s->response[0] = req.cmd;
    s->response_len = sd_do_command(s->card, &req, s->response+1);
    s->response_read_ptr = 0;

    if (s->response_len == 16) {
        /* R2 response */
        s->response[0] = 0x3f;
        s->response_len += 1;
    } else if (s->response_len == 4) {
        /* no crc calculation, insert dummy byte */
        s->response[5] = 0;
        s->response_len += 2;
    }

    if (req.cmd == 0) {
        /* next write is a dummy byte to clock the initialization of the sd
         * card */
        s->ignore_next_cmd = 1;
    }
}

static uint64_t memcard_read(void *opaque, hwaddr addr,
                             unsigned size)
{
    MilkymistMemcardState *s = opaque;
    uint32_t r = 0;

    addr >>= 2;
    switch (addr) {
    case R_CMD:
        if (!s->enabled) {
            r = 0xff;
        } else {
            r = s->response[s->response_read_ptr++];
            if (s->response_read_ptr > s->response_len) {
                error_report("milkymist_memcard: "
                        "read more cmd bytes than available. Clipping.");
                s->response_read_ptr = 0;
            }
        }
        break;
    case R_DAT:
        if (!s->enabled) {
            r = 0xffffffff;
        } else {
            r = 0;
            r |= sd_read_data(s->card) << 24;
            r |= sd_read_data(s->card) << 16;
            r |= sd_read_data(s->card) << 8;
            r |= sd_read_data(s->card);
        }
        break;
    case R_CLK2XDIV:
    case R_ENABLE:
    case R_PENDING:
    case R_START:
        r = s->regs[addr];
        break;

    default:
        error_report("milkymist_memcard: read access to unknown register 0x"
                TARGET_FMT_plx, addr << 2);
        break;
    }

    trace_milkymist_memcard_memory_read(addr << 2, r);

    return r;
}

static void memcard_write(void *opaque, hwaddr addr, uint64_t value,
                          unsigned size)
{
    MilkymistMemcardState *s = opaque;

    trace_milkymist_memcard_memory_write(addr, value);

    addr >>= 2;
    switch (addr) {
    case R_PENDING:
        /* clear rx pending bits */
        s->regs[R_PENDING] &= ~(value & (PENDING_CMD_RX | PENDING_DAT_RX));
        update_pending_bits(s);
        break;
    case R_CMD:
        if (!s->enabled) {
            break;
        }
        if (s->ignore_next_cmd) {
            s->ignore_next_cmd = 0;
            break;
        }
        s->command[s->command_write_ptr] = value & 0xff;
        s->command_write_ptr = (s->command_write_ptr + 1) % 6;
        if (s->command_write_ptr == 0) {
            memcard_sd_command(s);
        }
        break;
    case R_DAT:
        if (!s->enabled) {
            break;
        }
        sd_write_data(s->card, (value >> 24) & 0xff);
        sd_write_data(s->card, (value >> 16) & 0xff);
        sd_write_data(s->card, (value >> 8) & 0xff);
        sd_write_data(s->card, value & 0xff);
        break;
    case R_ENABLE:
        s->regs[addr] = value;
        update_pending_bits(s);
        break;
    case R_CLK2XDIV:
    case R_START:
        s->regs[addr] = value;
        break;

    default:
        error_report("milkymist_memcard: write access to unknown register 0x"
                TARGET_FMT_plx, addr << 2);
        break;
    }
}

static const MemoryRegionOps memcard_mmio_ops = {
    .read = memcard_read,
    .write = memcard_write,
    .valid = {
        .min_access_size = 4,
        .max_access_size = 4,
    },
    .endianness = DEVICE_NATIVE_ENDIAN,
};

static void milkymist_memcard_reset(DeviceState *d)
{
    MilkymistMemcardState *s = MILKYMIST_MEMCARD(d);
    int i;

    s->command_write_ptr = 0;
    s->response_read_ptr = 0;
    s->response_len = 0;

    for (i = 0; i < R_MAX; i++) {
        s->regs[i] = 0;
    }
    /* Since we're still using the legacy SD API the card is not plugged
     * into any bus, and we must reset it manually.
     */
    device_reset(DEVICE(s->card));
}

static int milkymist_memcard_init(SysBusDevice *dev)
{
    MilkymistMemcardState *s = MILKYMIST_MEMCARD(dev);
    DriveInfo *dinfo;
    BlockBackend *blk;

    /* FIXME use a qdev drive property instead of drive_get_next() */
    dinfo = drive_get_next(IF_SD);
    blk = dinfo ? blk_by_legacy_dinfo(dinfo) : NULL;
    s->card = sd_init(blk, false);
    if (s->card == NULL) {
        return -1;
    }

    s->enabled = blk && blk_is_inserted(blk);

    memory_region_init_io(&s->regs_region, OBJECT(s), &memcard_mmio_ops, s,
            "milkymist-memcard", R_MAX * 4);
    sysbus_init_mmio(dev, &s->regs_region);

    return 0;
}

static const VMStateDescription vmstate_milkymist_memcard = {
    .name = "milkymist-memcard",
    .version_id = 1,
    .minimum_version_id = 1,
    .fields = (VMStateField[]) {
        VMSTATE_INT32(command_write_ptr, MilkymistMemcardState),
        VMSTATE_INT32(response_read_ptr, MilkymistMemcardState),
        VMSTATE_INT32(response_len, MilkymistMemcardState),
        VMSTATE_INT32(ignore_next_cmd, MilkymistMemcardState),
        VMSTATE_INT32(enabled, MilkymistMemcardState),
        VMSTATE_UINT8_ARRAY(command, MilkymistMemcardState, 6),
        VMSTATE_UINT8_ARRAY(response, MilkymistMemcardState, 17),
        VMSTATE_UINT32_ARRAY(regs, MilkymistMemcardState, R_MAX),
        VMSTATE_END_OF_LIST()
    }
};

static void milkymist_memcard_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);
    SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);

    k->init = milkymist_memcard_init;
    dc->reset = milkymist_memcard_reset;
    dc->vmsd = &vmstate_milkymist_memcard;
    /* Reason: init() method uses drive_get_next() */
    dc->user_creatable = false;
}

static const TypeInfo milkymist_memcard_info = {
    .name          = TYPE_MILKYMIST_MEMCARD,
    .parent        = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(MilkymistMemcardState),
    .class_init    = milkymist_memcard_class_init,
};

static void milkymist_memcard_register_types(void)
{
    type_register_static(&milkymist_memcard_info);
}

type_init(milkymist_memcard_register_types)
Commit	Line	Data
b4e37d98 MW	1	/*
	2	* QEMU model of the Milkymist SD Card Controller.
	3	*
	4	* Copyright (c) 2010 Michael Walle <[email protected]>
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
	9	* version 2 of the License, or (at your option) any later version.
	10	*
	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
	17	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
	18	*
	19	*
	20	* Specification available at:
6dbbe243	21	* http://milkymist.walle.cc/socdoc/memcard.pdf
b4e37d98 MW	22	*/
b4e37d98 MW	23
ea99dde1	24	#include "qemu/osdep.h"
83c9f4ca PB	25	#include "hw/hw.h"
83c9f4ca PB	26	#include "hw/sysbus.h"
9c17d615	27	#include "sysemu/sysemu.h"
b4e37d98	28	#include "trace.h"
1de7afc9	29	#include "qemu/error-report.h"
fa1d36df	30	#include "sysemu/block-backend.h"
9c17d615	31	#include "sysemu/blockdev.h"
e3382ef0	32	#include "hw/sd/sd.h"
b4e37d98 MW	33
	34	enum {
	35	ENABLE_CMD_TX = (1<<0),
	36	ENABLE_CMD_RX = (1<<1),
	37	ENABLE_DAT_TX = (1<<2),
	38	ENABLE_DAT_RX = (1<<3),
	39	};
	40
	41	enum {
	42	PENDING_CMD_TX = (1<<0),
	43	PENDING_CMD_RX = (1<<1),
	44	PENDING_DAT_TX = (1<<2),
	45	PENDING_DAT_RX = (1<<3),
	46	};
	47
	48	enum {
	49	START_CMD_TX = (1<<0),
	50	START_DAT_RX = (1<<1),
	51	};
	52
	53	enum {
	54	R_CLK2XDIV = 0,
	55	R_ENABLE,
	56	R_PENDING,
	57	R_START,
	58	R_CMD,
	59	R_DAT,
	60	R_MAX
	61	};
	62
7a239e46 AF	63	#define TYPE_MILKYMIST_MEMCARD "milkymist-memcard"
	64	#define MILKYMIST_MEMCARD(obj) \
	65	OBJECT_CHECK(MilkymistMemcardState, (obj), TYPE_MILKYMIST_MEMCARD)
	66
b4e37d98	67	struct MilkymistMemcardState {
7a239e46 AF	68	SysBusDevice parent_obj;
7a239e46 AF	69
8c85d15b	70	MemoryRegion regs_region;
b4e37d98 MW	71	SDState *card;
	72
	73	int command_write_ptr;
	74	int response_read_ptr;
	75	int response_len;
	76	int ignore_next_cmd;
	77	int enabled;
	78	uint8_t command[6];
	79	uint8_t response[17];
	80	uint32_t regs[R_MAX];
	81	};
	82	typedef struct MilkymistMemcardState MilkymistMemcardState;
	83
	84	static void update_pending_bits(MilkymistMemcardState *s)
	85	{
	86	/* transmits are instantaneous, thus tx pending bits are never set */
	87	s->regs[R_PENDING] = 0;
	88	/* if rx is enabled the corresponding pending bits are always set */
	89	if (s->regs[R_ENABLE] & ENABLE_CMD_RX) {
	90	s->regs[R_PENDING] \|= PENDING_CMD_RX;
	91	}
	92	if (s->regs[R_ENABLE] & ENABLE_DAT_RX) {
	93	s->regs[R_PENDING] \|= PENDING_DAT_RX;
	94	}
	95	}
	96
	97	static void memcard_sd_command(MilkymistMemcardState *s)
	98	{
	99	SDRequest req;
	100
	101	req.cmd = s->command[0] & 0x3f;
	102	req.arg = (s->command[1] << 24) \| (s->command[2] << 16)
	103	\| (s->command[3] << 8) \| s->command[4];
	104	req.crc = s->command[5];
	105
	106	s->response[0] = req.cmd;
	107	s->response_len = sd_do_command(s->card, &req, s->response+1);
	108	s->response_read_ptr = 0;
	109
	110	if (s->response_len == 16) {
	111	/* R2 response */
	112	s->response[0] = 0x3f;
	113	s->response_len += 1;
	114	} else if (s->response_len == 4) {
	115	/* no crc calculation, insert dummy byte */
	116	s->response[5] = 0;
	117	s->response_len += 2;
	118	}
	119
	120	if (req.cmd == 0) {
	121	/* next write is a dummy byte to clock the initialization of the sd
	122	* card */
	123	s->ignore_next_cmd = 1;
	124	}
	125	}
	126
a8170e5e	127	static uint64_t memcard_read(void *opaque, hwaddr addr,
8c85d15b	128	unsigned size)
b4e37d98 MW	129	{
	130	MilkymistMemcardState *s = opaque;
	131	uint32_t r = 0;
	132
	133	addr >>= 2;
	134	switch (addr) {
	135	case R_CMD:
	136	if (!s->enabled) {
	137	r = 0xff;
	138	} else {
	139	r = s->response[s->response_read_ptr++];
	140	if (s->response_read_ptr > s->response_len) {
	141	error_report("milkymist_memcard: "
	142	"read more cmd bytes than available. Clipping.");
	143	s->response_read_ptr = 0;
	144	}
	145	}
	146	break;
	147	case R_DAT:
	148	if (!s->enabled) {
	149	r = 0xffffffff;
	150	} else {
	151	r = 0;
	152	r \|= sd_read_data(s->card) << 24;
	153	r \|= sd_read_data(s->card) << 16;
	154	r \|= sd_read_data(s->card) << 8;
	155	r \|= sd_read_data(s->card);
	156	}
	157	break;
	158	case R_CLK2XDIV:
	159	case R_ENABLE:
	160	case R_PENDING:
	161	case R_START:
	162	r = s->regs[addr];
	163	break;
	164
	165	default:
dd3d6775	166	error_report("milkymist_memcard: read access to unknown register 0x"
b4e37d98 MW	167	TARGET_FMT_plx, addr << 2);
	168	break;
	169	}
	170
	171	trace_milkymist_memcard_memory_read(addr << 2, r);
	172
	173	return r;
	174	}
	175
a8170e5e	176	static void memcard_write(void *opaque, hwaddr addr, uint64_t value,
8c85d15b	177	unsigned size)
b4e37d98 MW	178	{
	179	MilkymistMemcardState *s = opaque;
	180
	181	trace_milkymist_memcard_memory_write(addr, value);
	182
	183	addr >>= 2;
	184	switch (addr) {
	185	case R_PENDING:
	186	/* clear rx pending bits */
	187	s->regs[R_PENDING] &= ~(value & (PENDING_CMD_RX \| PENDING_DAT_RX));
	188	update_pending_bits(s);
	189	break;
	190	case R_CMD:
	191	if (!s->enabled) {
	192	break;
	193	}
	194	if (s->ignore_next_cmd) {
	195	s->ignore_next_cmd = 0;
	196	break;
	197	}
	198	s->command[s->command_write_ptr] = value & 0xff;
	199	s->command_write_ptr = (s->command_write_ptr + 1) % 6;
	200	if (s->command_write_ptr == 0) {
	201	memcard_sd_command(s);
	202	}
	203	break;
	204	case R_DAT:
	205	if (!s->enabled) {
	206	break;
	207	}
	208	sd_write_data(s->card, (value >> 24) & 0xff);
	209	sd_write_data(s->card, (value >> 16) & 0xff);
	210	sd_write_data(s->card, (value >> 8) & 0xff);
	211	sd_write_data(s->card, value & 0xff);
	212	break;
	213	case R_ENABLE:
	214	s->regs[addr] = value;
	215	update_pending_bits(s);
	216	break;
	217	case R_CLK2XDIV:
	218	case R_START:
	219	s->regs[addr] = value;
	220	break;
	221
	222	default:
dd3d6775	223	error_report("milkymist_memcard: write access to unknown register 0x"
b4e37d98 MW	224	TARGET_FMT_plx, addr << 2);
	225	break;
	226	}
	227	}
	228
8c85d15b MW	229	static const MemoryRegionOps memcard_mmio_ops = {
	230	.read = memcard_read,
	231	.write = memcard_write,
	232	.valid = {
	233	.min_access_size = 4,
	234	.max_access_size = 4,
	235	},
	236	.endianness = DEVICE_NATIVE_ENDIAN,
b4e37d98 MW	237	};
	238
	239	static void milkymist_memcard_reset(DeviceState *d)
	240	{
7a239e46	241	MilkymistMemcardState *s = MILKYMIST_MEMCARD(d);
b4e37d98 MW	242	int i;
	243
	244	s->command_write_ptr = 0;
	245	s->response_read_ptr = 0;
	246	s->response_len = 0;
	247
	248	for (i = 0; i < R_MAX; i++) {
	249	s->regs[i] = 0;
	250	}
16bf0e0e PM	251	/* Since we're still using the legacy SD API the card is not plugged
	252	* into any bus, and we must reset it manually.
	253	*/
	254	device_reset(DEVICE(s->card));
b4e37d98 MW	255	}
	256
	257	static int milkymist_memcard_init(SysBusDevice *dev)
	258	{
7a239e46	259	MilkymistMemcardState *s = MILKYMIST_MEMCARD(dev);
b4e37d98	260	DriveInfo *dinfo;
4be74634	261	BlockBackend *blk;
b4e37d98	262
af9e40aa	263	/* FIXME use a qdev drive property instead of drive_get_next() */
b4e37d98	264	dinfo = drive_get_next(IF_SD);
4be74634 MA	265	blk = dinfo ? blk_by_legacy_dinfo(dinfo) : NULL;
4be74634 MA	266	s->card = sd_init(blk, false);
4f8a066b KW	267	if (s->card == NULL) {
	268	return -1;
	269	}
	270
4be74634	271	s->enabled = blk && blk_is_inserted(blk);
b4e37d98	272
29776739	273	memory_region_init_io(&s->regs_region, OBJECT(s), &memcard_mmio_ops, s,
8c85d15b	274	"milkymist-memcard", R_MAX * 4);
750ecd44	275	sysbus_init_mmio(dev, &s->regs_region);
b4e37d98 MW	276
	277	return 0;
	278	}
	279
	280	static const VMStateDescription vmstate_milkymist_memcard = {
	281	.name = "milkymist-memcard",
	282	.version_id = 1,
	283	.minimum_version_id = 1,
35d08458	284	.fields = (VMStateField[]) {
b4e37d98 MW	285	VMSTATE_INT32(command_write_ptr, MilkymistMemcardState),
	286	VMSTATE_INT32(response_read_ptr, MilkymistMemcardState),
	287	VMSTATE_INT32(response_len, MilkymistMemcardState),
	288	VMSTATE_INT32(ignore_next_cmd, MilkymistMemcardState),
	289	VMSTATE_INT32(enabled, MilkymistMemcardState),
	290	VMSTATE_UINT8_ARRAY(command, MilkymistMemcardState, 6),
	291	VMSTATE_UINT8_ARRAY(response, MilkymistMemcardState, 17),
	292	VMSTATE_UINT32_ARRAY(regs, MilkymistMemcardState, R_MAX),
	293	VMSTATE_END_OF_LIST()
	294	}
	295	};
	296
999e12bb AL	297	static void milkymist_memcard_class_init(ObjectClass klass, void data)
999e12bb AL	298	{
39bffca2	299	DeviceClass *dc = DEVICE_CLASS(klass);
999e12bb AL	300	SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
	301
	302	k->init = milkymist_memcard_init;
39bffca2 AL	303	dc->reset = milkymist_memcard_reset;
39bffca2 AL	304	dc->vmsd = &vmstate_milkymist_memcard;
9f9bdf43	305	/* Reason: init() method uses drive_get_next() */
e90f2a8c	306	dc->user_creatable = false;
999e12bb AL	307	}
999e12bb AL	308
8c43a6f0	309	static const TypeInfo milkymist_memcard_info = {
7a239e46	310	.name = TYPE_MILKYMIST_MEMCARD,
39bffca2 AL	311	.parent = TYPE_SYS_BUS_DEVICE,
	312	.instance_size = sizeof(MilkymistMemcardState),
	313	.class_init = milkymist_memcard_class_init,
b4e37d98 MW	314	};
b4e37d98 MW	315
83f7d43a	316	static void milkymist_memcard_register_types(void)
b4e37d98	317	{
39bffca2	318	type_register_static(&milkymist_memcard_info);
b4e37d98 MW	319	}
b4e37d98 MW	320
83f7d43a	321	type_init(milkymist_memcard_register_types)