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5fafdf24 | 1 | /* |
502a5395 PB |
2 | * ARM Versatile/PB PCI host controller |
3 | * | |
0027b06d | 4 | * Copyright (c) 2006-2009 CodeSourcery. |
502a5395 PB |
5 | * Written by Paul Brook |
6 | * | |
7 | * This code is licenced under the LGPL. | |
8 | */ | |
9 | ||
0027b06d | 10 | #include "sysbus.h" |
87ecb68b | 11 | #include "pci.h" |
b6243d99 | 12 | #include "pci_host.h" |
0027b06d PB |
13 | |
14 | typedef struct { | |
15 | SysBusDevice busdev; | |
16 | qemu_irq irq[4]; | |
17 | int realview; | |
18 | int mem_config; | |
19 | } PCIVPBState; | |
502a5395 | 20 | |
c227f099 | 21 | static inline uint32_t vpb_pci_config_addr(target_phys_addr_t addr) |
502a5395 | 22 | { |
80b3ada7 | 23 | return addr & 0xffffff; |
502a5395 PB |
24 | } |
25 | ||
c227f099 | 26 | static void pci_vpb_config_writeb (void *opaque, target_phys_addr_t addr, |
502a5395 PB |
27 | uint32_t val) |
28 | { | |
29 | pci_data_write(opaque, vpb_pci_config_addr (addr), val, 1); | |
30 | } | |
31 | ||
c227f099 | 32 | static void pci_vpb_config_writew (void *opaque, target_phys_addr_t addr, |
502a5395 PB |
33 | uint32_t val) |
34 | { | |
502a5395 PB |
35 | pci_data_write(opaque, vpb_pci_config_addr (addr), val, 2); |
36 | } | |
37 | ||
c227f099 | 38 | static void pci_vpb_config_writel (void *opaque, target_phys_addr_t addr, |
502a5395 PB |
39 | uint32_t val) |
40 | { | |
502a5395 PB |
41 | pci_data_write(opaque, vpb_pci_config_addr (addr), val, 4); |
42 | } | |
43 | ||
c227f099 | 44 | static uint32_t pci_vpb_config_readb (void *opaque, target_phys_addr_t addr) |
502a5395 PB |
45 | { |
46 | uint32_t val; | |
47 | val = pci_data_read(opaque, vpb_pci_config_addr (addr), 1); | |
48 | return val; | |
49 | } | |
50 | ||
c227f099 | 51 | static uint32_t pci_vpb_config_readw (void *opaque, target_phys_addr_t addr) |
502a5395 PB |
52 | { |
53 | uint32_t val; | |
54 | val = pci_data_read(opaque, vpb_pci_config_addr (addr), 2); | |
502a5395 PB |
55 | return val; |
56 | } | |
57 | ||
c227f099 | 58 | static uint32_t pci_vpb_config_readl (void *opaque, target_phys_addr_t addr) |
502a5395 PB |
59 | { |
60 | uint32_t val; | |
61 | val = pci_data_read(opaque, vpb_pci_config_addr (addr), 4); | |
502a5395 PB |
62 | return val; |
63 | } | |
64 | ||
d60efc6b | 65 | static CPUWriteMemoryFunc * const pci_vpb_config_write[] = { |
502a5395 PB |
66 | &pci_vpb_config_writeb, |
67 | &pci_vpb_config_writew, | |
68 | &pci_vpb_config_writel, | |
69 | }; | |
70 | ||
d60efc6b | 71 | static CPUReadMemoryFunc * const pci_vpb_config_read[] = { |
502a5395 PB |
72 | &pci_vpb_config_readb, |
73 | &pci_vpb_config_readw, | |
74 | &pci_vpb_config_readl, | |
75 | }; | |
76 | ||
d2b59317 PB |
77 | static int pci_vpb_map_irq(PCIDevice *d, int irq_num) |
78 | { | |
79 | return irq_num; | |
80 | } | |
81 | ||
5d4e84c8 | 82 | static void pci_vpb_set_irq(void *opaque, int irq_num, int level) |
502a5395 | 83 | { |
5d4e84c8 JQ |
84 | qemu_irq *pic = opaque; |
85 | ||
97aff481 | 86 | qemu_set_irq(pic[irq_num], level); |
502a5395 PB |
87 | } |
88 | ||
c227f099 | 89 | static void pci_vpb_map(SysBusDevice *dev, target_phys_addr_t base) |
502a5395 | 90 | { |
0027b06d PB |
91 | PCIVPBState *s = (PCIVPBState *)dev; |
92 | /* Selfconfig area. */ | |
93 | cpu_register_physical_memory(base + 0x01000000, 0x1000000, s->mem_config); | |
94 | /* Normal config area. */ | |
95 | cpu_register_physical_memory(base + 0x02000000, 0x1000000, s->mem_config); | |
96 | ||
97 | if (s->realview) { | |
98 | /* IO memory area. */ | |
968d683c | 99 | isa_mmio_init(base + 0x03000000, 0x00100000); |
0027b06d PB |
100 | } |
101 | } | |
102 | ||
81a322d4 | 103 | static int pci_vpb_init(SysBusDevice *dev) |
0027b06d PB |
104 | { |
105 | PCIVPBState *s = FROM_SYSBUS(PCIVPBState, dev); | |
106 | PCIBus *bus; | |
97aff481 | 107 | int i; |
e69954b9 | 108 | |
97aff481 | 109 | for (i = 0; i < 4; i++) { |
0027b06d | 110 | sysbus_init_irq(dev, &s->irq[i]); |
e69954b9 | 111 | } |
02e2da45 PB |
112 | bus = pci_register_bus(&dev->qdev, "pci", |
113 | pci_vpb_set_irq, pci_vpb_map_irq, s->irq, | |
520128bd | 114 | PCI_DEVFN(11, 0), 4); |
0027b06d | 115 | |
502a5395 PB |
116 | /* ??? Register memory space. */ |
117 | ||
1eed09cb | 118 | s->mem_config = cpu_register_io_memory(pci_vpb_config_read, |
2507c12a | 119 | pci_vpb_config_write, bus, |
387c3e96 | 120 | DEVICE_LITTLE_ENDIAN); |
0027b06d | 121 | sysbus_init_mmio_cb(dev, 0x04000000, pci_vpb_map); |
e69954b9 | 122 | |
0027b06d | 123 | pci_create_simple(bus, -1, "versatile_pci_host"); |
81a322d4 | 124 | return 0; |
0027b06d | 125 | } |
e69954b9 | 126 | |
81a322d4 | 127 | static int pci_realview_init(SysBusDevice *dev) |
0027b06d PB |
128 | { |
129 | PCIVPBState *s = FROM_SYSBUS(PCIVPBState, dev); | |
130 | s->realview = 1; | |
81a322d4 | 131 | return pci_vpb_init(dev); |
0027b06d | 132 | } |
502a5395 | 133 | |
81a322d4 | 134 | static int versatile_pci_host_init(PCIDevice *d) |
0027b06d | 135 | { |
deb54399 | 136 | pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_XILINX); |
e69954b9 | 137 | /* Both boards have the same device ID. Oh well. */ |
a770dc7e | 138 | pci_config_set_device_id(d->config, PCI_DEVICE_ID_XILINX_XC2VP30); |
a408b1de MT |
139 | pci_set_word(d->config + PCI_STATUS, |
140 | PCI_STATUS_66MHZ | PCI_STATUS_DEVSEL_MEDIUM); | |
173a543b | 141 | pci_config_set_class(d->config, PCI_CLASS_PROCESSOR_CO); |
01764fe0 | 142 | pci_set_byte(d->config + PCI_LATENCY_TIMER, 0x10); |
81a322d4 | 143 | return 0; |
0027b06d | 144 | } |
502a5395 | 145 | |
0aab0d3a GH |
146 | static PCIDeviceInfo versatile_pci_host_info = { |
147 | .qdev.name = "versatile_pci_host", | |
148 | .qdev.size = sizeof(PCIDevice), | |
149 | .init = versatile_pci_host_init, | |
150 | }; | |
151 | ||
0027b06d PB |
152 | static void versatile_pci_register_devices(void) |
153 | { | |
154 | sysbus_register_dev("versatile_pci", sizeof(PCIVPBState), pci_vpb_init); | |
155 | sysbus_register_dev("realview_pci", sizeof(PCIVPBState), | |
156 | pci_realview_init); | |
0aab0d3a | 157 | pci_qdev_register(&versatile_pci_host_info); |
502a5395 | 158 | } |
0027b06d PB |
159 | |
160 | device_init(versatile_pci_register_devices) |