[qemu.git] / hw / timer / allwinner-a10-pit.c

/*
 * Allwinner A10 timer device emulation
 *
 * Copyright (C) 2013 Li Guang
 * Written by Li Guang <[email protected]>
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License as published by the
 * Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
 * for more details.
 */

#include "hw/sysbus.h"
#include "sysemu/sysemu.h"
#include "hw/timer/allwinner-a10-pit.h"

static void a10_pit_update_irq(AwA10PITState *s)
{
    int i;

    for (i = 0; i < AW_A10_PIT_TIMER_NR; i++) {
        qemu_set_irq(s->irq[i], !!(s->irq_status & s->irq_enable & (1 << i)));
    }
}

static uint64_t a10_pit_read(void *opaque, hwaddr offset, unsigned size)
{
    AwA10PITState *s = AW_A10_PIT(opaque);
    uint8_t index;

    switch (offset) {
    case AW_A10_PIT_TIMER_IRQ_EN:
        return s->irq_enable;
    case AW_A10_PIT_TIMER_IRQ_ST:
        return s->irq_status;
    case AW_A10_PIT_TIMER_BASE ... AW_A10_PIT_TIMER_BASE_END:
        index = offset & 0xf0;
        index >>= 4;
        index -= 1;
        switch (offset & 0x0f) {
        case AW_A10_PIT_TIMER_CONTROL:
            return s->control[index];
        case AW_A10_PIT_TIMER_INTERVAL:
            return s->interval[index];
        case AW_A10_PIT_TIMER_COUNT:
            s->count[index] = ptimer_get_count(s->timer[index]);
            return s->count[index];
        default:
            qemu_log_mask(LOG_GUEST_ERROR,
                          "%s: Bad offset 0x%x\n",  __func__, (int)offset);
            break;
        }
    case AW_A10_PIT_WDOG_CONTROL:
        break;
    case AW_A10_PIT_WDOG_MODE:
        break;
    case AW_A10_PIT_COUNT_LO:
        return s->count_lo;
    case AW_A10_PIT_COUNT_HI:
        return s->count_hi;
    case AW_A10_PIT_COUNT_CTL:
        return s->count_ctl;
    default:
        qemu_log_mask(LOG_GUEST_ERROR,
                      "%s: Bad offset 0x%x\n",  __func__, (int)offset);
        break;
    }

    return 0;
}

static void a10_pit_set_freq(AwA10PITState *s, int index)
{
    uint32_t prescaler, source, source_freq;

    prescaler = 1 << extract32(s->control[index], 4, 3);
    source = extract32(s->control[index], 2, 2);
    source_freq = s->clk_freq[source];

    if (source_freq) {
        ptimer_set_freq(s->timer[index], source_freq / prescaler);
    } else {
        qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid clock source %u\n",
                      __func__, source);
    }
}

static void a10_pit_write(void *opaque, hwaddr offset, uint64_t value,
                            unsigned size)
{
     AwA10PITState *s = AW_A10_PIT(opaque);
     uint8_t index;

    switch (offset) {
    case AW_A10_PIT_TIMER_IRQ_EN:
        s->irq_enable = value;
        a10_pit_update_irq(s);
        break;
    case AW_A10_PIT_TIMER_IRQ_ST:
        s->irq_status &= ~value;
        a10_pit_update_irq(s);
        break;
    case AW_A10_PIT_TIMER_BASE ... AW_A10_PIT_TIMER_BASE_END:
        index = offset & 0xf0;
        index >>= 4;
        index -= 1;
        switch (offset & 0x0f) {
        case AW_A10_PIT_TIMER_CONTROL:
            s->control[index] = value;
            a10_pit_set_freq(s, index);
            if (s->control[index] & AW_A10_PIT_TIMER_RELOAD) {
                ptimer_set_count(s->timer[index], s->interval[index]);
            }
            if (s->control[index] & AW_A10_PIT_TIMER_EN) {
                int oneshot = 0;
                if (s->control[index] & AW_A10_PIT_TIMER_MODE) {
                    oneshot = 1;
                }
                ptimer_run(s->timer[index], oneshot);
            } else {
                ptimer_stop(s->timer[index]);
            }
            break;
        case AW_A10_PIT_TIMER_INTERVAL:
            s->interval[index] = value;
            ptimer_set_limit(s->timer[index], s->interval[index], 1);
            break;
        case AW_A10_PIT_TIMER_COUNT:
            s->count[index] = value;
            break;
        default:
            qemu_log_mask(LOG_GUEST_ERROR,
                          "%s: Bad offset 0x%x\n",  __func__, (int)offset);
        }
        break;
    case AW_A10_PIT_WDOG_CONTROL:
        s->watch_dog_control = value;
        break;
    case AW_A10_PIT_WDOG_MODE:
        s->watch_dog_mode = value;
        break;
    case AW_A10_PIT_COUNT_LO:
        s->count_lo = value;
        break;
    case AW_A10_PIT_COUNT_HI:
        s->count_hi = value;
        break;
    case AW_A10_PIT_COUNT_CTL:
        s->count_ctl = value;
        if (s->count_ctl & AW_A10_PIT_COUNT_RL_EN) {
            uint64_t  tmp_count = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);

            s->count_lo = tmp_count;
            s->count_hi = tmp_count >> 32;
            s->count_ctl &= ~AW_A10_PIT_COUNT_RL_EN;
        }
        if (s->count_ctl & AW_A10_PIT_COUNT_CLR_EN) {
            s->count_lo = 0;
            s->count_hi = 0;
            s->count_ctl &= ~AW_A10_PIT_COUNT_CLR_EN;
        }
        break;
    default:
        qemu_log_mask(LOG_GUEST_ERROR,
                      "%s: Bad offset 0x%x\n",  __func__, (int)offset);
        break;
    }
}

static const MemoryRegionOps a10_pit_ops = {
    .read = a10_pit_read,
    .write = a10_pit_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
};

static Property a10_pit_properties[] = {
    DEFINE_PROP_UINT32("clk0-freq", AwA10PITState, clk_freq[0], 0),
    DEFINE_PROP_UINT32("clk1-freq", AwA10PITState, clk_freq[1], 0),
    DEFINE_PROP_UINT32("clk2-freq", AwA10PITState, clk_freq[2], 0),
    DEFINE_PROP_UINT32("clk3-freq", AwA10PITState, clk_freq[3], 0),
    DEFINE_PROP_END_OF_LIST(),
};

static const VMStateDescription vmstate_a10_pit = {
    .name = "a10.pit",
    .version_id = 1,
    .minimum_version_id = 1,
    .fields = (VMStateField[]) {
        VMSTATE_UINT32(irq_enable, AwA10PITState),
        VMSTATE_UINT32(irq_status, AwA10PITState),
        VMSTATE_UINT32_ARRAY(control, AwA10PITState, AW_A10_PIT_TIMER_NR),
        VMSTATE_UINT32_ARRAY(interval, AwA10PITState, AW_A10_PIT_TIMER_NR),
        VMSTATE_UINT32_ARRAY(count, AwA10PITState, AW_A10_PIT_TIMER_NR),
        VMSTATE_UINT32(watch_dog_mode, AwA10PITState),
        VMSTATE_UINT32(watch_dog_control, AwA10PITState),
        VMSTATE_UINT32(count_lo, AwA10PITState),
        VMSTATE_UINT32(count_hi, AwA10PITState),
        VMSTATE_UINT32(count_ctl, AwA10PITState),
        VMSTATE_PTIMER_ARRAY(timer, AwA10PITState, AW_A10_PIT_TIMER_NR),
        VMSTATE_END_OF_LIST()
    }
};

static void a10_pit_reset(DeviceState *dev)
{
    AwA10PITState *s = AW_A10_PIT(dev);
    uint8_t i;

    s->irq_enable = 0;
    s->irq_status = 0;
    a10_pit_update_irq(s);

    for (i = 0; i < 6; i++) {
        s->control[i] = AW_A10_PIT_DEFAULT_CLOCK;
        s->interval[i] = 0;
        s->count[i] = 0;
        ptimer_stop(s->timer[i]);
        a10_pit_set_freq(s, i);
    }
    s->watch_dog_mode = 0;
    s->watch_dog_control = 0;
    s->count_lo = 0;
    s->count_hi = 0;
    s->count_ctl = 0;
}

static void a10_pit_timer_cb(void *opaque)
{
    AwA10TimerContext *tc = opaque;
    AwA10PITState *s = tc->container;
    uint8_t i = tc->index;

    if (s->control[i] & AW_A10_PIT_TIMER_EN) {
        s->irq_status |= 1 << i;
        if (s->control[i] & AW_A10_PIT_TIMER_MODE) {
            ptimer_stop(s->timer[i]);
            s->control[i] &= ~AW_A10_PIT_TIMER_EN;
        }
        a10_pit_update_irq(s);
    }
}

static void a10_pit_init(Object *obj)
{
    AwA10PITState *s = AW_A10_PIT(obj);
    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
    QEMUBH * bh[AW_A10_PIT_TIMER_NR];
    uint8_t i;

    for (i = 0; i < AW_A10_PIT_TIMER_NR; i++) {
        sysbus_init_irq(sbd, &s->irq[i]);
    }
    memory_region_init_io(&s->iomem, OBJECT(s), &a10_pit_ops, s,
                          TYPE_AW_A10_PIT, 0x400);
    sysbus_init_mmio(sbd, &s->iomem);

    for (i = 0; i < AW_A10_PIT_TIMER_NR; i++) {
        AwA10TimerContext *tc = &s->timer_context[i];

        tc->container = s;
        tc->index = i;
        bh[i] = qemu_bh_new(a10_pit_timer_cb, tc);
        s->timer[i] = ptimer_init(bh[i]);
    }
}

static void a10_pit_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);

    dc->reset = a10_pit_reset;
    dc->props = a10_pit_properties;
    dc->desc = "allwinner a10 timer";
    dc->vmsd = &vmstate_a10_pit;
}

static const TypeInfo a10_pit_info = {
    .name = TYPE_AW_A10_PIT,
    .parent = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(AwA10PITState),
    .instance_init = a10_pit_init,
    .class_init = a10_pit_class_init,
};

static void a10_register_types(void)
{
    type_register_static(&a10_pit_info);
}

type_init(a10_register_types);
Commit	Line	Data
3589de8c LG	1	/*
	2	* Allwinner A10 timer device emulation
	3	*
	4	* Copyright (C) 2013 Li Guang
	5	* Written by Li Guang <[email protected]>
	6	*
	7	* This program is free software; you can redistribute it and/or modify it
	8	* under the terms of the GNU General Public License as published by the
	9	* Free Software Foundation; either version 2 of the License, or
	10	* (at your option) any later version.
	11	*
	12	* This program is distributed in the hope that it will be useful, but WITHOUT
	13	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	14	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
	15	* for more details.
	16	*/
	17
	18	#include "hw/sysbus.h"
	19	#include "sysemu/sysemu.h"
	20	#include "hw/timer/allwinner-a10-pit.h"
	21
a63f9f85 BG	22	static void a10_pit_update_irq(AwA10PITState *s)
	23	{
	24	int i;
	25
	26	for (i = 0; i < AW_A10_PIT_TIMER_NR; i++) {
	27	qemu_set_irq(s->irq[i], !!(s->irq_status & s->irq_enable & (1 << i)));
	28	}
	29	}
	30
3589de8c LG	31	static uint64_t a10_pit_read(void *opaque, hwaddr offset, unsigned size)
	32	{
	33	AwA10PITState *s = AW_A10_PIT(opaque);
	34	uint8_t index;
	35
	36	switch (offset) {
	37	case AW_A10_PIT_TIMER_IRQ_EN:
	38	return s->irq_enable;
	39	case AW_A10_PIT_TIMER_IRQ_ST:
	40	return s->irq_status;
	41	case AW_A10_PIT_TIMER_BASE ... AW_A10_PIT_TIMER_BASE_END:
	42	index = offset & 0xf0;
	43	index >>= 4;
	44	index -= 1;
	45	switch (offset & 0x0f) {
	46	case AW_A10_PIT_TIMER_CONTROL:
	47	return s->control[index];
	48	case AW_A10_PIT_TIMER_INTERVAL:
	49	return s->interval[index];
	50	case AW_A10_PIT_TIMER_COUNT:
	51	s->count[index] = ptimer_get_count(s->timer[index]);
	52	return s->count[index];
	53	default:
	54	qemu_log_mask(LOG_GUEST_ERROR,
	55	"%s: Bad offset 0x%x\n", __func__, (int)offset);
	56	break;
	57	}
	58	case AW_A10_PIT_WDOG_CONTROL:
	59	break;
	60	case AW_A10_PIT_WDOG_MODE:
	61	break;
	62	case AW_A10_PIT_COUNT_LO:
	63	return s->count_lo;
	64	case AW_A10_PIT_COUNT_HI:
	65	return s->count_hi;
	66	case AW_A10_PIT_COUNT_CTL:
	67	return s->count_ctl;
	68	default:
	69	qemu_log_mask(LOG_GUEST_ERROR,
	70	"%s: Bad offset 0x%x\n", __func__, (int)offset);
	71	break;
	72	}
	73
	74	return 0;
	75	}
	76
286226a4 BG	77	static void a10_pit_set_freq(AwA10PITState *s, int index)
	78	{
	79	uint32_t prescaler, source, source_freq;
	80
	81	prescaler = 1 << extract32(s->control[index], 4, 3);
	82	source = extract32(s->control[index], 2, 2);
	83	source_freq = s->clk_freq[source];
	84
	85	if (source_freq) {
	86	ptimer_set_freq(s->timer[index], source_freq / prescaler);
	87	} else {
	88	qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid clock source %u\n",
	89	__func__, source);
	90	}
	91	}
	92
3589de8c LG	93	static void a10_pit_write(void *opaque, hwaddr offset, uint64_t value,
	94	unsigned size)
	95	{
	96	AwA10PITState *s = AW_A10_PIT(opaque);
	97	uint8_t index;
	98
	99	switch (offset) {
	100	case AW_A10_PIT_TIMER_IRQ_EN:
	101	s->irq_enable = value;
a63f9f85	102	a10_pit_update_irq(s);
3589de8c LG	103	break;
	104	case AW_A10_PIT_TIMER_IRQ_ST:
	105	s->irq_status &= ~value;
a63f9f85	106	a10_pit_update_irq(s);
3589de8c LG	107	break;
	108	case AW_A10_PIT_TIMER_BASE ... AW_A10_PIT_TIMER_BASE_END:
	109	index = offset & 0xf0;
	110	index >>= 4;
	111	index -= 1;
	112	switch (offset & 0x0f) {
	113	case AW_A10_PIT_TIMER_CONTROL:
	114	s->control[index] = value;
286226a4	115	a10_pit_set_freq(s, index);
3589de8c LG	116	if (s->control[index] & AW_A10_PIT_TIMER_RELOAD) {
	117	ptimer_set_count(s->timer[index], s->interval[index]);
	118	}
	119	if (s->control[index] & AW_A10_PIT_TIMER_EN) {
	120	int oneshot = 0;
	121	if (s->control[index] & AW_A10_PIT_TIMER_MODE) {
	122	oneshot = 1;
	123	}
	124	ptimer_run(s->timer[index], oneshot);
	125	} else {
	126	ptimer_stop(s->timer[index]);
	127	}
	128	break;
	129	case AW_A10_PIT_TIMER_INTERVAL:
	130	s->interval[index] = value;
	131	ptimer_set_limit(s->timer[index], s->interval[index], 1);
	132	break;
	133	case AW_A10_PIT_TIMER_COUNT:
	134	s->count[index] = value;
	135	break;
	136	default:
	137	qemu_log_mask(LOG_GUEST_ERROR,
	138	"%s: Bad offset 0x%x\n", __func__, (int)offset);
	139	}
	140	break;
	141	case AW_A10_PIT_WDOG_CONTROL:
	142	s->watch_dog_control = value;
	143	break;
	144	case AW_A10_PIT_WDOG_MODE:
	145	s->watch_dog_mode = value;
	146	break;
	147	case AW_A10_PIT_COUNT_LO:
	148	s->count_lo = value;
	149	break;
	150	case AW_A10_PIT_COUNT_HI:
	151	s->count_hi = value;
	152	break;
	153	case AW_A10_PIT_COUNT_CTL:
	154	s->count_ctl = value;
	155	if (s->count_ctl & AW_A10_PIT_COUNT_RL_EN) {
	156	uint64_t tmp_count = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
	157
	158	s->count_lo = tmp_count;
	159	s->count_hi = tmp_count >> 32;
	160	s->count_ctl &= ~AW_A10_PIT_COUNT_RL_EN;
	161	}
	162	if (s->count_ctl & AW_A10_PIT_COUNT_CLR_EN) {
	163	s->count_lo = 0;
	164	s->count_hi = 0;
	165	s->count_ctl &= ~AW_A10_PIT_COUNT_CLR_EN;
	166	}
	167	break;
	168	default:
	169	qemu_log_mask(LOG_GUEST_ERROR,
	170	"%s: Bad offset 0x%x\n", __func__, (int)offset);
	171	break;
	172	}
	173	}
	174
	175	static const MemoryRegionOps a10_pit_ops = {
	176	.read = a10_pit_read,
	177	.write = a10_pit_write,
	178	.endianness = DEVICE_NATIVE_ENDIAN,
	179	};
180
286226a4 BG	181	static Property a10_pit_properties[] = {
	182	DEFINE_PROP_UINT32("clk0-freq", AwA10PITState, clk_freq[0], 0),
	183	DEFINE_PROP_UINT32("clk1-freq", AwA10PITState, clk_freq[1], 0),
	184	DEFINE_PROP_UINT32("clk2-freq", AwA10PITState, clk_freq[2], 0),
	185	DEFINE_PROP_UINT32("clk3-freq", AwA10PITState, clk_freq[3], 0),
	186	DEFINE_PROP_END_OF_LIST(),
	187	};
	188
3589de8c LG	189	static const VMStateDescription vmstate_a10_pit = {
	190	.name = "a10.pit",
	191	.version_id = 1,
	192	.minimum_version_id = 1,
3589de8c LG	193	.fields = (VMStateField[]) {
	194	VMSTATE_UINT32(irq_enable, AwA10PITState),
	195	VMSTATE_UINT32(irq_status, AwA10PITState),
	196	VMSTATE_UINT32_ARRAY(control, AwA10PITState, AW_A10_PIT_TIMER_NR),
	197	VMSTATE_UINT32_ARRAY(interval, AwA10PITState, AW_A10_PIT_TIMER_NR),
	198	VMSTATE_UINT32_ARRAY(count, AwA10PITState, AW_A10_PIT_TIMER_NR),
	199	VMSTATE_UINT32(watch_dog_mode, AwA10PITState),
	200	VMSTATE_UINT32(watch_dog_control, AwA10PITState),
	201	VMSTATE_UINT32(count_lo, AwA10PITState),
	202	VMSTATE_UINT32(count_hi, AwA10PITState),
	203	VMSTATE_UINT32(count_ctl, AwA10PITState),
	204	VMSTATE_PTIMER_ARRAY(timer, AwA10PITState, AW_A10_PIT_TIMER_NR),
	205	VMSTATE_END_OF_LIST()
	206	}
	207	};
	208
	209	static void a10_pit_reset(DeviceState *dev)
	210	{
	211	AwA10PITState *s = AW_A10_PIT(dev);
	212	uint8_t i;
	213
	214	s->irq_enable = 0;
	215	s->irq_status = 0;
a63f9f85 BG	216	a10_pit_update_irq(s);
a63f9f85 BG	217
3589de8c LG	218	for (i = 0; i < 6; i++) {
	219	s->control[i] = AW_A10_PIT_DEFAULT_CLOCK;
	220	s->interval[i] = 0;
	221	s->count[i] = 0;
	222	ptimer_stop(s->timer[i]);
286226a4	223	a10_pit_set_freq(s, i);
3589de8c LG	224	}
	225	s->watch_dog_mode = 0;
	226	s->watch_dog_control = 0;
	227	s->count_lo = 0;
	228	s->count_hi = 0;
	229	s->count_ctl = 0;
	230	}
	231
	232	static void a10_pit_timer_cb(void *opaque)
	233	{
323a8771 BG	234	AwA10TimerContext *tc = opaque;
	235	AwA10PITState *s = tc->container;
	236	uint8_t i = tc->index;
3589de8c	237
323a8771 BG	238	if (s->control[i] & AW_A10_PIT_TIMER_EN) {
	239	s->irq_status \|= 1 << i;
	240	if (s->control[i] & AW_A10_PIT_TIMER_MODE) {
	241	ptimer_stop(s->timer[i]);
	242	s->control[i] &= ~AW_A10_PIT_TIMER_EN;
3589de8c	243	}
a63f9f85	244	a10_pit_update_irq(s);
3589de8c LG	245	}
	246	}
	247
	248	static void a10_pit_init(Object *obj)
	249	{
	250	AwA10PITState *s = AW_A10_PIT(obj);
	251	SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
	252	QEMUBH * bh[AW_A10_PIT_TIMER_NR];
	253	uint8_t i;
	254
	255	for (i = 0; i < AW_A10_PIT_TIMER_NR; i++) {
	256	sysbus_init_irq(sbd, &s->irq[i]);
	257	}
	258	memory_region_init_io(&s->iomem, OBJECT(s), &a10_pit_ops, s,
	259	TYPE_AW_A10_PIT, 0x400);
	260	sysbus_init_mmio(sbd, &s->iomem);
	261
	262	for (i = 0; i < AW_A10_PIT_TIMER_NR; i++) {
323a8771 BG	263	AwA10TimerContext *tc = &s->timer_context[i];
	264
	265	tc->container = s;
	266	tc->index = i;
	267	bh[i] = qemu_bh_new(a10_pit_timer_cb, tc);
3589de8c	268	s->timer[i] = ptimer_init(bh[i]);
3589de8c LG	269	}
	270	}
	271
	272	static void a10_pit_class_init(ObjectClass klass, void data)
	273	{
	274	DeviceClass *dc = DEVICE_CLASS(klass);
	275
	276	dc->reset = a10_pit_reset;
286226a4	277	dc->props = a10_pit_properties;
3589de8c LG	278	dc->desc = "allwinner a10 timer";
	279	dc->vmsd = &vmstate_a10_pit;
	280	}
	281
	282	static const TypeInfo a10_pit_info = {
	283	.name = TYPE_AW_A10_PIT,
	284	.parent = TYPE_SYS_BUS_DEVICE,
	285	.instance_size = sizeof(AwA10PITState),
	286	.instance_init = a10_pit_init,
	287	.class_init = a10_pit_class_init,
	288	};
	289
	290	static void a10_register_types(void)
	291	{
	292	type_register_static(&a10_pit_info);
	293	}
	294
	295	type_init(a10_register_types);