]> Git Repo - qemu.git/blame - hw/i2c/core.c
block: Connect BlockBackend to BlockDriverState
[qemu.git] / hw / i2c / core.c
CommitLineData
5fafdf24 1/*
0ff596d0
PB
2 * QEMU I2C bus interface.
3 *
4 * Copyright (c) 2007 CodeSourcery.
5 * Written by Paul Brook
6 *
8e31bf38 7 * This code is licensed under the LGPL.
0ff596d0
PB
8 */
9
0d09e41a 10#include "hw/i2c/i2c.h"
0ff596d0 11
a5c82852 12struct I2CBus
0ff596d0 13{
02e2da45 14 BusState qbus;
9e07bdf8
AL
15 I2CSlave *current_dev;
16 I2CSlave *dev;
5b7f5327 17 uint8_t saved_address;
0ff596d0
PB
18};
19
3cb75a7c
PB
20static Property i2c_props[] = {
21 DEFINE_PROP_UINT8("address", struct I2CSlave, address, 0),
22 DEFINE_PROP_END_OF_LIST(),
23};
24
0d936928 25#define TYPE_I2C_BUS "i2c-bus"
a5c82852 26#define I2C_BUS(obj) OBJECT_CHECK(I2CBus, (obj), TYPE_I2C_BUS)
0d936928
AL
27
28static const TypeInfo i2c_bus_info = {
29 .name = TYPE_I2C_BUS,
30 .parent = TYPE_BUS,
a5c82852 31 .instance_size = sizeof(I2CBus),
10c4c98a
GH
32};
33
8d0eb050 34static void i2c_bus_pre_save(void *opaque)
c701b35b 35{
a5c82852 36 I2CBus *bus = opaque;
c701b35b 37
8d0eb050 38 bus->saved_address = bus->current_dev ? bus->current_dev->address : -1;
c701b35b
PB
39}
40
8d0eb050 41static int i2c_bus_post_load(void *opaque, int version_id)
c701b35b 42{
a5c82852 43 I2CBus *bus = opaque;
c701b35b
PB
44
45 /* The bus is loaded before attached devices, so load and save the
46 current device id. Devices will check themselves as loaded. */
c701b35b 47 bus->current_dev = NULL;
c701b35b
PB
48 return 0;
49}
50
8d0eb050
JQ
51static const VMStateDescription vmstate_i2c_bus = {
52 .name = "i2c_bus",
53 .version_id = 1,
54 .minimum_version_id = 1,
8d0eb050
JQ
55 .pre_save = i2c_bus_pre_save,
56 .post_load = i2c_bus_post_load,
35d08458 57 .fields = (VMStateField[]) {
a5c82852 58 VMSTATE_UINT8(saved_address, I2CBus),
8d0eb050
JQ
59 VMSTATE_END_OF_LIST()
60 }
61};
62
0ff596d0 63/* Create a new I2C bus. */
a5c82852 64I2CBus *i2c_init_bus(DeviceState *parent, const char *name)
0ff596d0 65{
a5c82852 66 I2CBus *bus;
0ff596d0 67
fef7fbc9 68 bus = I2C_BUS(qbus_create(TYPE_I2C_BUS, parent, name));
0be71e32 69 vmstate_register(NULL, -1, &vmstate_i2c_bus, bus);
0ff596d0
PB
70 return bus;
71}
72
9e07bdf8 73void i2c_set_slave_address(I2CSlave *dev, uint8_t address)
0ff596d0
PB
74{
75 dev->address = address;
76}
77
78/* Return nonzero if bus is busy. */
a5c82852 79int i2c_bus_busy(I2CBus *bus)
0ff596d0
PB
80{
81 return bus->current_dev != NULL;
82}
83
4a2c8ac2 84/* Returns non-zero if the address is not valid. */
0ff596d0 85/* TODO: Make this handle multiple masters. */
a5c82852 86int i2c_start_transfer(I2CBus *bus, uint8_t address, int recv)
0ff596d0 87{
0866aca1 88 BusChild *kid;
9e07bdf8 89 I2CSlave *slave = NULL;
b5ea9327 90 I2CSlaveClass *sc;
0ff596d0 91
0866aca1
AL
92 QTAILQ_FOREACH(kid, &bus->qbus.children, sibling) {
93 DeviceState *qdev = kid->child;
8aae84a1 94 I2CSlave *candidate = I2C_SLAVE(qdev);
b3a21988
JR
95 if (candidate->address == address) {
96 slave = candidate;
0ff596d0 97 break;
b3a21988 98 }
0ff596d0
PB
99 }
100
b5ea9327 101 if (!slave) {
0ff596d0 102 return 1;
b5ea9327 103 }
0ff596d0 104
b5ea9327 105 sc = I2C_SLAVE_GET_CLASS(slave);
0ff596d0
PB
106 /* If the bus is already busy, assume this is a repeated
107 start condition. */
02e2da45 108 bus->current_dev = slave;
b5ea9327
AL
109 if (sc->event) {
110 sc->event(slave, recv ? I2C_START_RECV : I2C_START_SEND);
111 }
0ff596d0
PB
112 return 0;
113}
114
a5c82852 115void i2c_end_transfer(I2CBus *bus)
0ff596d0 116{
9e07bdf8 117 I2CSlave *dev = bus->current_dev;
b5ea9327 118 I2CSlaveClass *sc;
0ff596d0 119
b5ea9327 120 if (!dev) {
0ff596d0 121 return;
b5ea9327 122 }
0ff596d0 123
b5ea9327
AL
124 sc = I2C_SLAVE_GET_CLASS(dev);
125 if (sc->event) {
126 sc->event(dev, I2C_FINISH);
127 }
0ff596d0
PB
128
129 bus->current_dev = NULL;
130}
131
a5c82852 132int i2c_send(I2CBus *bus, uint8_t data)
0ff596d0 133{
9e07bdf8 134 I2CSlave *dev = bus->current_dev;
b5ea9327 135 I2CSlaveClass *sc;
0ff596d0 136
b5ea9327 137 if (!dev) {
0ff596d0 138 return -1;
b5ea9327 139 }
0ff596d0 140
b5ea9327
AL
141 sc = I2C_SLAVE_GET_CLASS(dev);
142 if (sc->send) {
143 return sc->send(dev, data);
144 }
145
146 return -1;
0ff596d0
PB
147}
148
a5c82852 149int i2c_recv(I2CBus *bus)
0ff596d0 150{
9e07bdf8 151 I2CSlave *dev = bus->current_dev;
b5ea9327 152 I2CSlaveClass *sc;
0ff596d0 153
b5ea9327 154 if (!dev) {
0ff596d0 155 return -1;
b5ea9327
AL
156 }
157
158 sc = I2C_SLAVE_GET_CLASS(dev);
159 if (sc->recv) {
160 return sc->recv(dev);
161 }
0ff596d0 162
b5ea9327 163 return -1;
0ff596d0
PB
164}
165
a5c82852 166void i2c_nack(I2CBus *bus)
0ff596d0 167{
9e07bdf8 168 I2CSlave *dev = bus->current_dev;
b5ea9327 169 I2CSlaveClass *sc;
0ff596d0 170
b5ea9327 171 if (!dev) {
0ff596d0 172 return;
b5ea9327 173 }
0ff596d0 174
b5ea9327
AL
175 sc = I2C_SLAVE_GET_CLASS(dev);
176 if (sc->event) {
177 sc->event(dev, I2C_NACK);
178 }
0ff596d0
PB
179}
180
bcbe8068 181static int i2c_slave_post_load(void *opaque, int version_id)
aa941b94 182{
9e07bdf8 183 I2CSlave *dev = opaque;
a5c82852 184 I2CBus *bus;
fef7fbc9 185 bus = I2C_BUS(qdev_get_parent_bus(DEVICE(dev)));
fe8de492
PB
186 if (bus->saved_address == dev->address) {
187 bus->current_dev = dev;
188 }
bcbe8068
JQ
189 return 0;
190}
191
1894839f 192const VMStateDescription vmstate_i2c_slave = {
9e07bdf8 193 .name = "I2CSlave",
bcbe8068
JQ
194 .version_id = 1,
195 .minimum_version_id = 1,
bcbe8068 196 .post_load = i2c_slave_post_load,
35d08458 197 .fields = (VMStateField[]) {
9e07bdf8 198 VMSTATE_UINT8(address, I2CSlave),
bcbe8068
JQ
199 VMSTATE_END_OF_LIST()
200 }
201};
202
d307af79 203static int i2c_slave_qdev_init(DeviceState *dev)
fe8de492 204{
8aae84a1 205 I2CSlave *s = I2C_SLAVE(dev);
b5ea9327 206 I2CSlaveClass *sc = I2C_SLAVE_GET_CLASS(s);
fe8de492 207
b5ea9327
AL
208 return sc->init(s);
209}
fe8de492 210
a5c82852 211DeviceState *i2c_create_slave(I2CBus *bus, const char *name, uint8_t addr)
fe8de492
PB
212{
213 DeviceState *dev;
214
02e2da45 215 dev = qdev_create(&bus->qbus, name);
5b7f5327 216 qdev_prop_set_uint8(dev, "address", addr);
e23a1b33 217 qdev_init_nofail(dev);
fe8de492 218 return dev;
aa941b94 219}
b5ea9327 220
39bffca2
AL
221static void i2c_slave_class_init(ObjectClass *klass, void *data)
222{
223 DeviceClass *k = DEVICE_CLASS(klass);
224 k->init = i2c_slave_qdev_init;
125ee0ed 225 set_bit(DEVICE_CATEGORY_MISC, k->categories);
0d936928 226 k->bus_type = TYPE_I2C_BUS;
bce54474 227 k->props = i2c_props;
39bffca2
AL
228}
229
8c43a6f0 230static const TypeInfo i2c_slave_type_info = {
b5ea9327
AL
231 .name = TYPE_I2C_SLAVE,
232 .parent = TYPE_DEVICE,
233 .instance_size = sizeof(I2CSlave),
234 .abstract = true,
235 .class_size = sizeof(I2CSlaveClass),
39bffca2 236 .class_init = i2c_slave_class_init,
b5ea9327
AL
237};
238
83f7d43a 239static void i2c_slave_register_types(void)
b5ea9327 240{
0d936928 241 type_register_static(&i2c_bus_info);
b5ea9327
AL
242 type_register_static(&i2c_slave_type_info);
243}
244
83f7d43a 245type_init(i2c_slave_register_types)
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