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Commit | Line | Data |
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2a6a4076 MA |
1 | #ifndef SH_INTC_H |
2 | #define SH_INTC_H | |
80f515e6 | 3 | |
96e2fc41 | 4 | #include "qemu-common.h" |
83c9f4ca | 5 | #include "hw/irq.h" |
96e2fc41 | 6 | |
80f515e6 AZ |
7 | typedef unsigned char intc_enum; |
8 | ||
9 | struct intc_vect { | |
10 | intc_enum enum_id; | |
11 | unsigned short vect; | |
12 | }; | |
13 | ||
14 | #define INTC_VECT(enum_id, vect) { enum_id, vect } | |
15 | ||
16 | struct intc_group { | |
17 | intc_enum enum_id; | |
18 | intc_enum enum_ids[32]; | |
19 | }; | |
20 | ||
001faf32 | 21 | #define INTC_GROUP(enum_id, ...) { enum_id, { __VA_ARGS__ } } |
80f515e6 AZ |
22 | |
23 | struct intc_mask_reg { | |
24 | unsigned long set_reg, clr_reg, reg_width; | |
25 | intc_enum enum_ids[32]; | |
26 | unsigned long value; | |
27 | }; | |
28 | ||
29 | struct intc_prio_reg { | |
30 | unsigned long set_reg, clr_reg, reg_width, field_width; | |
31 | intc_enum enum_ids[16]; | |
32 | unsigned long value; | |
33 | }; | |
34 | ||
b1503cda | 35 | #define _INTC_ARRAY(a) a, ARRAY_SIZE(a) |
80f515e6 AZ |
36 | |
37 | struct intc_source { | |
38 | unsigned short vect; | |
39 | intc_enum next_enum_id; | |
40 | ||
e96e2044 | 41 | int asserted; /* emulates the interrupt signal line from device to intc */ |
80f515e6 AZ |
42 | int enable_count; |
43 | int enable_max; | |
e96e2044 TS |
44 | int pending; /* emulates the result of signal and masking */ |
45 | struct intc_desc *parent; | |
80f515e6 AZ |
46 | }; |
47 | ||
48 | struct intc_desc { | |
b279e5ef BC |
49 | MemoryRegion iomem; |
50 | MemoryRegion *iomem_aliases; | |
96e2fc41 | 51 | qemu_irq *irqs; |
80f515e6 AZ |
52 | struct intc_source *sources; |
53 | int nr_sources; | |
54 | struct intc_mask_reg *mask_regs; | |
55 | int nr_mask_regs; | |
56 | struct intc_prio_reg *prio_regs; | |
57 | int nr_prio_regs; | |
e96e2044 | 58 | int pending; /* number of interrupt sources that has pending set */ |
80f515e6 AZ |
59 | }; |
60 | ||
e96e2044 | 61 | int sh_intc_get_pending_vector(struct intc_desc *desc, int imask); |
80f515e6 | 62 | struct intc_source *sh_intc_source(struct intc_desc *desc, intc_enum id); |
e96e2044 | 63 | void sh_intc_toggle_source(struct intc_source *source, |
7d37435b | 64 | int enable_adj, int assert_adj); |
80f515e6 AZ |
65 | |
66 | void sh_intc_register_sources(struct intc_desc *desc, | |
7d37435b PB |
67 | struct intc_vect *vectors, |
68 | int nr_vectors, | |
69 | struct intc_group *groups, | |
70 | int nr_groups); | |
80f515e6 | 71 | |
b279e5ef BC |
72 | int sh_intc_init(MemoryRegion *sysmem, |
73 | struct intc_desc *desc, | |
7d37435b PB |
74 | int nr_sources, |
75 | struct intc_mask_reg *mask_regs, | |
76 | int nr_mask_regs, | |
77 | struct intc_prio_reg *prio_regs, | |
78 | int nr_prio_regs); | |
80f515e6 | 79 | |
c6d86a33 AZ |
80 | void sh_intc_set_irl(void *opaque, int n, int level); |
81 | ||
2a6a4076 | 82 | #endif /* SH_INTC_H */ |