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1 | /* |
2 | * TriCore emulation for qemu: main CPU struct. | |
3 | * | |
4 | * Copyright (c) 2012-2014 Bastian Koppelmann C-Lab/University Paderborn | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | #if !defined(__TRICORE_CPU_H__) | |
20 | #define __TRICORE_CPU_H__ | |
21 | ||
22 | #include "tricore-defs.h" | |
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23 | #include "qemu-common.h" |
24 | #include "exec/cpu-defs.h" | |
25 | #include "fpu/softfloat.h" | |
26 | ||
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27 | #define CPUArchState struct CPUTriCoreState |
28 | ||
29 | struct CPUTriCoreState; | |
30 | ||
31 | struct tricore_boot_info; | |
32 | ||
33 | #define NB_MMU_MODES 3 | |
34 | ||
35 | typedef struct tricore_def_t tricore_def_t; | |
36 | ||
37 | typedef struct CPUTriCoreState CPUTriCoreState; | |
38 | struct CPUTriCoreState { | |
39 | /* GPR Register */ | |
40 | uint32_t gpr_a[16]; | |
41 | uint32_t gpr_d[16]; | |
42 | /* CSFR Register */ | |
43 | uint32_t PCXI; | |
44 | /* Frequently accessed PSW_USB bits are stored separately for efficiency. | |
45 | This contains all the other bits. Use psw_{read,write} to access | |
46 | the whole PSW. */ | |
47 | uint32_t PSW; | |
48 | ||
49 | /* PSW flag cache for faster execution | |
50 | */ | |
51 | uint32_t PSW_USB_C; | |
52 | uint32_t PSW_USB_V; /* Only if bit 31 set, then flag is set */ | |
53 | uint32_t PSW_USB_SV; /* Only if bit 31 set, then flag is set */ | |
54 | uint32_t PSW_USB_AV; /* Only if bit 31 set, then flag is set. */ | |
55 | uint32_t PSW_USB_SAV; /* Only if bit 31 set, then flag is set. */ | |
56 | ||
57 | uint32_t PC; | |
58 | uint32_t SYSCON; | |
59 | uint32_t CPU_ID; | |
60 | uint32_t BIV; | |
61 | uint32_t BTV; | |
62 | uint32_t ISP; | |
63 | uint32_t ICR; | |
64 | uint32_t FCX; | |
65 | uint32_t LCX; | |
66 | uint32_t COMPAT; | |
67 | ||
68 | /* Mem Protection Register */ | |
69 | uint32_t DPR0_0L; | |
70 | uint32_t DPR0_0U; | |
71 | uint32_t DPR0_1L; | |
72 | uint32_t DPR0_1U; | |
73 | uint32_t DPR0_2L; | |
74 | uint32_t DPR0_2U; | |
75 | uint32_t DPR0_3L; | |
76 | uint32_t DPR0_3U; | |
77 | ||
78 | uint32_t DPR1_0L; | |
79 | uint32_t DPR1_0U; | |
80 | uint32_t DPR1_1L; | |
81 | uint32_t DPR1_1U; | |
82 | uint32_t DPR1_2L; | |
83 | uint32_t DPR1_2U; | |
84 | uint32_t DPR1_3L; | |
85 | uint32_t DPR1_3U; | |
86 | ||
87 | uint32_t DPR2_0L; | |
88 | uint32_t DPR2_0U; | |
89 | uint32_t DPR2_1L; | |
90 | uint32_t DPR2_1U; | |
91 | uint32_t DPR2_2L; | |
92 | uint32_t DPR2_2U; | |
93 | uint32_t DPR2_3L; | |
94 | uint32_t DPR2_3U; | |
95 | ||
96 | uint32_t DPR3_0L; | |
97 | uint32_t DPR3_0U; | |
98 | uint32_t DPR3_1L; | |
99 | uint32_t DPR3_1U; | |
100 | uint32_t DPR3_2L; | |
101 | uint32_t DPR3_2U; | |
102 | uint32_t DPR3_3L; | |
103 | uint32_t DPR3_3U; | |
104 | ||
105 | uint32_t CPR0_0L; | |
106 | uint32_t CPR0_0U; | |
107 | uint32_t CPR0_1L; | |
108 | uint32_t CPR0_1U; | |
109 | uint32_t CPR0_2L; | |
110 | uint32_t CPR0_2U; | |
111 | uint32_t CPR0_3L; | |
112 | uint32_t CPR0_3U; | |
113 | ||
114 | uint32_t CPR1_0L; | |
115 | uint32_t CPR1_0U; | |
116 | uint32_t CPR1_1L; | |
117 | uint32_t CPR1_1U; | |
118 | uint32_t CPR1_2L; | |
119 | uint32_t CPR1_2U; | |
120 | uint32_t CPR1_3L; | |
121 | uint32_t CPR1_3U; | |
122 | ||
123 | uint32_t CPR2_0L; | |
124 | uint32_t CPR2_0U; | |
125 | uint32_t CPR2_1L; | |
126 | uint32_t CPR2_1U; | |
127 | uint32_t CPR2_2L; | |
128 | uint32_t CPR2_2U; | |
129 | uint32_t CPR2_3L; | |
130 | uint32_t CPR2_3U; | |
131 | ||
132 | uint32_t CPR3_0L; | |
133 | uint32_t CPR3_0U; | |
134 | uint32_t CPR3_1L; | |
135 | uint32_t CPR3_1U; | |
136 | uint32_t CPR3_2L; | |
137 | uint32_t CPR3_2U; | |
138 | uint32_t CPR3_3L; | |
139 | uint32_t CPR3_3U; | |
140 | ||
141 | uint32_t DPM0; | |
142 | uint32_t DPM1; | |
143 | uint32_t DPM2; | |
144 | uint32_t DPM3; | |
145 | ||
146 | uint32_t CPM0; | |
147 | uint32_t CPM1; | |
148 | uint32_t CPM2; | |
149 | uint32_t CPM3; | |
150 | ||
151 | /* Memory Management Registers */ | |
152 | uint32_t MMU_CON; | |
153 | uint32_t MMU_ASI; | |
154 | uint32_t MMU_TVA; | |
155 | uint32_t MMU_TPA; | |
156 | uint32_t MMU_TPX; | |
157 | uint32_t MMU_TFA; | |
158 | /* {1.3.1 only */ | |
159 | uint32_t BMACON; | |
160 | uint32_t SMACON; | |
161 | uint32_t DIEAR; | |
162 | uint32_t DIETR; | |
163 | uint32_t CCDIER; | |
164 | uint32_t MIECON; | |
165 | uint32_t PIEAR; | |
166 | uint32_t PIETR; | |
167 | uint32_t CCPIER; | |
168 | /*} */ | |
169 | /* Debug Registers */ | |
170 | uint32_t DBGSR; | |
171 | uint32_t EXEVT; | |
172 | uint32_t CREVT; | |
173 | uint32_t SWEVT; | |
174 | uint32_t TR0EVT; | |
175 | uint32_t TR1EVT; | |
176 | uint32_t DMS; | |
177 | uint32_t DCX; | |
178 | uint32_t DBGTCR; | |
179 | uint32_t CCTRL; | |
180 | uint32_t CCNT; | |
181 | uint32_t ICNT; | |
182 | uint32_t M1CNT; | |
183 | uint32_t M2CNT; | |
184 | uint32_t M3CNT; | |
185 | /* Floating Point Registers */ | |
996a729f | 186 | float_status fp_status; |
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187 | /* QEMU */ |
188 | int error_code; | |
189 | uint32_t hflags; /* CPU State */ | |
190 | ||
191 | CPU_COMMON | |
192 | ||
193 | /* Internal CPU feature flags. */ | |
194 | uint64_t features; | |
195 | ||
196 | const tricore_def_t *cpu_model; | |
197 | void *irq[8]; | |
198 | struct QEMUTimer *timer; /* Internal timer */ | |
199 | }; | |
200 | ||
201 | #define MASK_PCXI_PCPN 0xff000000 | |
202 | #define MASK_PCXI_PIE 0x00800000 | |
203 | #define MASK_PCXI_UL 0x00400000 | |
204 | #define MASK_PCXI_PCXS 0x000f0000 | |
205 | #define MASK_PCXI_PCXO 0x0000ffff | |
206 | ||
207 | #define MASK_PSW_USB 0xff000000 | |
208 | #define MASK_USB_C 0x80000000 | |
209 | #define MASK_USB_V 0x40000000 | |
210 | #define MASK_USB_SV 0x20000000 | |
211 | #define MASK_USB_AV 0x10000000 | |
212 | #define MASK_USB_SAV 0x08000000 | |
213 | #define MASK_PSW_PRS 0x00003000 | |
214 | #define MASK_PSW_IO 0x00000c00 | |
215 | #define MASK_PSW_IS 0x00000200 | |
216 | #define MASK_PSW_GW 0x00000100 | |
217 | #define MASK_PSW_CDE 0x00000080 | |
218 | #define MASK_PSW_CDC 0x0000007f | |
996a729f | 219 | #define MASK_PSW_FPU_RM 0x3000000 |
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220 | |
221 | #define MASK_SYSCON_PRO_TEN 0x2 | |
222 | #define MASK_SYSCON_FCD_SF 0x1 | |
223 | ||
224 | #define MASK_CPUID_MOD 0xffff0000 | |
225 | #define MASK_CPUID_MOD_32B 0x0000ff00 | |
226 | #define MASK_CPUID_REV 0x000000ff | |
227 | ||
228 | #define MASK_ICR_PIPN 0x00ff0000 | |
229 | #define MASK_ICR_IE 0x00000100 | |
230 | #define MASK_ICR_CCPN 0x000000ff | |
231 | ||
232 | #define MASK_FCX_FCXS 0x000f0000 | |
233 | #define MASK_FCX_FCXO 0x0000ffff | |
234 | ||
235 | #define MASK_LCX_LCXS 0x000f0000 | |
236 | #define MASK_LCX_LCX0 0x0000ffff | |
237 | ||
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238 | #define MASK_DBGSR_DE 0x1 |
239 | #define MASK_DBGSR_HALT 0x6 | |
240 | #define MASK_DBGSR_SUSP 0x10 | |
241 | #define MASK_DBGSR_PREVSUSP 0x20 | |
242 | #define MASK_DBGSR_PEVT 0x40 | |
243 | #define MASK_DBGSR_EVTSRC 0x1f00 | |
244 | ||
40a1f64b | 245 | #define TRICORE_HFLAG_KUU 0x3 |
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246 | #define TRICORE_HFLAG_UM0 0x00002 /* user mode-0 flag */ |
247 | #define TRICORE_HFLAG_UM1 0x00001 /* user mode-1 flag */ | |
248 | #define TRICORE_HFLAG_SM 0x00000 /* kernel mode flag */ | |
249 | ||
250 | enum tricore_features { | |
251 | TRICORE_FEATURE_13, | |
252 | TRICORE_FEATURE_131, | |
253 | TRICORE_FEATURE_16, | |
6d2afc8a | 254 | TRICORE_FEATURE_161, |
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255 | }; |
256 | ||
257 | static inline int tricore_feature(CPUTriCoreState *env, int feature) | |
258 | { | |
259 | return (env->features & (1ULL << feature)) != 0; | |
260 | } | |
261 | ||
262 | /* TriCore Traps Classes*/ | |
263 | enum { | |
264 | TRAPC_NONE = -1, | |
265 | TRAPC_MMU = 0, | |
266 | TRAPC_PROT = 1, | |
267 | TRAPC_INSN_ERR = 2, | |
268 | TRAPC_CTX_MNG = 3, | |
269 | TRAPC_SYSBUS = 4, | |
270 | TRAPC_ASSERT = 5, | |
271 | TRAPC_SYSCALL = 6, | |
272 | TRAPC_NMI = 7, | |
518d7fd2 | 273 | TRAPC_IRQ = 8 |
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274 | }; |
275 | ||
276 | /* Class 0 TIN */ | |
277 | enum { | |
278 | TIN0_VAF = 0, | |
279 | TIN0_VAP = 1, | |
280 | }; | |
281 | ||
282 | /* Class 1 TIN */ | |
283 | enum { | |
284 | TIN1_PRIV = 1, | |
285 | TIN1_MPR = 2, | |
286 | TIN1_MPW = 3, | |
287 | TIN1_MPX = 4, | |
288 | TIN1_MPP = 5, | |
289 | TIN1_MPN = 6, | |
290 | TIN1_GRWP = 7, | |
291 | }; | |
292 | ||
293 | /* Class 2 TIN */ | |
294 | enum { | |
295 | TIN2_IOPC = 1, | |
296 | TIN2_UOPC = 2, | |
297 | TIN2_OPD = 3, | |
298 | TIN2_ALN = 4, | |
299 | TIN2_MEM = 5, | |
300 | }; | |
301 | ||
302 | /* Class 3 TIN */ | |
303 | enum { | |
304 | TIN3_FCD = 1, | |
305 | TIN3_CDO = 2, | |
306 | TIN3_CDU = 3, | |
307 | TIN3_FCU = 4, | |
308 | TIN3_CSU = 5, | |
309 | TIN3_CTYP = 6, | |
310 | TIN3_NEST = 7, | |
311 | }; | |
312 | ||
313 | /* Class 4 TIN */ | |
314 | enum { | |
315 | TIN4_PSE = 1, | |
316 | TIN4_DSE = 2, | |
317 | TIN4_DAE = 3, | |
318 | TIN4_CAE = 4, | |
319 | TIN4_PIE = 5, | |
320 | TIN4_DIE = 6, | |
321 | }; | |
322 | ||
323 | /* Class 5 TIN */ | |
324 | enum { | |
325 | TIN5_OVF = 1, | |
326 | TIN5_SOVF = 1, | |
327 | }; | |
328 | ||
329 | /* Class 6 TIN | |
330 | * | |
331 | * Is always TIN6_SYS | |
332 | */ | |
333 | ||
334 | /* Class 7 TIN */ | |
335 | enum { | |
336 | TIN7_NMI = 0, | |
337 | }; | |
338 | ||
339 | uint32_t psw_read(CPUTriCoreState *env); | |
340 | void psw_write(CPUTriCoreState *env, uint32_t val); | |
341 | ||
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342 | void fpu_set_state(CPUTriCoreState *env); |
343 | ||
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344 | #include "cpu-qom.h" |
345 | #define MMU_USER_IDX 2 | |
346 | ||
347 | void tricore_cpu_list(FILE *f, fprintf_function cpu_fprintf); | |
348 | ||
349 | #define cpu_exec cpu_tricore_exec | |
350 | #define cpu_signal_handler cpu_tricore_signal_handler | |
351 | #define cpu_list tricore_cpu_list | |
352 | ||
97ed5ccd | 353 | static inline int cpu_mmu_index(CPUTriCoreState *env, bool ifetch) |
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354 | { |
355 | return 0; | |
356 | } | |
357 | ||
358 | ||
359 | ||
360 | #include "exec/cpu-all.h" | |
361 | ||
362 | enum { | |
363 | /* 1 bit to define user level / supervisor access */ | |
364 | ACCESS_USER = 0x00, | |
365 | ACCESS_SUPER = 0x01, | |
366 | /* 1 bit to indicate direction */ | |
367 | ACCESS_STORE = 0x02, | |
368 | /* Type of instruction that generated the access */ | |
369 | ACCESS_CODE = 0x10, /* Code fetch access */ | |
370 | ACCESS_INT = 0x20, /* Integer load/store access */ | |
371 | ACCESS_FLOAT = 0x30, /* floating point load/store access */ | |
372 | }; | |
373 | ||
374 | void cpu_state_reset(CPUTriCoreState *s); | |
ea3e9847 | 375 | int cpu_tricore_exec(CPUState *cpu); |
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376 | void tricore_tcg_init(void); |
377 | int cpu_tricore_signal_handler(int host_signum, void *pinfo, void *puc); | |
378 | ||
379 | static inline void cpu_get_tb_cpu_state(CPUTriCoreState *env, target_ulong *pc, | |
380 | target_ulong *cs_base, int *flags) | |
381 | { | |
382 | *pc = env->PC; | |
383 | *cs_base = 0; | |
384 | *flags = 0; | |
385 | } | |
386 | ||
387 | TriCoreCPU *cpu_tricore_init(const char *cpu_model); | |
388 | ||
2994fd96 | 389 | #define cpu_init(cpu_model) CPU(cpu_tricore_init(cpu_model)) |
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390 | |
391 | ||
392 | /* helpers.c */ | |
393 | int cpu_tricore_handle_mmu_fault(CPUState *cpu, target_ulong address, | |
394 | int rw, int mmu_idx); | |
395 | #define cpu_handle_mmu_fault cpu_tricore_handle_mmu_fault | |
396 | ||
397 | #include "exec/exec-all.h" | |
398 | ||
48e06fe0 | 399 | #endif /*__TRICORE_CPU_H__ */ |