[qemu.git] / hw / ide.h

#ifndef HW_IDE_H
#define HW_IDE_H

#include "qdev.h"

/* ide-isa.c */
void isa_ide_init(int iobase, int iobase2, qemu_irq irq,
                  DriveInfo *hd0, DriveInfo *hd1);

/* ide-pci.c */
void pci_cmd646_ide_init(PCIBus *bus, DriveInfo **hd_table,
                         int secondary_ide_enabled);
void pci_piix3_ide_init(PCIBus *bus, DriveInfo **hd_table, int devfn,
                        qemu_irq *pic);
void pci_piix4_ide_init(PCIBus *bus, DriveInfo **hd_table, int devfn,
                        qemu_irq *pic);

/* ide-macio.c */
int pmac_ide_init (DriveInfo **hd_table, qemu_irq irq,
		   void *dbdma, int channel, qemu_irq dma_irq);

/* ide-mmio.c */
void mmio_ide_init (target_phys_addr_t membase, target_phys_addr_t membase2,
                    qemu_irq irq, int shift,
                    DriveInfo *hd0, DriveInfo *hd1);

#endif /* HW_IDE_H */
Commit	Line	Data
ec82026c GH	1	#ifndef HW_IDE_H
	2	#define HW_IDE_H
	3
	4	#include "qdev.h"
	5
	6	/* ide-isa.c */
	7	void isa_ide_init(int iobase, int iobase2, qemu_irq irq,
f455e98c	8	DriveInfo hd0, DriveInfo hd1);
ec82026c	9
977e1244	10	/* ide-pci.c */
f455e98c	11	void pci_cmd646_ide_init(PCIBus bus, DriveInfo *hd_table,
977e1244	12	int secondary_ide_enabled);
f455e98c	13	void pci_piix3_ide_init(PCIBus bus, DriveInfo *hd_table, int devfn,
977e1244	14	qemu_irq *pic);
f455e98c	15	void pci_piix4_ide_init(PCIBus bus, DriveInfo *hd_table, int devfn,
977e1244 GH	16	qemu_irq *pic);
977e1244 GH	17
b8842209	18	/* ide-macio.c */
f455e98c	19	int pmac_ide_init (DriveInfo **hd_table, qemu_irq irq,
b8842209 GH	20	void *dbdma, int channel, qemu_irq dma_irq);
b8842209 GH	21
3d2bf4a1 GH	22	/* ide-mmio.c */
	23	void mmio_ide_init (target_phys_addr_t membase, target_phys_addr_t membase2,
	24	qemu_irq irq, int shift,
f455e98c	25	DriveInfo hd0, DriveInfo hd1);
3d2bf4a1	26
ec82026c	27	#endif /* HW_IDE_H */