[qemu.git] / hw / audio / pl041.c

/*
 * Arm PrimeCell PL041 Advanced Audio Codec Interface
 *
 * Copyright (c) 2011
 * Written by Mathieu Sonet - www.elasticsheep.com
 *
 * This code is licensed under the GPL.
 *
 * *****************************************************************
 *
 * This driver emulates the ARM AACI interface
 * connected to a LM4549 codec.
 *
 * Limitations:
 * - Supports only a playback on one channel (Versatile/Vexpress)
 * - Supports only one TX FIFO in compact-mode or non-compact mode.
 * - Supports playback of 12, 16, 18 and 20 bits samples.
 * - Record is not supported.
 * - The PL041 is hardwired to a LM4549 codec.
 *
 */

#include "qemu/osdep.h"
#include "hw/sysbus.h"
#include "qemu/log.h"

#include "pl041.h"
#include "lm4549.h"

#if 0
#define PL041_DEBUG_LEVEL 1
#endif

#if defined(PL041_DEBUG_LEVEL) && (PL041_DEBUG_LEVEL >= 1)
#define DBG_L1(fmt, ...) \
do { printf("pl041: " fmt , ## __VA_ARGS__); } while (0)
#else
#define DBG_L1(fmt, ...) \
do { } while (0)
#endif

#if defined(PL041_DEBUG_LEVEL) && (PL041_DEBUG_LEVEL >= 2)
#define DBG_L2(fmt, ...) \
do { printf("pl041: " fmt , ## __VA_ARGS__); } while (0)
#else
#define DBG_L2(fmt, ...) \
do { } while (0)
#endif


#define MAX_FIFO_DEPTH      (1024)
#define DEFAULT_FIFO_DEPTH  (8)

#define SLOT1_RW    (1 << 19)

/* This FIFO only stores 20-bit samples on 32-bit words.
   So its level is independent of the selected mode */
typedef struct {
    uint32_t level;
    uint32_t data[MAX_FIFO_DEPTH];
} pl041_fifo;

typedef struct {
    pl041_fifo tx_fifo;
    uint8_t tx_enabled;
    uint8_t tx_compact_mode;
    uint8_t tx_sample_size;

    pl041_fifo rx_fifo;
    uint8_t rx_enabled;
    uint8_t rx_compact_mode;
    uint8_t rx_sample_size;
} pl041_channel;

#define TYPE_PL041 "pl041"
#define PL041(obj) OBJECT_CHECK(PL041State, (obj), TYPE_PL041)

typedef struct PL041State {
    SysBusDevice parent_obj;

    MemoryRegion iomem;
    qemu_irq irq;

    uint32_t fifo_depth; /* FIFO depth in non-compact mode */

    pl041_regfile regs;
    pl041_channel fifo1;
    lm4549_state codec;
} PL041State;


static const unsigned char pl041_default_id[8] = {
    0x41, 0x10, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1
};

#if defined(PL041_DEBUG_LEVEL)
#define REGISTER(name, offset) #name,
static const char *pl041_regs_name[] = {
    #include "pl041.hx"
};
#undef REGISTER
#endif


#if defined(PL041_DEBUG_LEVEL)
static const char *get_reg_name(hwaddr offset)
{
    if (offset <= PL041_dr1_7) {
        return pl041_regs_name[offset >> 2];
    }

    return "unknown";
}
#endif

static uint8_t pl041_compute_periphid3(PL041State *s)
{
    uint8_t id3 = 1; /* One channel */

    /* Add the fifo depth information */
    switch (s->fifo_depth) {
    case 8:
        id3 |= 0 << 3;
        break;
    case 32:
        id3 |= 1 << 3;
        break;
    case 64:
        id3 |= 2 << 3;
        break;
    case 128:
        id3 |= 3 << 3;
        break;
    case 256:
        id3 |= 4 << 3;
        break;
    case 512:
        id3 |= 5 << 3;
        break;
    case 1024:
        id3 |= 6 << 3;
        break;
    case 2048:
        id3 |= 7 << 3;
        break;
    }

    return id3;
}

static void pl041_reset(PL041State *s)
{
    DBG_L1("pl041_reset\n");

    memset(&s->regs, 0x00, sizeof(pl041_regfile));

    s->regs.slfr = SL1TXEMPTY | SL2TXEMPTY | SL12TXEMPTY;
    s->regs.sr1 = TXFE | RXFE | TXHE;
    s->regs.isr1 = 0;

    memset(&s->fifo1, 0x00, sizeof(s->fifo1));
}


static void pl041_fifo1_write(PL041State *s, uint32_t value)
{
    pl041_channel *channel = &s->fifo1;
    pl041_fifo *fifo = &s->fifo1.tx_fifo;

    /* Push the value in the FIFO */
    if (channel->tx_compact_mode == 0) {
        /* Non-compact mode */

        if (fifo->level < s->fifo_depth) {
            /* Pad the value with 0 to obtain a 20-bit sample */
            switch (channel->tx_sample_size) {
            case 12:
                value = (value << 8) & 0xFFFFF;
                break;
            case 16:
                value = (value << 4) & 0xFFFFF;
                break;
            case 18:
                value = (value << 2) & 0xFFFFF;
                break;
            case 20:
            default:
                break;
            }

            /* Store the sample in the FIFO */
            fifo->data[fifo->level++] = value;
        }
#if defined(PL041_DEBUG_LEVEL)
        else {
            DBG_L1("fifo1 write: overrun\n");
        }
#endif
    } else {
        /* Compact mode */

        if ((fifo->level + 2) < s->fifo_depth) {
            uint32_t i = 0;
            uint32_t sample = 0;

            for (i = 0; i < 2; i++) {
                sample = value & 0xFFFF;
                value = value >> 16;

                /* Pad each sample with 0 to obtain a 20-bit sample */
                switch (channel->tx_sample_size) {
                case 12:
                    sample = sample << 8;
                    break;
                case 16:
                default:
                    sample = sample << 4;
                    break;
                }

                /* Store the sample in the FIFO */
                fifo->data[fifo->level++] = sample;
            }
        }
#if defined(PL041_DEBUG_LEVEL)
        else {
            DBG_L1("fifo1 write: overrun\n");
        }
#endif
    }

    /* Update the status register */
    if (fifo->level > 0) {
        s->regs.sr1 &= ~(TXUNDERRUN | TXFE);
    }

    if (fifo->level >= (s->fifo_depth / 2)) {
        s->regs.sr1 &= ~TXHE;
    }

    if (fifo->level >= s->fifo_depth) {
        s->regs.sr1 |= TXFF;
    }

    DBG_L2("fifo1_push sr1 = 0x%08x\n", s->regs.sr1);
}

static void pl041_fifo1_transmit(PL041State *s)
{
    pl041_channel *channel = &s->fifo1;
    pl041_fifo *fifo = &s->fifo1.tx_fifo;
    uint32_t slots = s->regs.txcr1 & TXSLOT_MASK;
    uint32_t written_samples;

    /* Check if FIFO1 transmit is enabled */
    if ((channel->tx_enabled) && (slots & (TXSLOT3 | TXSLOT4))) {
        if (fifo->level >= (s->fifo_depth / 2)) {
            int i;

            DBG_L1("Transfer FIFO level = %i\n", fifo->level);

            /* Try to transfer the whole FIFO */
            for (i = 0; i < (fifo->level / 2); i++) {
                uint32_t left = fifo->data[i * 2];
                uint32_t right = fifo->data[i * 2 + 1];

                 /* Transmit two 20-bit samples to the codec */
                if (lm4549_write_samples(&s->codec, left, right) == 0) {
                    DBG_L1("Codec buffer full\n");
                    break;
                }
            }

            written_samples = i * 2;
            if (written_samples > 0) {
                /* Update the FIFO level */
                fifo->level -= written_samples;

                /* Move back the pending samples to the start of the FIFO */
                for (i = 0; i < fifo->level; i++) {
                    fifo->data[i] = fifo->data[written_samples + i];
                }

                /* Update the status register */
                s->regs.sr1 &= ~TXFF;

                if (fifo->level <= (s->fifo_depth / 2)) {
                    s->regs.sr1 |= TXHE;
                }

                if (fifo->level == 0) {
                    s->regs.sr1 |= TXFE | TXUNDERRUN;
                    DBG_L1("Empty FIFO\n");
                }
            }
        }
    }
}

static void pl041_isr1_update(PL041State *s)
{
    /* Update ISR1 */
    if (s->regs.sr1 & TXUNDERRUN) {
        s->regs.isr1 |= URINTR;
    } else {
        s->regs.isr1 &= ~URINTR;
    }

    if (s->regs.sr1 & TXHE) {
        s->regs.isr1 |= TXINTR;
    } else {
        s->regs.isr1 &= ~TXINTR;
    }

    if (!(s->regs.sr1 & TXBUSY) && (s->regs.sr1 & TXFE)) {
        s->regs.isr1 |= TXCINTR;
    } else {
        s->regs.isr1 &= ~TXCINTR;
    }

    /* Update the irq state */
    qemu_set_irq(s->irq, ((s->regs.isr1 & s->regs.ie1) > 0) ? 1 : 0);
    DBG_L2("Set interrupt sr1 = 0x%08x isr1 = 0x%08x masked = 0x%08x\n",
           s->regs.sr1, s->regs.isr1, s->regs.isr1 & s->regs.ie1);
}

static void pl041_request_data(void *opaque)
{
    PL041State *s = (PL041State *)opaque;

    /* Trigger pending transfers */
    pl041_fifo1_transmit(s);
    pl041_isr1_update(s);
}

static uint64_t pl041_read(void *opaque, hwaddr offset,
                                unsigned size)
{
    PL041State *s = (PL041State *)opaque;
    int value;

    if ((offset >= PL041_periphid0) && (offset <= PL041_pcellid3)) {
        if (offset == PL041_periphid3) {
            value = pl041_compute_periphid3(s);
        } else {
            value = pl041_default_id[(offset - PL041_periphid0) >> 2];
        }

        DBG_L1("pl041_read [0x%08x] => 0x%08x\n", offset, value);
        return value;
    } else if (offset <= PL041_dr4_7) {
        value = *((uint32_t *)&s->regs + (offset >> 2));
    } else {
        DBG_L1("pl041_read: Reserved offset %x\n", (int)offset);
        return 0;
    }

    switch (offset) {
    case PL041_allints:
        value = s->regs.isr1 & 0x7F;
        break;
    }

    DBG_L1("pl041_read [0x%08x] %s => 0x%08x\n", offset,
           get_reg_name(offset), value);

    return value;
}

static void pl041_write(void *opaque, hwaddr offset,
                             uint64_t value, unsigned size)
{
    PL041State *s = (PL041State *)opaque;
    uint16_t control, data;
    uint32_t result;

    DBG_L1("pl041_write [0x%08x] %s <= 0x%08x\n", offset,
           get_reg_name(offset), (unsigned int)value);

    /* Write the register */
    if (offset <= PL041_dr4_7) {
        *((uint32_t *)&s->regs + (offset >> 2)) = value;
    } else {
        DBG_L1("pl041_write: Reserved offset %x\n", (int)offset);
        return;
    }

    /* Execute the actions */
    switch (offset) {
    case PL041_txcr1:
    {
        pl041_channel *channel = &s->fifo1;

        uint32_t txen = s->regs.txcr1 & TXEN;
        uint32_t tsize = (s->regs.txcr1 & TSIZE_MASK) >> TSIZE_MASK_BIT;
        uint32_t compact_mode = (s->regs.txcr1 & TXCOMPACT) ? 1 : 0;
#if defined(PL041_DEBUG_LEVEL)
        uint32_t slots = (s->regs.txcr1 & TXSLOT_MASK) >> TXSLOT_MASK_BIT;
        uint32_t txfen = (s->regs.txcr1 & TXFEN) > 0 ? 1 : 0;
#endif

        DBG_L1("=> txen = %i slots = 0x%01x tsize = %i compact = %i "
               "txfen = %i\n", txen, slots,  tsize, compact_mode, txfen);

        channel->tx_enabled = txen;
        channel->tx_compact_mode = compact_mode;

        switch (tsize) {
        case 0:
            channel->tx_sample_size = 16;
            break;
        case 1:
            channel->tx_sample_size = 18;
            break;
        case 2:
            channel->tx_sample_size = 20;
            break;
        case 3:
            channel->tx_sample_size = 12;
            break;
        }

        DBG_L1("TX enabled = %i\n", channel->tx_enabled);
        DBG_L1("TX compact mode = %i\n", channel->tx_compact_mode);
        DBG_L1("TX sample width = %i\n", channel->tx_sample_size);

        /* Check if compact mode is allowed with selected tsize */
        if (channel->tx_compact_mode == 1) {
            if ((channel->tx_sample_size == 18) ||
                (channel->tx_sample_size == 20)) {
                channel->tx_compact_mode = 0;
                DBG_L1("Compact mode not allowed with 18/20-bit sample size\n");
            }
        }

        break;
    }
    case PL041_sl1tx:
        s->regs.slfr &= ~SL1TXEMPTY;

        control = (s->regs.sl1tx >> 12) & 0x7F;
        data = (s->regs.sl2tx >> 4) & 0xFFFF;

        if ((s->regs.sl1tx & SLOT1_RW) == 0) {
            /* Write operation */
            lm4549_write(&s->codec, control, data);
        } else {
            /* Read operation */
            result = lm4549_read(&s->codec, control);

            /* Store the returned value */
            s->regs.sl1rx = s->regs.sl1tx & ~SLOT1_RW;
            s->regs.sl2rx = result << 4;

            s->regs.slfr &= ~(SL1RXBUSY | SL2RXBUSY);
            s->regs.slfr |= SL1RXVALID | SL2RXVALID;
        }
        break;

    case PL041_sl2tx:
        s->regs.sl2tx = value;
        s->regs.slfr &= ~SL2TXEMPTY;
        break;

    case PL041_intclr:
        DBG_L1("=> Clear interrupt intclr = 0x%08x isr1 = 0x%08x\n",
               s->regs.intclr, s->regs.isr1);

        if (s->regs.intclr & TXUEC1) {
            s->regs.sr1 &= ~TXUNDERRUN;
        }
        break;

    case PL041_maincr:
    {
#if defined(PL041_DEBUG_LEVEL)
        char debug[] = " AACIFE  SL1RXEN  SL1TXEN";
        if (!(value & AACIFE)) {
            debug[0] = '!';
        }
        if (!(value & SL1RXEN)) {
            debug[8] = '!';
        }
        if (!(value & SL1TXEN)) {
            debug[17] = '!';
        }
        DBG_L1("%s\n", debug);
#endif

        if ((s->regs.maincr & AACIFE) == 0) {
            pl041_reset(s);
        }
        break;
    }

    case PL041_dr1_0:
    case PL041_dr1_1:
    case PL041_dr1_2:
    case PL041_dr1_3:
        pl041_fifo1_write(s, value);
        break;
    }

    /* Transmit the FIFO content */
    pl041_fifo1_transmit(s);

    /* Update the ISR1 register */
    pl041_isr1_update(s);
}

static void pl041_device_reset(DeviceState *d)
{
    PL041State *s = PL041(d);

    pl041_reset(s);
}

static const MemoryRegionOps pl041_ops = {
    .read = pl041_read,
    .write = pl041_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
};

static void pl041_init(Object *obj)
{
    SysBusDevice *dev = SYS_BUS_DEVICE(obj);
    PL041State *s = PL041(dev);

    DBG_L1("pl041_init 0x%08x\n", (uint32_t)s);

    /* Connect the device to the sysbus */
    memory_region_init_io(&s->iomem, obj, &pl041_ops, s, "pl041", 0x1000);
    sysbus_init_mmio(dev, &s->iomem);
    sysbus_init_irq(dev, &s->irq);
}

static void pl041_realize(DeviceState *dev, Error **errp)
{
    PL041State *s = PL041(dev);

    /* Check the device properties */
    switch (s->fifo_depth) {
    case 8:
    case 32:
    case 64:
    case 128:
    case 256:
    case 512:
    case 1024:
    case 2048:
        break;
    case 16:
    default:
        /* NC FIFO depth of 16 is not allowed because its id bits in
           AACIPERIPHID3 overlap with the id for the default NC FIFO depth */
        qemu_log_mask(LOG_UNIMP,
                      "pl041: unsupported non-compact fifo depth [%i]\n",
                      s->fifo_depth);
    }

    /* Init the codec */
    lm4549_init(&s->codec, &pl041_request_data, (void *)s);
}

static const VMStateDescription vmstate_pl041_regfile = {
    .name = "pl041_regfile",
    .version_id = 1,
    .minimum_version_id = 1,
    .fields = (VMStateField[]) {
#define REGISTER(name, offset) VMSTATE_UINT32(name, pl041_regfile),
        #include "pl041.hx"
#undef REGISTER
        VMSTATE_END_OF_LIST()
    }
};

static const VMStateDescription vmstate_pl041_fifo = {
    .name = "pl041_fifo",
    .version_id = 1,
    .minimum_version_id = 1,
    .fields = (VMStateField[]) {
        VMSTATE_UINT32(level, pl041_fifo),
        VMSTATE_UINT32_ARRAY(data, pl041_fifo, MAX_FIFO_DEPTH),
        VMSTATE_END_OF_LIST()
    }
};

static const VMStateDescription vmstate_pl041_channel = {
    .name = "pl041_channel",
    .version_id = 1,
    .minimum_version_id = 1,
    .fields = (VMStateField[]) {
        VMSTATE_STRUCT(tx_fifo, pl041_channel, 0,
                       vmstate_pl041_fifo, pl041_fifo),
        VMSTATE_UINT8(tx_enabled, pl041_channel),
        VMSTATE_UINT8(tx_compact_mode, pl041_channel),
        VMSTATE_UINT8(tx_sample_size, pl041_channel),
        VMSTATE_STRUCT(rx_fifo, pl041_channel, 0,
                       vmstate_pl041_fifo, pl041_fifo),
        VMSTATE_UINT8(rx_enabled, pl041_channel),
        VMSTATE_UINT8(rx_compact_mode, pl041_channel),
        VMSTATE_UINT8(rx_sample_size, pl041_channel),
        VMSTATE_END_OF_LIST()
    }
};

static const VMStateDescription vmstate_pl041 = {
    .name = "pl041",
    .version_id = 1,
    .minimum_version_id = 1,
    .fields = (VMStateField[]) {
        VMSTATE_UINT32(fifo_depth, PL041State),
        VMSTATE_STRUCT(regs, PL041State, 0,
                       vmstate_pl041_regfile, pl041_regfile),
        VMSTATE_STRUCT(fifo1, PL041State, 0,
                       vmstate_pl041_channel, pl041_channel),
        VMSTATE_STRUCT(codec, PL041State, 0,
                       vmstate_lm4549_state, lm4549_state),
        VMSTATE_END_OF_LIST()
    }
};

static Property pl041_device_properties[] = {
    /* Non-compact FIFO depth property */
    DEFINE_PROP_UINT32("nc_fifo_depth", PL041State, fifo_depth,
                       DEFAULT_FIFO_DEPTH),
    DEFINE_PROP_END_OF_LIST(),
};

static void pl041_device_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);

    dc->realize = pl041_realize;
    set_bit(DEVICE_CATEGORY_SOUND, dc->categories);
    dc->reset = pl041_device_reset;
    dc->vmsd = &vmstate_pl041;
    dc->props = pl041_device_properties;
}

static const TypeInfo pl041_device_info = {
    .name          = TYPE_PL041,
    .parent        = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(PL041State),
    .instance_init = pl041_init,
    .class_init    = pl041_device_class_init,
};

static void pl041_register_types(void)
{
    type_register_static(&pl041_device_info);
}

type_init(pl041_register_types)
Commit	Line	Data
d028d02d MS	1	/*
	2	* Arm PrimeCell PL041 Advanced Audio Codec Interface
	3	*
	4	* Copyright (c) 2011
	5	* Written by Mathieu Sonet - www.elasticsheep.com
	6	*
4d8db4e4	7	* This code is licensed under the GPL.
d028d02d MS	8	*
	9	* *****************************************************************
	10	*
	11	* This driver emulates the ARM AACI interface
	12	* connected to a LM4549 codec.
	13	*
	14	* Limitations:
	15	* - Supports only a playback on one channel (Versatile/Vexpress)
	16	* - Supports only one TX FIFO in compact-mode or non-compact mode.
	17	* - Supports playback of 12, 16, 18 and 20 bits samples.
	18	* - Record is not supported.
	19	* - The PL041 is hardwired to a LM4549 codec.
	20	*
	21	*/
	22
6086a565	23	#include "qemu/osdep.h"
83c9f4ca	24	#include "hw/sysbus.h"
03dd024f	25	#include "qemu/log.h"
d028d02d	26
47b43a1f PB	27	#include "pl041.h"
47b43a1f PB	28	#include "lm4549.h"
d028d02d MS	29
	30	#if 0
	31	#define PL041_DEBUG_LEVEL 1
	32	#endif
	33
	34	#if defined(PL041_DEBUG_LEVEL) && (PL041_DEBUG_LEVEL >= 1)
	35	#define DBG_L1(fmt, ...) \
	36	do { printf("pl041: " fmt , ## __VA_ARGS__); } while (0)
	37	#else
	38	#define DBG_L1(fmt, ...) \
	39	do { } while (0)
	40	#endif
	41
	42	#if defined(PL041_DEBUG_LEVEL) && (PL041_DEBUG_LEVEL >= 2)
	43	#define DBG_L2(fmt, ...) \
	44	do { printf("pl041: " fmt , ## __VA_ARGS__); } while (0)
	45	#else
	46	#define DBG_L2(fmt, ...) \
	47	do { } while (0)
	48	#endif
	49
	50
	51	#define MAX_FIFO_DEPTH (1024)
	52	#define DEFAULT_FIFO_DEPTH (8)
	53
	54	#define SLOT1_RW (1 << 19)
	55
	56	/* This FIFO only stores 20-bit samples on 32-bit words.
	57	So its level is independent of the selected mode */
	58	typedef struct {
	59	uint32_t level;
	60	uint32_t data[MAX_FIFO_DEPTH];
	61	} pl041_fifo;
	62
	63	typedef struct {
	64	pl041_fifo tx_fifo;
	65	uint8_t tx_enabled;
	66	uint8_t tx_compact_mode;
	67	uint8_t tx_sample_size;
	68
	69	pl041_fifo rx_fifo;
	70	uint8_t rx_enabled;
	71	uint8_t rx_compact_mode;
	72	uint8_t rx_sample_size;
	73	} pl041_channel;
	74
b354f03c AF	75	#define TYPE_PL041 "pl041"
	76	#define PL041(obj) OBJECT_CHECK(PL041State, (obj), TYPE_PL041)
	77
baae6725	78	typedef struct PL041State {
b354f03c AF	79	SysBusDevice parent_obj;
b354f03c AF	80
d028d02d MS	81	MemoryRegion iomem;
	82	qemu_irq irq;
	83
	84	uint32_t fifo_depth; /* FIFO depth in non-compact mode */
	85
	86	pl041_regfile regs;
	87	pl041_channel fifo1;
	88	lm4549_state codec;
baae6725	89	} PL041State;
d028d02d MS	90
	91
	92	static const unsigned char pl041_default_id[8] = {
	93	0x41, 0x10, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1
	94	};
	95
	96	#if defined(PL041_DEBUG_LEVEL)
	97	#define REGISTER(name, offset) #name,
	98	static const char *pl041_regs_name[] = {
	99	#include "pl041.hx"
	100	};
	101	#undef REGISTER
	102	#endif
	103
	104
	105	#if defined(PL041_DEBUG_LEVEL)
a8170e5e	106	static const char *get_reg_name(hwaddr offset)
d028d02d MS	107	{
	108	if (offset <= PL041_dr1_7) {
	109	return pl041_regs_name[offset >> 2];
	110	}
	111
	112	return "unknown";
	113	}
	114	#endif
	115
baae6725	116	static uint8_t pl041_compute_periphid3(PL041State *s)
d028d02d MS	117	{
	118	uint8_t id3 = 1; /* One channel */
	119
	120	/* Add the fifo depth information */
	121	switch (s->fifo_depth) {
	122	case 8:
	123	id3 \|= 0 << 3;
	124	break;
	125	case 32:
	126	id3 \|= 1 << 3;
	127	break;
	128	case 64:
	129	id3 \|= 2 << 3;
	130	break;
	131	case 128:
	132	id3 \|= 3 << 3;
	133	break;
	134	case 256:
	135	id3 \|= 4 << 3;
	136	break;
	137	case 512:
	138	id3 \|= 5 << 3;
	139	break;
	140	case 1024:
	141	id3 \|= 6 << 3;
	142	break;
	143	case 2048:
	144	id3 \|= 7 << 3;
	145	break;
	146	}
	147
	148	return id3;
	149	}
	150
baae6725	151	static void pl041_reset(PL041State *s)
d028d02d MS	152	{
	153	DBG_L1("pl041_reset\n");
	154
	155	memset(&s->regs, 0x00, sizeof(pl041_regfile));
	156
	157	s->regs.slfr = SL1TXEMPTY \| SL2TXEMPTY \| SL12TXEMPTY;
	158	s->regs.sr1 = TXFE \| RXFE \| TXHE;
	159	s->regs.isr1 = 0;
	160
	161	memset(&s->fifo1, 0x00, sizeof(s->fifo1));
	162	}
	163
	164
baae6725	165	static void pl041_fifo1_write(PL041State *s, uint32_t value)
d028d02d MS	166	{
	167	pl041_channel *channel = &s->fifo1;
	168	pl041_fifo *fifo = &s->fifo1.tx_fifo;
	169
	170	/* Push the value in the FIFO */
	171	if (channel->tx_compact_mode == 0) {
	172	/* Non-compact mode */
	173
	174	if (fifo->level < s->fifo_depth) {
	175	/* Pad the value with 0 to obtain a 20-bit sample */
	176	switch (channel->tx_sample_size) {
	177	case 12:
	178	value = (value << 8) & 0xFFFFF;
	179	break;
	180	case 16:
	181	value = (value << 4) & 0xFFFFF;
	182	break;
	183	case 18:
	184	value = (value << 2) & 0xFFFFF;
	185	break;
	186	case 20:
	187	default:
	188	break;
	189	}
	190
	191	/* Store the sample in the FIFO */
	192	fifo->data[fifo->level++] = value;
	193	}
	194	#if defined(PL041_DEBUG_LEVEL)
	195	else {
	196	DBG_L1("fifo1 write: overrun\n");
	197	}
	198	#endif
	199	} else {
	200	/* Compact mode */
	201
	202	if ((fifo->level + 2) < s->fifo_depth) {
	203	uint32_t i = 0;
	204	uint32_t sample = 0;
	205
	206	for (i = 0; i < 2; i++) {
	207	sample = value & 0xFFFF;
	208	value = value >> 16;
	209
	210	/* Pad each sample with 0 to obtain a 20-bit sample */
	211	switch (channel->tx_sample_size) {
	212	case 12:
	213	sample = sample << 8;
	214	break;
	215	case 16:
	216	default:
	217	sample = sample << 4;
	218	break;
	219	}
	220
	221	/* Store the sample in the FIFO */
	222	fifo->data[fifo->level++] = sample;
	223	}
	224	}
	225	#if defined(PL041_DEBUG_LEVEL)
	226	else {
	227	DBG_L1("fifo1 write: overrun\n");
	228	}
	229	#endif
230	}
231
232	/* Update the status register */
233	if (fifo->level > 0) {
234	s->regs.sr1 &= ~(TXUNDERRUN \| TXFE);
235	}
236
237	if (fifo->level >= (s->fifo_depth / 2)) {
238	s->regs.sr1 &= ~TXHE;
239	}
240
241	if (fifo->level >= s->fifo_depth) {
242	s->regs.sr1 \|= TXFF;
243	}
244
245	DBG_L2("fifo1_push sr1 = 0x%08x\n", s->regs.sr1);
246	}
247
baae6725	248	static void pl041_fifo1_transmit(PL041State *s)
d028d02d MS	249	{
	250	pl041_channel *channel = &s->fifo1;
	251	pl041_fifo *fifo = &s->fifo1.tx_fifo;
	252	uint32_t slots = s->regs.txcr1 & TXSLOT_MASK;
	253	uint32_t written_samples;
	254
	255	/* Check if FIFO1 transmit is enabled */
	256	if ((channel->tx_enabled) && (slots & (TXSLOT3 \| TXSLOT4))) {
	257	if (fifo->level >= (s->fifo_depth / 2)) {
	258	int i;
	259
	260	DBG_L1("Transfer FIFO level = %i\n", fifo->level);
	261
	262	/* Try to transfer the whole FIFO */
	263	for (i = 0; i < (fifo->level / 2); i++) {
	264	uint32_t left = fifo->data[i * 2];
	265	uint32_t right = fifo->data[i * 2 + 1];
	266
	267	/* Transmit two 20-bit samples to the codec */
	268	if (lm4549_write_samples(&s->codec, left, right) == 0) {
	269	DBG_L1("Codec buffer full\n");
	270	break;
	271	}
	272	}
	273
	274	written_samples = i * 2;
	275	if (written_samples > 0) {
	276	/* Update the FIFO level */
	277	fifo->level -= written_samples;
	278
	279	/* Move back the pending samples to the start of the FIFO */
	280	for (i = 0; i < fifo->level; i++) {
	281	fifo->data[i] = fifo->data[written_samples + i];
	282	}
	283
	284	/* Update the status register */
	285	s->regs.sr1 &= ~TXFF;
	286
	287	if (fifo->level <= (s->fifo_depth / 2)) {
	288	s->regs.sr1 \|= TXHE;
	289	}
	290
	291	if (fifo->level == 0) {
	292	s->regs.sr1 \|= TXFE \| TXUNDERRUN;
	293	DBG_L1("Empty FIFO\n");
	294	}
	295	}
	296	}
	297	}
	298	}
	299
baae6725	300	static void pl041_isr1_update(PL041State *s)
d028d02d MS	301	{
	302	/* Update ISR1 */
	303	if (s->regs.sr1 & TXUNDERRUN) {
	304	s->regs.isr1 \|= URINTR;
	305	} else {
	306	s->regs.isr1 &= ~URINTR;
	307	}
	308
	309	if (s->regs.sr1 & TXHE) {
	310	s->regs.isr1 \|= TXINTR;
	311	} else {
	312	s->regs.isr1 &= ~TXINTR;
	313	}
	314
	315	if (!(s->regs.sr1 & TXBUSY) && (s->regs.sr1 & TXFE)) {
	316	s->regs.isr1 \|= TXCINTR;
	317	} else {
	318	s->regs.isr1 &= ~TXCINTR;
	319	}
	320
	321	/* Update the irq state */
	322	qemu_set_irq(s->irq, ((s->regs.isr1 & s->regs.ie1) > 0) ? 1 : 0);
	323	DBG_L2("Set interrupt sr1 = 0x%08x isr1 = 0x%08x masked = 0x%08x\n",
	324	s->regs.sr1, s->regs.isr1, s->regs.isr1 & s->regs.ie1);
	325	}
	326
	327	static void pl041_request_data(void *opaque)
	328	{
baae6725	329	PL041State s = (PL041State )opaque;
d028d02d MS	330
	331	/* Trigger pending transfers */
	332	pl041_fifo1_transmit(s);
	333	pl041_isr1_update(s);
	334	}
	335
a8170e5e	336	static uint64_t pl041_read(void *opaque, hwaddr offset,
d028d02d MS	337	unsigned size)
d028d02d MS	338	{
baae6725	339	PL041State s = (PL041State )opaque;
d028d02d MS	340	int value;
	341
	342	if ((offset >= PL041_periphid0) && (offset <= PL041_pcellid3)) {
	343	if (offset == PL041_periphid3) {
	344	value = pl041_compute_periphid3(s);
	345	} else {
	346	value = pl041_default_id[(offset - PL041_periphid0) >> 2];
	347	}
	348
	349	DBG_L1("pl041_read [0x%08x] => 0x%08x\n", offset, value);
	350	return value;
	351	} else if (offset <= PL041_dr4_7) {
	352	value = ((uint32_t )&s->regs + (offset >> 2));
	353	} else {
	354	DBG_L1("pl041_read: Reserved offset %x\n", (int)offset);
	355	return 0;
	356	}
	357
	358	switch (offset) {
	359	case PL041_allints:
	360	value = s->regs.isr1 & 0x7F;
	361	break;
	362	}
	363
	364	DBG_L1("pl041_read [0x%08x] %s => 0x%08x\n", offset,
	365	get_reg_name(offset), value);
	366
	367	return value;
	368	}
	369
a8170e5e	370	static void pl041_write(void *opaque, hwaddr offset,
d028d02d MS	371	uint64_t value, unsigned size)
d028d02d MS	372	{
baae6725	373	PL041State s = (PL041State )opaque;
d028d02d MS	374	uint16_t control, data;
	375	uint32_t result;
	376
	377	DBG_L1("pl041_write [0x%08x] %s <= 0x%08x\n", offset,
	378	get_reg_name(offset), (unsigned int)value);
	379
	380	/* Write the register */
	381	if (offset <= PL041_dr4_7) {
	382	((uint32_t )&s->regs + (offset >> 2)) = value;
	383	} else {
	384	DBG_L1("pl041_write: Reserved offset %x\n", (int)offset);
	385	return;
	386	}
	387
	388	/* Execute the actions */
	389	switch (offset) {
	390	case PL041_txcr1:
	391	{
	392	pl041_channel *channel = &s->fifo1;
	393
	394	uint32_t txen = s->regs.txcr1 & TXEN;
	395	uint32_t tsize = (s->regs.txcr1 & TSIZE_MASK) >> TSIZE_MASK_BIT;
	396	uint32_t compact_mode = (s->regs.txcr1 & TXCOMPACT) ? 1 : 0;
	397	#if defined(PL041_DEBUG_LEVEL)
	398	uint32_t slots = (s->regs.txcr1 & TXSLOT_MASK) >> TXSLOT_MASK_BIT;
	399	uint32_t txfen = (s->regs.txcr1 & TXFEN) > 0 ? 1 : 0;
	400	#endif
	401
	402	DBG_L1("=> txen = %i slots = 0x%01x tsize = %i compact = %i "
	403	"txfen = %i\n", txen, slots, tsize, compact_mode, txfen);
	404
	405	channel->tx_enabled = txen;
	406	channel->tx_compact_mode = compact_mode;
	407
	408	switch (tsize) {
	409	case 0:
	410	channel->tx_sample_size = 16;
	411	break;
	412	case 1:
	413	channel->tx_sample_size = 18;
	414	break;
	415	case 2:
	416	channel->tx_sample_size = 20;
	417	break;
	418	case 3:
	419	channel->tx_sample_size = 12;
	420	break;
	421	}
	422
	423	DBG_L1("TX enabled = %i\n", channel->tx_enabled);
	424	DBG_L1("TX compact mode = %i\n", channel->tx_compact_mode);
	425	DBG_L1("TX sample width = %i\n", channel->tx_sample_size);
	426
	427	/* Check if compact mode is allowed with selected tsize */
	428	if (channel->tx_compact_mode == 1) {
	429	if ((channel->tx_sample_size == 18) \|\|
	430	(channel->tx_sample_size == 20)) {
	431	channel->tx_compact_mode = 0;
	432	DBG_L1("Compact mode not allowed with 18/20-bit sample size\n");
	433	}
	434	}
	435
	436	break;
	437	}
438	case PL041_sl1tx:
439	s->regs.slfr &= ~SL1TXEMPTY;
440
441	control = (s->regs.sl1tx >> 12) & 0x7F;
442	data = (s->regs.sl2tx >> 4) & 0xFFFF;
443
444	if ((s->regs.sl1tx & SLOT1_RW) == 0) {
445	/* Write operation */
446	lm4549_write(&s->codec, control, data);
447	} else {
448	/* Read operation */
449	result = lm4549_read(&s->codec, control);
450
451	/* Store the returned value */
452	s->regs.sl1rx = s->regs.sl1tx & ~SLOT1_RW;
453	s->regs.sl2rx = result << 4;
454
455	s->regs.slfr &= ~(SL1RXBUSY \| SL2RXBUSY);
456	s->regs.slfr \|= SL1RXVALID \| SL2RXVALID;
457	}
458	break;
459
460	case PL041_sl2tx:
461	s->regs.sl2tx = value;
462	s->regs.slfr &= ~SL2TXEMPTY;
463	break;
464
465	case PL041_intclr:
466	DBG_L1("=> Clear interrupt intclr = 0x%08x isr1 = 0x%08x\n",
467	s->regs.intclr, s->regs.isr1);
468
469	if (s->regs.intclr & TXUEC1) {
470	s->regs.sr1 &= ~TXUNDERRUN;
471	}
472	break;
473
474	case PL041_maincr:
475	{
476	#if defined(PL041_DEBUG_LEVEL)
477	char debug[] = " AACIFE SL1RXEN SL1TXEN";
478	if (!(value & AACIFE)) {
479	debug[0] = '!';
480	}
481	if (!(value & SL1RXEN)) {
482	debug[8] = '!';
483	}
484	if (!(value & SL1TXEN)) {
485	debug[17] = '!';
486	}
487	DBG_L1("%s\n", debug);
488	#endif
489
490	if ((s->regs.maincr & AACIFE) == 0) {
491	pl041_reset(s);
492	}
493	break;
494	}
495
496	case PL041_dr1_0:
497	case PL041_dr1_1:
498	case PL041_dr1_2:
499	case PL041_dr1_3:
500	pl041_fifo1_write(s, value);
501	break;
502	}
503
504	/* Transmit the FIFO content */
505	pl041_fifo1_transmit(s);
506
507	/* Update the ISR1 register */
508	pl041_isr1_update(s);
509	}
510
511	static void pl041_device_reset(DeviceState *d)
512	{
b354f03c	513	PL041State *s = PL041(d);
d028d02d MS	514
	515	pl041_reset(s);
	516	}
	517
	518	static const MemoryRegionOps pl041_ops = {
	519	.read = pl041_read,
	520	.write = pl041_write,
	521	.endianness = DEVICE_NATIVE_ENDIAN,
	522	};
	523
8becab95	524	static void pl041_init(Object *obj)
d028d02d	525	{
8becab95	526	SysBusDevice *dev = SYS_BUS_DEVICE(obj);
b354f03c	527	PL041State *s = PL041(dev);
d028d02d MS	528
	529	DBG_L1("pl041_init 0x%08x\n", (uint32_t)s);
	530
8becab95 XZ	531	/* Connect the device to the sysbus */
	532	memory_region_init_io(&s->iomem, obj, &pl041_ops, s, "pl041", 0x1000);
	533	sysbus_init_mmio(dev, &s->iomem);
	534	sysbus_init_irq(dev, &s->irq);
	535	}
	536
	537	static void pl041_realize(DeviceState dev, Error *errp)
	538	{
	539	PL041State *s = PL041(dev);
	540
d028d02d MS	541	/* Check the device properties */
	542	switch (s->fifo_depth) {
	543	case 8:
	544	case 32:
	545	case 64:
	546	case 128:
	547	case 256:
	548	case 512:
	549	case 1024:
	550	case 2048:
	551	break;
	552	case 16:
	553	default:
	554	/* NC FIFO depth of 16 is not allowed because its id bits in
	555	AACIPERIPHID3 overlap with the id for the default NC FIFO depth */
b1d9df90 PM	556	qemu_log_mask(LOG_UNIMP,
	557	"pl041: unsupported non-compact fifo depth [%i]\n",
	558	s->fifo_depth);
d028d02d MS	559	}
d028d02d MS	560
d028d02d MS	561	/* Init the codec */
d028d02d MS	562	lm4549_init(&s->codec, &pl041_request_data, (void *)s);
d028d02d MS	563	}
	564
	565	static const VMStateDescription vmstate_pl041_regfile = {
	566	.name = "pl041_regfile",
	567	.version_id = 1,
	568	.minimum_version_id = 1,
8f1e884b	569	.fields = (VMStateField[]) {
d028d02d MS	570	#define REGISTER(name, offset) VMSTATE_UINT32(name, pl041_regfile),
	571	#include "pl041.hx"
	572	#undef REGISTER
	573	VMSTATE_END_OF_LIST()
	574	}
	575	};
	576
	577	static const VMStateDescription vmstate_pl041_fifo = {
	578	.name = "pl041_fifo",
	579	.version_id = 1,
	580	.minimum_version_id = 1,
8f1e884b	581	.fields = (VMStateField[]) {
d028d02d MS	582	VMSTATE_UINT32(level, pl041_fifo),
	583	VMSTATE_UINT32_ARRAY(data, pl041_fifo, MAX_FIFO_DEPTH),
	584	VMSTATE_END_OF_LIST()
	585	}
	586	};
	587
	588	static const VMStateDescription vmstate_pl041_channel = {
	589	.name = "pl041_channel",
	590	.version_id = 1,
	591	.minimum_version_id = 1,
8f1e884b	592	.fields = (VMStateField[]) {
d028d02d MS	593	VMSTATE_STRUCT(tx_fifo, pl041_channel, 0,
	594	vmstate_pl041_fifo, pl041_fifo),
	595	VMSTATE_UINT8(tx_enabled, pl041_channel),
	596	VMSTATE_UINT8(tx_compact_mode, pl041_channel),
	597	VMSTATE_UINT8(tx_sample_size, pl041_channel),
	598	VMSTATE_STRUCT(rx_fifo, pl041_channel, 0,
	599	vmstate_pl041_fifo, pl041_fifo),
	600	VMSTATE_UINT8(rx_enabled, pl041_channel),
	601	VMSTATE_UINT8(rx_compact_mode, pl041_channel),
	602	VMSTATE_UINT8(rx_sample_size, pl041_channel),
	603	VMSTATE_END_OF_LIST()
	604	}
	605	};
	606
	607	static const VMStateDescription vmstate_pl041 = {
	608	.name = "pl041",
	609	.version_id = 1,
	610	.minimum_version_id = 1,
	611	.fields = (VMStateField[]) {
baae6725 AF	612	VMSTATE_UINT32(fifo_depth, PL041State),
baae6725 AF	613	VMSTATE_STRUCT(regs, PL041State, 0,
d028d02d	614	vmstate_pl041_regfile, pl041_regfile),
baae6725	615	VMSTATE_STRUCT(fifo1, PL041State, 0,
d028d02d	616	vmstate_pl041_channel, pl041_channel),
baae6725	617	VMSTATE_STRUCT(codec, PL041State, 0,
d028d02d MS	618	vmstate_lm4549_state, lm4549_state),
	619	VMSTATE_END_OF_LIST()
	620	}
	621	};
	622
999e12bb AL	623	static Property pl041_device_properties[] = {
999e12bb AL	624	/* Non-compact FIFO depth property */
baae6725 AF	625	DEFINE_PROP_UINT32("nc_fifo_depth", PL041State, fifo_depth,
baae6725 AF	626	DEFAULT_FIFO_DEPTH),
999e12bb AL	627	DEFINE_PROP_END_OF_LIST(),
	628	};
	629
	630	static void pl041_device_class_init(ObjectClass klass, void data)
	631	{
39bffca2	632	DeviceClass *dc = DEVICE_CLASS(klass);
999e12bb	633
8becab95	634	dc->realize = pl041_realize;
125ee0ed	635	set_bit(DEVICE_CATEGORY_SOUND, dc->categories);
39bffca2 AL	636	dc->reset = pl041_device_reset;
	637	dc->vmsd = &vmstate_pl041;
	638	dc->props = pl041_device_properties;
999e12bb AL	639	}
999e12bb AL	640
8c43a6f0	641	static const TypeInfo pl041_device_info = {
b354f03c	642	.name = TYPE_PL041,
39bffca2	643	.parent = TYPE_SYS_BUS_DEVICE,
baae6725	644	.instance_size = sizeof(PL041State),
8becab95	645	.instance_init = pl041_init,
39bffca2	646	.class_init = pl041_device_class_init,
d028d02d MS	647	};
d028d02d MS	648
83f7d43a	649	static void pl041_register_types(void)
d028d02d	650	{
39bffca2	651	type_register_static(&pl041_device_info);
d028d02d MS	652	}
d028d02d MS	653
83f7d43a	654	type_init(pl041_register_types)