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target-arm: Change cpu_arm_init() return type to ARMCPU
[qemu.git] / target-arm / cpu.c
CommitLineData
dec9c2d4
AF		 1/*
2 * QEMU ARM CPU
3 *
4 * Copyright (c) 2012 SUSE LINUX Products GmbH
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see
18 * <http://www.gnu.org/licenses/gpl-2.0.html>
19 */
20
778c3a06 21#include "cpu.h"
dec9c2d4 22#include "qemu-common.h"
3c30dd5a
PM		 23#if !defined(CONFIG_USER_ONLY)
24#include "hw/loader.h"
25#endif
dec9c2d4
AF		 26
27/* CPUClass::reset() */
28static void arm_cpu_reset(CPUState *s)
29{
30 ARMCPU *cpu = ARM_CPU(s);
31 ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu);
3c30dd5a
PM		 32 CPUARMState *env = &cpu->env;
33 uint32_t tmp = 0;
34
35 if (qemu_loglevel_mask(CPU_LOG_RESET)) {
36 qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
37 log_cpu_state(env, 0);
38 }
dec9c2d4
AF		 39
40 acc->parent_reset(s);
41
3c30dd5a
PM		 42 tmp = env->cp15.c15_config_base_address;
43 memset(env, 0, offsetof(CPUARMState, breakpoints));
44 env->cp15.c15_config_base_address = tmp;
45 env->cp15.c0_cpuid = cpu->midr;
46 env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid;
47 env->vfp.xregs[ARM_VFP_MVFR0] = cpu->mvfr0;
48 env->vfp.xregs[ARM_VFP_MVFR1] = cpu->mvfr1;
49 env->cp15.c0_cachetype = cpu->ctr;
50 env->cp15.c1_sys = cpu->reset_sctlr;
51 env->cp15.c0_c1[0] = cpu->id_pfr0;
52 env->cp15.c0_c1[1] = cpu->id_pfr1;
53 env->cp15.c0_c1[2] = cpu->id_dfr0;
54 env->cp15.c0_c1[3] = cpu->id_afr0;
55 env->cp15.c0_c1[4] = cpu->id_mmfr0;
56 env->cp15.c0_c1[5] = cpu->id_mmfr1;
57 env->cp15.c0_c1[6] = cpu->id_mmfr2;
58 env->cp15.c0_c1[7] = cpu->id_mmfr3;
59 env->cp15.c0_c2[0] = cpu->id_isar0;
60 env->cp15.c0_c2[1] = cpu->id_isar1;
61 env->cp15.c0_c2[2] = cpu->id_isar2;
62 env->cp15.c0_c2[3] = cpu->id_isar3;
63 env->cp15.c0_c2[4] = cpu->id_isar4;
64 env->cp15.c0_c2[5] = cpu->id_isar5;
65 env->cp15.c15_i_min = 0xff0;
66 env->cp15.c0_clid = cpu->clidr;
67 memcpy(env->cp15.c0_ccsid, cpu->ccsidr, ARRAY_SIZE(cpu->ccsidr));
68
69 if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
70 env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q';
71 }
72
73#if defined(CONFIG_USER_ONLY)
74 env->uncached_cpsr = ARM_CPU_MODE_USR;
75 /* For user mode we must enable access to coprocessors */
76 env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30;
77 if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
78 env->cp15.c15_cpar = 3;
79 } else if (arm_feature(env, ARM_FEATURE_XSCALE)) {
80 env->cp15.c15_cpar = 1;
81 }
82#else
83 /* SVC mode with interrupts disabled. */
84 env->uncached_cpsr = ARM_CPU_MODE_SVC | CPSR_A | CPSR_F | CPSR_I;
85 /* On ARMv7-M the CPSR_I is the value of the PRIMASK register, and is
86 clear at reset. Initial SP and PC are loaded from ROM. */
87 if (IS_M(env)) {
88 uint32_t pc;
89 uint8_t *rom;
90 env->uncached_cpsr &= ~CPSR_I;
91 rom = rom_ptr(0);
92 if (rom) {
93 /* We should really use ldl_phys here, in case the guest
94 modified flash and reset itself. However images
95 loaded via -kernel have not been copied yet, so load the
96 values directly from there. */
97 env->regs[13] = ldl_p(rom);
98 pc = ldl_p(rom + 4);
99 env->thumb = pc & 1;
100 env->regs[15] = pc & ~1;
101 }
102 }
103 env->vfp.xregs[ARM_VFP_FPEXC] = 0;
104 env->cp15.c2_base_mask = 0xffffc000u;
105 /* v7 performance monitor control register: same implementor
106 * field as main ID register, and we implement no event counters.
107 */
108 env->cp15.c9_pmcr = (cpu->midr & 0xff000000);
109#endif
110 set_flush_to_zero(1, &env->vfp.standard_fp_status);
111 set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status);
112 set_default_nan_mode(1, &env->vfp.standard_fp_status);
113 set_float_detect_tininess(float_tininess_before_rounding,
114 &env->vfp.fp_status);
115 set_float_detect_tininess(float_tininess_before_rounding,
116 &env->vfp.standard_fp_status);
117 tlb_flush(env, 1);
118 /* Reset is a state change for some CPUARMState fields which we
119 * bake assumptions about into translated code, so we need to
120 * tb_flush().
121 */
122 tb_flush(env);
dec9c2d4
AF		 123}
124
581be094
PM		 125static inline void set_feature(CPUARMState *env, int feature)
126{
127 env->features |= 1u << feature;
128}
129
777dc784
PM		 130static void arm_cpu_initfn(Object *obj)
131{
132 ARMCPU *cpu = ARM_CPU(obj);
133
134 cpu_exec_init(&cpu->env);
135}
136
581be094
PM		 137void arm_cpu_realize(ARMCPU *cpu)
138{
139 /* This function is called by cpu_arm_init() because it
140 * needs to do common actions based on feature bits, etc
141 * that have been set by the subclass init functions.
142 * When we have QOM realize support it should become
143 * a true realize function instead.
144 */
145 CPUARMState *env = &cpu->env;
146 /* Some features automatically imply others: */
147 if (arm_feature(env, ARM_FEATURE_V7)) {
148 set_feature(env, ARM_FEATURE_VAPA);
149 set_feature(env, ARM_FEATURE_THUMB2);
150 if (!arm_feature(env, ARM_FEATURE_M)) {
151 set_feature(env, ARM_FEATURE_V6K);
152 } else {
153 set_feature(env, ARM_FEATURE_V6);
154 }
155 }
156 if (arm_feature(env, ARM_FEATURE_V6K)) {
157 set_feature(env, ARM_FEATURE_V6);
158 set_feature(env, ARM_FEATURE_MVFR);
159 }
160 if (arm_feature(env, ARM_FEATURE_V6)) {
161 set_feature(env, ARM_FEATURE_V5);
162 if (!arm_feature(env, ARM_FEATURE_M)) {
163 set_feature(env, ARM_FEATURE_AUXCR);
164 }
165 }
166 if (arm_feature(env, ARM_FEATURE_V5)) {
167 set_feature(env, ARM_FEATURE_V4T);
168 }
169 if (arm_feature(env, ARM_FEATURE_M)) {
170 set_feature(env, ARM_FEATURE_THUMB_DIV);
171 }
172 if (arm_feature(env, ARM_FEATURE_ARM_DIV)) {
173 set_feature(env, ARM_FEATURE_THUMB_DIV);
174 }
175 if (arm_feature(env, ARM_FEATURE_VFP4)) {
176 set_feature(env, ARM_FEATURE_VFP3);
177 }
178 if (arm_feature(env, ARM_FEATURE_VFP3)) {
179 set_feature(env, ARM_FEATURE_VFP);
180 }
181}
182
777dc784
PM		 183/* CPU models */
184
185static void arm926_initfn(Object *obj)
186{
187 ARMCPU *cpu = ARM_CPU(obj);
581be094
PM		 188 set_feature(&cpu->env, ARM_FEATURE_V5);
189 set_feature(&cpu->env, ARM_FEATURE_VFP);
777dc784 190 cpu->midr = ARM_CPUID_ARM926;
325b3cef 191 cpu->reset_fpsid = 0x41011090;
64e1671f 192 cpu->ctr = 0x1dd20d2;
0ca7e01c 193 cpu->reset_sctlr = 0x00090078;
777dc784
PM		 194}
195
196static void arm946_initfn(Object *obj)
197{
198 ARMCPU *cpu = ARM_CPU(obj);
581be094
PM		 199 set_feature(&cpu->env, ARM_FEATURE_V5);
200 set_feature(&cpu->env, ARM_FEATURE_MPU);
777dc784 201 cpu->midr = ARM_CPUID_ARM946;
64e1671f 202 cpu->ctr = 0x0f004006;
0ca7e01c 203 cpu->reset_sctlr = 0x00000078;
777dc784
PM		 204}
205
206static void arm1026_initfn(Object *obj)
207{
208 ARMCPU *cpu = ARM_CPU(obj);
581be094
PM		 209 set_feature(&cpu->env, ARM_FEATURE_V5);
210 set_feature(&cpu->env, ARM_FEATURE_VFP);
211 set_feature(&cpu->env, ARM_FEATURE_AUXCR);
777dc784 212 cpu->midr = ARM_CPUID_ARM1026;
325b3cef 213 cpu->reset_fpsid = 0x410110a0;
64e1671f 214 cpu->ctr = 0x1dd20d2;
0ca7e01c 215 cpu->reset_sctlr = 0x00090078;
777dc784
PM		 216}
217
218static void arm1136_r2_initfn(Object *obj)
219{
220 ARMCPU *cpu = ARM_CPU(obj);
2e4d7e3e
PM		 221 /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an
222 * older core than plain "arm1136". In particular this does not
223 * have the v6K features.
224 * These ID register values are correct for 1136 but may be wrong
225 * for 1136_r2 (in particular r0p2 does not actually implement most
226 * of the ID registers).
227 */
581be094
PM		 228 set_feature(&cpu->env, ARM_FEATURE_V6);
229 set_feature(&cpu->env, ARM_FEATURE_VFP);
777dc784 230 cpu->midr = ARM_CPUID_ARM1136_R2;
325b3cef 231 cpu->reset_fpsid = 0x410120b4;
bd35c355
PM		 232 cpu->mvfr0 = 0x11111111;
233 cpu->mvfr1 = 0x00000000;
64e1671f 234 cpu->ctr = 0x1dd20d2;
0ca7e01c 235 cpu->reset_sctlr = 0x00050078;
2e4d7e3e
PM		 236 cpu->id_pfr0 = 0x111;
237 cpu->id_pfr1 = 0x1;
238 cpu->id_dfr0 = 0x2;
239 cpu->id_afr0 = 0x3;
240 cpu->id_mmfr0 = 0x01130003;
241 cpu->id_mmfr1 = 0x10030302;
242 cpu->id_mmfr2 = 0x01222110;
243 cpu->id_isar0 = 0x00140011;
244 cpu->id_isar1 = 0x12002111;
245 cpu->id_isar2 = 0x11231111;
246 cpu->id_isar3 = 0x01102131;
247 cpu->id_isar4 = 0x141;
777dc784
PM		 248}
249
250static void arm1136_initfn(Object *obj)
251{
252 ARMCPU *cpu = ARM_CPU(obj);
581be094
PM		 253 set_feature(&cpu->env, ARM_FEATURE_V6K);
254 set_feature(&cpu->env, ARM_FEATURE_V6);
255 set_feature(&cpu->env, ARM_FEATURE_VFP);
777dc784 256 cpu->midr = ARM_CPUID_ARM1136;
325b3cef 257 cpu->reset_fpsid = 0x410120b4;
bd35c355
PM		 258 cpu->mvfr0 = 0x11111111;
259 cpu->mvfr1 = 0x00000000;
64e1671f 260 cpu->ctr = 0x1dd20d2;
0ca7e01c 261 cpu->reset_sctlr = 0x00050078;
2e4d7e3e
PM		 262 cpu->id_pfr0 = 0x111;
263 cpu->id_pfr1 = 0x1;
264 cpu->id_dfr0 = 0x2;
265 cpu->id_afr0 = 0x3;
266 cpu->id_mmfr0 = 0x01130003;
267 cpu->id_mmfr1 = 0x10030302;
268 cpu->id_mmfr2 = 0x01222110;
269 cpu->id_isar0 = 0x00140011;
270 cpu->id_isar1 = 0x12002111;
271 cpu->id_isar2 = 0x11231111;
272 cpu->id_isar3 = 0x01102131;
273 cpu->id_isar4 = 0x141;
777dc784
PM		 274}
275
276static void arm1176_initfn(Object *obj)
277{
278 ARMCPU *cpu = ARM_CPU(obj);
581be094
PM		 279 set_feature(&cpu->env, ARM_FEATURE_V6K);
280 set_feature(&cpu->env, ARM_FEATURE_VFP);
281 set_feature(&cpu->env, ARM_FEATURE_VAPA);
777dc784 282 cpu->midr = ARM_CPUID_ARM1176;
325b3cef 283 cpu->reset_fpsid = 0x410120b5;
bd35c355
PM		 284 cpu->mvfr0 = 0x11111111;
285 cpu->mvfr1 = 0x00000000;
64e1671f 286 cpu->ctr = 0x1dd20d2;
0ca7e01c 287 cpu->reset_sctlr = 0x00050078;
2e4d7e3e
PM		 288 cpu->id_pfr0 = 0x111;
289 cpu->id_pfr1 = 0x11;
290 cpu->id_dfr0 = 0x33;
291 cpu->id_afr0 = 0;
292 cpu->id_mmfr0 = 0x01130003;
293 cpu->id_mmfr1 = 0x10030302;
294 cpu->id_mmfr2 = 0x01222100;
295 cpu->id_isar0 = 0x0140011;
296 cpu->id_isar1 = 0x12002111;
297 cpu->id_isar2 = 0x11231121;
298 cpu->id_isar3 = 0x01102131;
299 cpu->id_isar4 = 0x01141;
777dc784
PM		 300}
301
302static void arm11mpcore_initfn(Object *obj)
303{
304 ARMCPU *cpu = ARM_CPU(obj);
581be094
PM		 305 set_feature(&cpu->env, ARM_FEATURE_V6K);
306 set_feature(&cpu->env, ARM_FEATURE_VFP);
307 set_feature(&cpu->env, ARM_FEATURE_VAPA);
777dc784 308 cpu->midr = ARM_CPUID_ARM11MPCORE;
325b3cef 309 cpu->reset_fpsid = 0x410120b4;
bd35c355
PM		 310 cpu->mvfr0 = 0x11111111;
311 cpu->mvfr1 = 0x00000000;
64e1671f 312 cpu->ctr = 0x1dd20d2;
2e4d7e3e
PM		 313 cpu->id_pfr0 = 0x111;
314 cpu->id_pfr1 = 0x1;
315 cpu->id_dfr0 = 0;
316 cpu->id_afr0 = 0x2;
317 cpu->id_mmfr0 = 0x01100103;
318 cpu->id_mmfr1 = 0x10020302;
319 cpu->id_mmfr2 = 0x01222000;
320 cpu->id_isar0 = 0x00100011;
321 cpu->id_isar1 = 0x12002111;
322 cpu->id_isar2 = 0x11221011;
323 cpu->id_isar3 = 0x01102131;
324 cpu->id_isar4 = 0x141;
777dc784
PM		 325}
326
327static void cortex_m3_initfn(Object *obj)
328{
329 ARMCPU *cpu = ARM_CPU(obj);
581be094
PM		 330 set_feature(&cpu->env, ARM_FEATURE_V7);
331 set_feature(&cpu->env, ARM_FEATURE_M);
777dc784
PM		 332 cpu->midr = ARM_CPUID_CORTEXM3;
333}
334
335static void cortex_a8_initfn(Object *obj)
336{
337 ARMCPU *cpu = ARM_CPU(obj);
581be094
PM		 338 set_feature(&cpu->env, ARM_FEATURE_V7);
339 set_feature(&cpu->env, ARM_FEATURE_VFP3);
340 set_feature(&cpu->env, ARM_FEATURE_NEON);
341 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
777dc784 342 cpu->midr = ARM_CPUID_CORTEXA8;
325b3cef 343 cpu->reset_fpsid = 0x410330c0;
bd35c355
PM		 344 cpu->mvfr0 = 0x11110222;
345 cpu->mvfr1 = 0x00011100;
64e1671f 346 cpu->ctr = 0x82048004;
0ca7e01c 347 cpu->reset_sctlr = 0x00c50078;
2e4d7e3e
PM		 348 cpu->id_pfr0 = 0x1031;
349 cpu->id_pfr1 = 0x11;
350 cpu->id_dfr0 = 0x400;
351 cpu->id_afr0 = 0;
352 cpu->id_mmfr0 = 0x31100003;
353 cpu->id_mmfr1 = 0x20000000;
354 cpu->id_mmfr2 = 0x01202000;
355 cpu->id_mmfr3 = 0x11;
356 cpu->id_isar0 = 0x00101111;
357 cpu->id_isar1 = 0x12112111;
358 cpu->id_isar2 = 0x21232031;
359 cpu->id_isar3 = 0x11112131;
360 cpu->id_isar4 = 0x00111142;
85df3786
PM		 361 cpu->clidr = (1 << 27) | (2 << 24) | 3;
362 cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */
363 cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */
364 cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */
777dc784
PM		 365}
366
367static void cortex_a9_initfn(Object *obj)
368{
369 ARMCPU *cpu = ARM_CPU(obj);
581be094
PM		 370 set_feature(&cpu->env, ARM_FEATURE_V7);
371 set_feature(&cpu->env, ARM_FEATURE_VFP3);
372 set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);
373 set_feature(&cpu->env, ARM_FEATURE_NEON);
374 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
375 /* Note that A9 supports the MP extensions even for
376 * A9UP and single-core A9MP (which are both different
377 * and valid configurations; we don't model A9UP).
378 */
379 set_feature(&cpu->env, ARM_FEATURE_V7MP);
777dc784 380 cpu->midr = ARM_CPUID_CORTEXA9;
325b3cef 381 cpu->reset_fpsid = 0x41033090;
bd35c355
PM		 382 cpu->mvfr0 = 0x11110222;
383 cpu->mvfr1 = 0x01111111;
64e1671f 384 cpu->ctr = 0x80038003;
0ca7e01c 385 cpu->reset_sctlr = 0x00c50078;
2e4d7e3e
PM		 386 cpu->id_pfr0 = 0x1031;
387 cpu->id_pfr1 = 0x11;
388 cpu->id_dfr0 = 0x000;
389 cpu->id_afr0 = 0;
390 cpu->id_mmfr0 = 0x00100103;
391 cpu->id_mmfr1 = 0x20000000;
392 cpu->id_mmfr2 = 0x01230000;
393 cpu->id_mmfr3 = 0x00002111;
394 cpu->id_isar0 = 0x00101111;
395 cpu->id_isar1 = 0x13112111;
396 cpu->id_isar2 = 0x21232041;
397 cpu->id_isar3 = 0x11112131;
398 cpu->id_isar4 = 0x00111142;
85df3786
PM		 399 cpu->clidr = (1 << 27) | (1 << 24) | 3;
400 cpu->ccsidr[0] = 0xe00fe015; /* 16k L1 dcache. */
401 cpu->ccsidr[1] = 0x200fe015; /* 16k L1 icache. */
777dc784
PM		 402}
403
404static void cortex_a15_initfn(Object *obj)
405{
406 ARMCPU *cpu = ARM_CPU(obj);
581be094
PM		 407 set_feature(&cpu->env, ARM_FEATURE_V7);
408 set_feature(&cpu->env, ARM_FEATURE_VFP4);
409 set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);
410 set_feature(&cpu->env, ARM_FEATURE_NEON);
411 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
412 set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);
413 set_feature(&cpu->env, ARM_FEATURE_V7MP);
414 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
777dc784 415 cpu->midr = ARM_CPUID_CORTEXA15;
325b3cef 416 cpu->reset_fpsid = 0x410430f0;
bd35c355
PM		 417 cpu->mvfr0 = 0x10110222;
418 cpu->mvfr1 = 0x11111111;
64e1671f 419 cpu->ctr = 0x8444c004;
0ca7e01c 420 cpu->reset_sctlr = 0x00c50078;
2e4d7e3e
PM		 421 cpu->id_pfr0 = 0x00001131;
422 cpu->id_pfr1 = 0x00011011;
423 cpu->id_dfr0 = 0x02010555;
424 cpu->id_afr0 = 0x00000000;
425 cpu->id_mmfr0 = 0x10201105;
426 cpu->id_mmfr1 = 0x20000000;
427 cpu->id_mmfr2 = 0x01240000;
428 cpu->id_mmfr3 = 0x02102211;
429 cpu->id_isar0 = 0x02101110;
430 cpu->id_isar1 = 0x13112111;
431 cpu->id_isar2 = 0x21232041;
432 cpu->id_isar3 = 0x11112131;
433 cpu->id_isar4 = 0x10011142;
85df3786
PM		 434 cpu->clidr = 0x0a200023;
435 cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */
436 cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */
437 cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */
777dc784
PM		 438}
439
440static void ti925t_initfn(Object *obj)
441{
442 ARMCPU *cpu = ARM_CPU(obj);
581be094
PM		 443 set_feature(&cpu->env, ARM_FEATURE_V4T);
444 set_feature(&cpu->env, ARM_FEATURE_OMAPCP);
777dc784 445 cpu->midr = ARM_CPUID_TI925T;
64e1671f 446 cpu->ctr = 0x5109149;
0ca7e01c 447 cpu->reset_sctlr = 0x00000070;
777dc784
PM		 448}
449
450static void sa1100_initfn(Object *obj)
451{
452 ARMCPU *cpu = ARM_CPU(obj);
581be094 453 set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
777dc784 454 cpu->midr = ARM_CPUID_SA1100;
0ca7e01c 455 cpu->reset_sctlr = 0x00000070;
777dc784
PM		 456}
457
458static void sa1110_initfn(Object *obj)
459{
460 ARMCPU *cpu = ARM_CPU(obj);
581be094 461 set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
777dc784 462 cpu->midr = ARM_CPUID_SA1110;
0ca7e01c 463 cpu->reset_sctlr = 0x00000070;
777dc784
PM		 464}
465
466static void pxa250_initfn(Object *obj)
467{
468 ARMCPU *cpu = ARM_CPU(obj);
581be094
PM		 469 set_feature(&cpu->env, ARM_FEATURE_V5);
470 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
777dc784 471 cpu->midr = ARM_CPUID_PXA250;
64e1671f 472 cpu->ctr = 0xd172172;
0ca7e01c 473 cpu->reset_sctlr = 0x00000078;
777dc784
PM		 474}
475
476static void pxa255_initfn(Object *obj)
477{
478 ARMCPU *cpu = ARM_CPU(obj);
581be094
PM		 479 set_feature(&cpu->env, ARM_FEATURE_V5);
480 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
777dc784 481 cpu->midr = ARM_CPUID_PXA255;
64e1671f 482 cpu->ctr = 0xd172172;
0ca7e01c 483 cpu->reset_sctlr = 0x00000078;
777dc784
PM		 484}
485
486static void pxa260_initfn(Object *obj)
487{
488 ARMCPU *cpu = ARM_CPU(obj);
581be094
PM		 489 set_feature(&cpu->env, ARM_FEATURE_V5);
490 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
777dc784 491 cpu->midr = ARM_CPUID_PXA260;
64e1671f 492 cpu->ctr = 0xd172172;
0ca7e01c 493 cpu->reset_sctlr = 0x00000078;
777dc784
PM		 494}
495
496static void pxa261_initfn(Object *obj)
497{
498 ARMCPU *cpu = ARM_CPU(obj);
581be094
PM		 499 set_feature(&cpu->env, ARM_FEATURE_V5);
500 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
777dc784 501 cpu->midr = ARM_CPUID_PXA261;
64e1671f 502 cpu->ctr = 0xd172172;
0ca7e01c 503 cpu->reset_sctlr = 0x00000078;
777dc784
PM		 504}
505
506static void pxa262_initfn(Object *obj)
507{
508 ARMCPU *cpu = ARM_CPU(obj);
581be094
PM		 509 set_feature(&cpu->env, ARM_FEATURE_V5);
510 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
777dc784 511 cpu->midr = ARM_CPUID_PXA262;
64e1671f 512 cpu->ctr = 0xd172172;
0ca7e01c 513 cpu->reset_sctlr = 0x00000078;
777dc784
PM		 514}
515
516static void pxa270a0_initfn(Object *obj)
517{
518 ARMCPU *cpu = ARM_CPU(obj);
581be094
PM		 519 set_feature(&cpu->env, ARM_FEATURE_V5);
520 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
521 set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
777dc784 522 cpu->midr = ARM_CPUID_PXA270_A0;
64e1671f 523 cpu->ctr = 0xd172172;
0ca7e01c 524 cpu->reset_sctlr = 0x00000078;
777dc784
PM		 525}
526
527static void pxa270a1_initfn(Object *obj)
528{
529 ARMCPU *cpu = ARM_CPU(obj);
581be094
PM		 530 set_feature(&cpu->env, ARM_FEATURE_V5);
531 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
532 set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
777dc784 533 cpu->midr = ARM_CPUID_PXA270_A1;
64e1671f 534 cpu->ctr = 0xd172172;
0ca7e01c 535 cpu->reset_sctlr = 0x00000078;
777dc784
PM		 536}
537
538static void pxa270b0_initfn(Object *obj)
539{
540 ARMCPU *cpu = ARM_CPU(obj);
581be094
PM		 541 set_feature(&cpu->env, ARM_FEATURE_V5);
542 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
543 set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
777dc784 544 cpu->midr = ARM_CPUID_PXA270_B0;
64e1671f 545 cpu->ctr = 0xd172172;
0ca7e01c 546 cpu->reset_sctlr = 0x00000078;
777dc784
PM		 547}
548
549static void pxa270b1_initfn(Object *obj)
550{
551 ARMCPU *cpu = ARM_CPU(obj);
581be094
PM		 552 set_feature(&cpu->env, ARM_FEATURE_V5);
553 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
554 set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
777dc784 555 cpu->midr = ARM_CPUID_PXA270_B1;
64e1671f 556 cpu->ctr = 0xd172172;
0ca7e01c 557 cpu->reset_sctlr = 0x00000078;
777dc784
PM		 558}
559
560static void pxa270c0_initfn(Object *obj)
561{
562 ARMCPU *cpu = ARM_CPU(obj);
581be094
PM		 563 set_feature(&cpu->env, ARM_FEATURE_V5);
564 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
565 set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
777dc784 566 cpu->midr = ARM_CPUID_PXA270_C0;
64e1671f 567 cpu->ctr = 0xd172172;
0ca7e01c 568 cpu->reset_sctlr = 0x00000078;
777dc784
PM		 569}
570
571static void pxa270c5_initfn(Object *obj)
572{
573 ARMCPU *cpu = ARM_CPU(obj);
581be094
PM		 574 set_feature(&cpu->env, ARM_FEATURE_V5);
575 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
576 set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
777dc784 577 cpu->midr = ARM_CPUID_PXA270_C5;
64e1671f 578 cpu->ctr = 0xd172172;
0ca7e01c 579 cpu->reset_sctlr = 0x00000078;
777dc784
PM		 580}
581
582static void arm_any_initfn(Object *obj)
583{
584 ARMCPU *cpu = ARM_CPU(obj);
581be094
PM		 585 set_feature(&cpu->env, ARM_FEATURE_V7);
586 set_feature(&cpu->env, ARM_FEATURE_VFP4);
587 set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);
588 set_feature(&cpu->env, ARM_FEATURE_NEON);
589 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
590 set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);
591 set_feature(&cpu->env, ARM_FEATURE_V7MP);
777dc784
PM		 592 cpu->midr = ARM_CPUID_ANY;
593}
594
595typedef struct ARMCPUInfo {
596 const char *name;
597 void (*initfn)(Object *obj);
598} ARMCPUInfo;
599
600static const ARMCPUInfo arm_cpus[] = {
601 { .name = "arm926", .initfn = arm926_initfn },
602 { .name = "arm946", .initfn = arm946_initfn },
603 { .name = "arm1026", .initfn = arm1026_initfn },
604 /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an
605 * older core than plain "arm1136". In particular this does not
606 * have the v6K features.
607 */
608 { .name = "arm1136-r2", .initfn = arm1136_r2_initfn },
609 { .name = "arm1136", .initfn = arm1136_initfn },
610 { .name = "arm1176", .initfn = arm1176_initfn },
611 { .name = "arm11mpcore", .initfn = arm11mpcore_initfn },
612 { .name = "cortex-m3", .initfn = cortex_m3_initfn },
613 { .name = "cortex-a8", .initfn = cortex_a8_initfn },
614 { .name = "cortex-a9", .initfn = cortex_a9_initfn },
615 { .name = "cortex-a15", .initfn = cortex_a15_initfn },
616 { .name = "ti925t", .initfn = ti925t_initfn },
617 { .name = "sa1100", .initfn = sa1100_initfn },
618 { .name = "sa1110", .initfn = sa1110_initfn },
619 { .name = "pxa250", .initfn = pxa250_initfn },
620 { .name = "pxa255", .initfn = pxa255_initfn },
621 { .name = "pxa260", .initfn = pxa260_initfn },
622 { .name = "pxa261", .initfn = pxa261_initfn },
623 { .name = "pxa262", .initfn = pxa262_initfn },
624 /* "pxa270" is an alias for "pxa270-a0" */
625 { .name = "pxa270", .initfn = pxa270a0_initfn },
626 { .name = "pxa270-a0", .initfn = pxa270a0_initfn },
627 { .name = "pxa270-a1", .initfn = pxa270a1_initfn },
628 { .name = "pxa270-b0", .initfn = pxa270b0_initfn },
629 { .name = "pxa270-b1", .initfn = pxa270b1_initfn },
630 { .name = "pxa270-c0", .initfn = pxa270c0_initfn },
631 { .name = "pxa270-c5", .initfn = pxa270c5_initfn },
632 { .name = "any", .initfn = arm_any_initfn },
633};
634
dec9c2d4
AF		 635static void arm_cpu_class_init(ObjectClass *oc, void *data)
636{
637 ARMCPUClass *acc = ARM_CPU_CLASS(oc);
638 CPUClass *cc = CPU_CLASS(acc);
639
640 acc->parent_reset = cc->reset;
641 cc->reset = arm_cpu_reset;
642}
643
777dc784
PM		 644static void cpu_register(const ARMCPUInfo *info)
645{
646 TypeInfo type_info = {
647 .name = info->name,
648 .parent = TYPE_ARM_CPU,
649 .instance_size = sizeof(ARMCPU),
650 .instance_init = info->initfn,
651 .class_size = sizeof(ARMCPUClass),
652 };
653
654 type_register_static(&type_info);
655}
656
dec9c2d4
AF		 657static const TypeInfo arm_cpu_type_info = {
658 .name = TYPE_ARM_CPU,
659 .parent = TYPE_CPU,
660 .instance_size = sizeof(ARMCPU),
777dc784
PM		 661 .instance_init = arm_cpu_initfn,
662 .abstract = true,
dec9c2d4
AF		 663 .class_size = sizeof(ARMCPUClass),
664 .class_init = arm_cpu_class_init,
665};
666
667static void arm_cpu_register_types(void)
668{
777dc784
PM		 669 int i;
670
dec9c2d4 671 type_register_static(&arm_cpu_type_info);
777dc784
PM		 672 for (i = 0; i < ARRAY_SIZE(arm_cpus); i++) {
673 cpu_register(&arm_cpus[i]);
674 }
dec9c2d4
AF		 675}
676
677type_init(arm_cpu_register_types)
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