projects / qemu.git / blame
| Commit | Line | Data |
|---|---|---|
| aaa2ebc5 | 1 | -include ../../../config-host.mak |
| 7d890b40 | 2 | |
| a2e67072 MF |
3 | CORE=dc232b |
| 4 | CROSS=xtensa-$(CORE)-elf- | |
| 7d890b40 MF |
5 | |
| 6 | ifndef XT | |
| aaa2ebc5 | 7 | SIM = ../../../xtensa-softmmu/qemu-system-xtensa |
| a2e67072 | 8 | SIMFLAGS = -M sim -cpu $(CORE) -nographic -semihosting $(EXTFLAGS) -kernel |
| 7d890b40 MF |
9 | SIMDEBUG = -s -S |
| 10 | else | |
| 11 | SIM = xt-run | |
| 12 | SIMFLAGS = --xtensa-core=DC_B_232L --exit_with_target_code $(EXTFLAGS) | |
| 13 | SIMDEBUG = --gdbserve=0 | |
| 14 | endif | |
| 15 | ||
| 20303e42 | 16 | HOST_CC = gcc |
| 7d890b40 | 17 | CC = $(CROSS)gcc |
| aaa2ebc5 | 18 | AS = $(CROSS)gcc -x assembler-with-cpp |
| 7d890b40 MF |
19 | LD = $(CROSS)ld |
| 20 | ||
| aaa2ebc5 | 21 | XTENSA_SRC_PATH = $(SRC_PATH)/tests/tcg/xtensa |
| a2e67072 MF |
22 | INCLUDE_DIRS = $(XTENSA_SRC_PATH) $(SRC_PATH)/target-xtensa/core-$(CORE) |
| 23 | XTENSA_INC = $(addprefix -I,$(INCLUDE_DIRS)) | |
| aaa2ebc5 | 24 | |
| 20303e42 | 25 | LDFLAGS = -Tlinker.ld |
| 7d890b40 MF |
26 | |
| 27 | CRT = crt.o vectors.o | |
| 28 | ||
| 29 | TESTCASES += test_b.tst | |
| 30 | TESTCASES += test_bi.tst | |
| 31 | #TESTCASES += test_boolean.tst | |
| e7dfa64d | 32 | TESTCASES += test_break.tst |
| 7d890b40 | 33 | TESTCASES += test_bz.tst |
| 2c09eee1 | 34 | TESTCASES += test_cache.tst |
| 7d890b40 | 35 | TESTCASES += test_clamps.tst |
| 7be9d0e6 | 36 | TESTCASES += test_extui.tst |
| 7d890b40 MF |
37 | TESTCASES += test_fail.tst |
| 38 | TESTCASES += test_interrupt.tst | |
| 39 | TESTCASES += test_loop.tst | |
| e7e9af5c | 40 | TESTCASES += test_mac16.tst |
| 7d890b40 MF |
41 | TESTCASES += test_max.tst |
| 42 | TESTCASES += test_min.tst | |
| 43 | TESTCASES += test_mmu.tst | |
| 44 | TESTCASES += test_mul16.tst | |
| 45 | TESTCASES += test_mul32.tst | |
| 46 | TESTCASES += test_nsa.tst | |
| 47 | ifdef XT | |
| 48 | TESTCASES += test_pipeline.tst | |
| 49 | endif | |
| 50 | TESTCASES += test_quo.tst | |
| 51 | TESTCASES += test_rem.tst | |
| 52 | TESTCASES += test_rst0.tst | |
| 5dacd229 | 53 | TESTCASES += test_s32c1i.tst |
| 7d890b40 MF |
54 | TESTCASES += test_sar.tst |
| 55 | TESTCASES += test_sext.tst | |
| 56 | TESTCASES += test_shift.tst | |
| efdfac94 | 57 | TESTCASES += test_sr.tst |
| 7d890b40 MF |
58 | TESTCASES += test_timer.tst |
| 59 | TESTCASES += test_windowed.tst | |
| 60 | ||
| 61 | all: build | |
| 62 | ||
| 20303e42 MF |
63 | linker.ld: $(XTENSA_SRC_PATH)/linker.ld.S |
| 64 | $(HOST_CC) $(XTENSA_INC) -E -P $< -o $@ | |
| 65 | ||
| aaa2ebc5 | 66 | %.o: $(XTENSA_SRC_PATH)/%.c |
| a2e67072 | 67 | $(CC) $(XTENSA_INC) $(CFLAGS) -c $< -o $@ |
| 7d890b40 | 68 | |
| aaa2ebc5 | 69 | %.o: $(XTENSA_SRC_PATH)/%.S |
| a2e67072 | 70 | $(CC) $(XTENSA_INC) $(ASFLAGS) -c $< -o $@ |
| 7d890b40 | 71 | |
| 20303e42 | 72 | %.tst: %.o linker.ld $(XTENSA_SRC_PATH)/macros.inc $(CRT) Makefile |
| 7d890b40 MF |
73 | $(LD) $(LDFLAGS) $(NOSTDFLAGS) $(CRT) $< -o $@ |
| 74 | ||
| 75 | build: $(TESTCASES) | |
| 76 | ||
| 77 | check: $(addprefix run-, $(TESTCASES)) | |
| 78 | ||
| 79 | run-%.tst: %.tst | |
| 80 | $(SIM) $(SIMFLAGS) ./$< | |
| 81 | ||
| 82 | run-test_fail.tst: test_fail.tst | |
| 83 | ! $(SIM) $(SIMFLAGS) ./$< | |
| 84 | ||
| 85 | debug-%.tst: %.tst | |
| 86 | $(SIM) $(SIMDEBUG) $(SIMFLAGS) ./$< | |
| 87 | ||
| 7d6b9f0a MF |
88 | host-debug-%.tst: %.tst |
| 89 | gdb --args $(SIM) $(SIMFLAGS) ./$< | |
| 90 | ||
| 7d890b40 | 91 | clean: |
| 20303e42 | 92 | $(RM) -fr $(TESTCASES) $(CRT) linker.ld |