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Commit | Line | Data |
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244ab90e AL |
1 | /* |
2 | * DMA helper functions | |
3 | * | |
4 | * Copyright (c) 2009 Red Hat | |
5 | * | |
6 | * This work is licensed under the terms of the GNU General Public License | |
7 | * (GNU GPL), version 2 or later. | |
8 | */ | |
9 | ||
d38ea87a | 10 | #include "qemu/osdep.h" |
4be74634 | 11 | #include "sysemu/block-backend.h" |
9c17d615 | 12 | #include "sysemu/dma.h" |
c57c4658 | 13 | #include "trace.h" |
1de7afc9 | 14 | #include "qemu/thread.h" |
6a1751b7 | 15 | #include "qemu/main-loop.h" |
244ab90e | 16 | |
e5332e63 DG |
17 | /* #define DEBUG_IOMMU */ |
18 | ||
df32fd1c | 19 | int dma_memory_set(AddressSpace *as, dma_addr_t addr, uint8_t c, dma_addr_t len) |
d86a77f8 | 20 | { |
df32fd1c | 21 | dma_barrier(as, DMA_DIRECTION_FROM_DEVICE); |
24addbc7 | 22 | |
d86a77f8 DG |
23 | #define FILLBUF_SIZE 512 |
24 | uint8_t fillbuf[FILLBUF_SIZE]; | |
25 | int l; | |
24addbc7 | 26 | bool error = false; |
d86a77f8 DG |
27 | |
28 | memset(fillbuf, c, FILLBUF_SIZE); | |
29 | while (len > 0) { | |
30 | l = len < FILLBUF_SIZE ? len : FILLBUF_SIZE; | |
5c9eb028 PM |
31 | error |= address_space_rw(as, addr, MEMTXATTRS_UNSPECIFIED, |
32 | fillbuf, l, true); | |
bc9b78de BH |
33 | len -= l; |
34 | addr += l; | |
d86a77f8 | 35 | } |
e5332e63 | 36 | |
24addbc7 | 37 | return error; |
d86a77f8 DG |
38 | } |
39 | ||
f487b677 PB |
40 | void qemu_sglist_init(QEMUSGList *qsg, DeviceState *dev, int alloc_hint, |
41 | AddressSpace *as) | |
244ab90e | 42 | { |
7267c094 | 43 | qsg->sg = g_malloc(alloc_hint * sizeof(ScatterGatherEntry)); |
244ab90e AL |
44 | qsg->nsg = 0; |
45 | qsg->nalloc = alloc_hint; | |
46 | qsg->size = 0; | |
df32fd1c | 47 | qsg->as = as; |
f487b677 PB |
48 | qsg->dev = dev; |
49 | object_ref(OBJECT(dev)); | |
244ab90e AL |
50 | } |
51 | ||
d3231181 | 52 | void qemu_sglist_add(QEMUSGList *qsg, dma_addr_t base, dma_addr_t len) |
244ab90e AL |
53 | { |
54 | if (qsg->nsg == qsg->nalloc) { | |
55 | qsg->nalloc = 2 * qsg->nalloc + 1; | |
7267c094 | 56 | qsg->sg = g_realloc(qsg->sg, qsg->nalloc * sizeof(ScatterGatherEntry)); |
244ab90e AL |
57 | } |
58 | qsg->sg[qsg->nsg].base = base; | |
59 | qsg->sg[qsg->nsg].len = len; | |
60 | qsg->size += len; | |
61 | ++qsg->nsg; | |
62 | } | |
63 | ||
64 | void qemu_sglist_destroy(QEMUSGList *qsg) | |
65 | { | |
f487b677 | 66 | object_unref(OBJECT(qsg->dev)); |
7267c094 | 67 | g_free(qsg->sg); |
ea8d82a1 | 68 | memset(qsg, 0, sizeof(*qsg)); |
244ab90e AL |
69 | } |
70 | ||
59a703eb | 71 | typedef struct { |
7c84b1b8 | 72 | BlockAIOCB common; |
8a8e63eb | 73 | AioContext *ctx; |
7c84b1b8 | 74 | BlockAIOCB *acb; |
59a703eb | 75 | QEMUSGList *sg; |
99868af3 | 76 | uint32_t align; |
d4f510eb | 77 | uint64_t offset; |
43cf8ae6 | 78 | DMADirection dir; |
59a703eb | 79 | int sg_cur_index; |
d3231181 | 80 | dma_addr_t sg_cur_byte; |
59a703eb AL |
81 | QEMUIOVector iov; |
82 | QEMUBH *bh; | |
cb144ccb | 83 | DMAIOFunc *io_func; |
8a8e63eb | 84 | void *io_func_opaque; |
37b7842c | 85 | } DMAAIOCB; |
59a703eb | 86 | |
4be74634 | 87 | static void dma_blk_cb(void *opaque, int ret); |
59a703eb AL |
88 | |
89 | static void reschedule_dma(void *opaque) | |
90 | { | |
37b7842c | 91 | DMAAIOCB *dbs = (DMAAIOCB *)opaque; |
59a703eb AL |
92 | |
93 | qemu_bh_delete(dbs->bh); | |
94 | dbs->bh = NULL; | |
4be74634 | 95 | dma_blk_cb(dbs, 0); |
59a703eb AL |
96 | } |
97 | ||
4be74634 | 98 | static void dma_blk_unmap(DMAAIOCB *dbs) |
59a703eb | 99 | { |
59a703eb AL |
100 | int i; |
101 | ||
59a703eb | 102 | for (i = 0; i < dbs->iov.niov; ++i) { |
df32fd1c | 103 | dma_memory_unmap(dbs->sg->as, dbs->iov.iov[i].iov_base, |
c65bcef3 DG |
104 | dbs->iov.iov[i].iov_len, dbs->dir, |
105 | dbs->iov.iov[i].iov_len); | |
59a703eb | 106 | } |
c3adb5b9 PB |
107 | qemu_iovec_reset(&dbs->iov); |
108 | } | |
109 | ||
110 | static void dma_complete(DMAAIOCB *dbs, int ret) | |
111 | { | |
c57c4658 KW |
112 | trace_dma_complete(dbs, ret, dbs->common.cb); |
113 | ||
4be74634 | 114 | dma_blk_unmap(dbs); |
c3adb5b9 PB |
115 | if (dbs->common.cb) { |
116 | dbs->common.cb(dbs->common.opaque, ret); | |
117 | } | |
118 | qemu_iovec_destroy(&dbs->iov); | |
119 | if (dbs->bh) { | |
120 | qemu_bh_delete(dbs->bh); | |
121 | dbs->bh = NULL; | |
122 | } | |
8007429a | 123 | qemu_aio_unref(dbs); |
7403b14e AL |
124 | } |
125 | ||
4be74634 | 126 | static void dma_blk_cb(void *opaque, int ret) |
7403b14e AL |
127 | { |
128 | DMAAIOCB *dbs = (DMAAIOCB *)opaque; | |
c65bcef3 | 129 | dma_addr_t cur_addr, cur_len; |
7403b14e AL |
130 | void *mem; |
131 | ||
4be74634 | 132 | trace_dma_blk_cb(dbs, ret); |
c57c4658 | 133 | |
7403b14e | 134 | dbs->acb = NULL; |
d4f510eb | 135 | dbs->offset += dbs->iov.size; |
59a703eb AL |
136 | |
137 | if (dbs->sg_cur_index == dbs->sg->nsg || ret < 0) { | |
c3adb5b9 | 138 | dma_complete(dbs, ret); |
59a703eb AL |
139 | return; |
140 | } | |
4be74634 | 141 | dma_blk_unmap(dbs); |
59a703eb AL |
142 | |
143 | while (dbs->sg_cur_index < dbs->sg->nsg) { | |
144 | cur_addr = dbs->sg->sg[dbs->sg_cur_index].base + dbs->sg_cur_byte; | |
145 | cur_len = dbs->sg->sg[dbs->sg_cur_index].len - dbs->sg_cur_byte; | |
df32fd1c | 146 | mem = dma_memory_map(dbs->sg->as, cur_addr, &cur_len, dbs->dir); |
59a703eb AL |
147 | if (!mem) |
148 | break; | |
149 | qemu_iovec_add(&dbs->iov, mem, cur_len); | |
150 | dbs->sg_cur_byte += cur_len; | |
151 | if (dbs->sg_cur_byte == dbs->sg->sg[dbs->sg_cur_index].len) { | |
152 | dbs->sg_cur_byte = 0; | |
153 | ++dbs->sg_cur_index; | |
154 | } | |
155 | } | |
156 | ||
157 | if (dbs->iov.size == 0) { | |
c57c4658 | 158 | trace_dma_map_wait(dbs); |
8a8e63eb | 159 | dbs->bh = aio_bh_new(dbs->ctx, reschedule_dma, dbs); |
e95205e1 | 160 | cpu_register_map_client(dbs->bh); |
59a703eb AL |
161 | return; |
162 | } | |
163 | ||
99868af3 MCA |
164 | if (!QEMU_IS_ALIGNED(dbs->iov.size, dbs->align)) { |
165 | qemu_iovec_discard_back(&dbs->iov, | |
166 | QEMU_ALIGN_DOWN(dbs->iov.size, dbs->align)); | |
58f423fb KW |
167 | } |
168 | ||
8a8e63eb PB |
169 | dbs->acb = dbs->io_func(dbs->offset, &dbs->iov, |
170 | dma_blk_cb, dbs, dbs->io_func_opaque); | |
6bee44ea | 171 | assert(dbs->acb); |
59a703eb AL |
172 | } |
173 | ||
7c84b1b8 | 174 | static void dma_aio_cancel(BlockAIOCB *acb) |
c16b5a2c CH |
175 | { |
176 | DMAAIOCB *dbs = container_of(acb, DMAAIOCB, common); | |
177 | ||
c57c4658 KW |
178 | trace_dma_aio_cancel(dbs); |
179 | ||
c16b5a2c | 180 | if (dbs->acb) { |
4be74634 | 181 | blk_aio_cancel_async(dbs->acb); |
c16b5a2c | 182 | } |
e95205e1 FZ |
183 | if (dbs->bh) { |
184 | cpu_unregister_map_client(dbs->bh); | |
185 | qemu_bh_delete(dbs->bh); | |
186 | dbs->bh = NULL; | |
187 | } | |
c16b5a2c CH |
188 | } |
189 | ||
5fa78b2a SH |
190 | static AioContext *dma_get_aio_context(BlockAIOCB *acb) |
191 | { | |
192 | DMAAIOCB *dbs = container_of(acb, DMAAIOCB, common); | |
193 | ||
194 | return dbs->ctx; | |
195 | } | |
9bb9da46 | 196 | |
d7331bed | 197 | static const AIOCBInfo dma_aiocb_info = { |
c16b5a2c | 198 | .aiocb_size = sizeof(DMAAIOCB), |
9bb9da46 | 199 | .cancel_async = dma_aio_cancel, |
5fa78b2a | 200 | .get_aio_context = dma_get_aio_context, |
c16b5a2c CH |
201 | }; |
202 | ||
8a8e63eb | 203 | BlockAIOCB *dma_blk_io(AioContext *ctx, |
99868af3 | 204 | QEMUSGList *sg, uint64_t offset, uint32_t align, |
8a8e63eb PB |
205 | DMAIOFunc *io_func, void *io_func_opaque, |
206 | BlockCompletionFunc *cb, | |
43cf8ae6 | 207 | void *opaque, DMADirection dir) |
59a703eb | 208 | { |
8a8e63eb | 209 | DMAAIOCB *dbs = qemu_aio_get(&dma_aiocb_info, NULL, cb, opaque); |
59a703eb | 210 | |
8a8e63eb | 211 | trace_dma_blk_io(dbs, io_func_opaque, offset, (dir == DMA_DIRECTION_TO_DEVICE)); |
c57c4658 | 212 | |
37b7842c | 213 | dbs->acb = NULL; |
59a703eb | 214 | dbs->sg = sg; |
8a8e63eb | 215 | dbs->ctx = ctx; |
cbe0ed62 | 216 | dbs->offset = offset; |
99868af3 | 217 | dbs->align = align; |
59a703eb AL |
218 | dbs->sg_cur_index = 0; |
219 | dbs->sg_cur_byte = 0; | |
43cf8ae6 | 220 | dbs->dir = dir; |
cb144ccb | 221 | dbs->io_func = io_func; |
8a8e63eb | 222 | dbs->io_func_opaque = io_func_opaque; |
59a703eb AL |
223 | dbs->bh = NULL; |
224 | qemu_iovec_init(&dbs->iov, sg->nsg); | |
4be74634 | 225 | dma_blk_cb(dbs, 0); |
37b7842c | 226 | return &dbs->common; |
59a703eb AL |
227 | } |
228 | ||
229 | ||
8a8e63eb PB |
230 | static |
231 | BlockAIOCB *dma_blk_read_io_func(int64_t offset, QEMUIOVector *iov, | |
232 | BlockCompletionFunc *cb, void *cb_opaque, | |
233 | void *opaque) | |
234 | { | |
235 | BlockBackend *blk = opaque; | |
236 | return blk_aio_preadv(blk, offset, iov, 0, cb, cb_opaque); | |
237 | } | |
238 | ||
4be74634 | 239 | BlockAIOCB *dma_blk_read(BlockBackend *blk, |
99868af3 | 240 | QEMUSGList *sg, uint64_t offset, uint32_t align, |
4be74634 | 241 | void (*cb)(void *opaque, int ret), void *opaque) |
59a703eb | 242 | { |
99868af3 MCA |
243 | return dma_blk_io(blk_get_aio_context(blk), sg, offset, align, |
244 | dma_blk_read_io_func, blk, cb, opaque, | |
4be74634 | 245 | DMA_DIRECTION_FROM_DEVICE); |
59a703eb AL |
246 | } |
247 | ||
8a8e63eb PB |
248 | static |
249 | BlockAIOCB *dma_blk_write_io_func(int64_t offset, QEMUIOVector *iov, | |
250 | BlockCompletionFunc *cb, void *cb_opaque, | |
251 | void *opaque) | |
252 | { | |
253 | BlockBackend *blk = opaque; | |
254 | return blk_aio_pwritev(blk, offset, iov, 0, cb, cb_opaque); | |
255 | } | |
256 | ||
4be74634 | 257 | BlockAIOCB *dma_blk_write(BlockBackend *blk, |
99868af3 | 258 | QEMUSGList *sg, uint64_t offset, uint32_t align, |
4be74634 | 259 | void (*cb)(void *opaque, int ret), void *opaque) |
59a703eb | 260 | { |
99868af3 MCA |
261 | return dma_blk_io(blk_get_aio_context(blk), sg, offset, align, |
262 | dma_blk_write_io_func, blk, cb, opaque, | |
4be74634 | 263 | DMA_DIRECTION_TO_DEVICE); |
59a703eb | 264 | } |
8171ee35 PB |
265 | |
266 | ||
c65bcef3 DG |
267 | static uint64_t dma_buf_rw(uint8_t *ptr, int32_t len, QEMUSGList *sg, |
268 | DMADirection dir) | |
8171ee35 PB |
269 | { |
270 | uint64_t resid; | |
271 | int sg_cur_index; | |
272 | ||
273 | resid = sg->size; | |
274 | sg_cur_index = 0; | |
275 | len = MIN(len, resid); | |
276 | while (len > 0) { | |
277 | ScatterGatherEntry entry = sg->sg[sg_cur_index++]; | |
278 | int32_t xfer = MIN(len, entry.len); | |
df32fd1c | 279 | dma_memory_rw(sg->as, entry.base, ptr, xfer, dir); |
8171ee35 PB |
280 | ptr += xfer; |
281 | len -= xfer; | |
282 | resid -= xfer; | |
283 | } | |
284 | ||
285 | return resid; | |
286 | } | |
287 | ||
288 | uint64_t dma_buf_read(uint8_t *ptr, int32_t len, QEMUSGList *sg) | |
289 | { | |
c65bcef3 | 290 | return dma_buf_rw(ptr, len, sg, DMA_DIRECTION_FROM_DEVICE); |
8171ee35 PB |
291 | } |
292 | ||
293 | uint64_t dma_buf_write(uint8_t *ptr, int32_t len, QEMUSGList *sg) | |
294 | { | |
c65bcef3 | 295 | return dma_buf_rw(ptr, len, sg, DMA_DIRECTION_TO_DEVICE); |
8171ee35 | 296 | } |
84a69356 | 297 | |
4be74634 | 298 | void dma_acct_start(BlockBackend *blk, BlockAcctCookie *cookie, |
84a69356 PB |
299 | QEMUSGList *sg, enum BlockAcctType type) |
300 | { | |
4be74634 | 301 | block_acct_start(blk_get_stats(blk), cookie, sg->size, type); |
84a69356 | 302 | } |