[qemu.git] / hw / isa / pc87312.c

/*
 * QEMU National Semiconductor PC87312 (Super I/O)
 *
 * Copyright (c) 2010-2012 Herve Poussineau
 * Copyright (c) 2011-2012 Andreas Färber
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */

#include "hw/isa/pc87312.h"
#include "qemu/error-report.h"
#include "sysemu/blockdev.h"
#include "sysemu/sysemu.h"
#include "sysemu/char.h"
#include "trace.h"


#define REG_FER 0
#define REG_FAR 1
#define REG_PTR 2

#define FER_PARALLEL_EN   0x01
#define FER_UART1_EN      0x02
#define FER_UART2_EN      0x04
#define FER_FDC_EN        0x08
#define FER_FDC_4         0x10
#define FER_FDC_ADDR      0x20
#define FER_IDE_EN        0x40
#define FER_IDE_ADDR      0x80

#define FAR_PARALLEL_ADDR 0x03
#define FAR_UART1_ADDR    0x0C
#define FAR_UART2_ADDR    0x30
#define FAR_UART_3_4      0xC0

#define PTR_POWER_DOWN    0x01
#define PTR_CLOCK_DOWN    0x02
#define PTR_PWDN          0x04
#define PTR_IRQ_5_7       0x08
#define PTR_UART1_TEST    0x10
#define PTR_UART2_TEST    0x20
#define PTR_LOCK_CONF     0x40
#define PTR_EPP_MODE      0x80


/* Parallel port */

static inline bool is_parallel_enabled(PC87312State *s)
{
    return s->regs[REG_FER] & FER_PARALLEL_EN;
}

static const uint32_t parallel_base[] = { 0x378, 0x3bc, 0x278, 0x00 };

static inline uint32_t get_parallel_iobase(PC87312State *s)
{
    return parallel_base[s->regs[REG_FAR] & FAR_PARALLEL_ADDR];
}

static const uint32_t parallel_irq[] = { 5, 7, 5, 0 };

static inline uint32_t get_parallel_irq(PC87312State *s)
{
    int idx;
    idx = (s->regs[REG_FAR] & FAR_PARALLEL_ADDR);
    if (idx == 0) {
        return (s->regs[REG_PTR] & PTR_IRQ_5_7) ? 7 : 5;
    } else {
        return parallel_irq[idx];
    }
}

static inline bool is_parallel_epp(PC87312State *s)
{
    return s->regs[REG_PTR] & PTR_EPP_MODE;
}


/* UARTs */

static const uint32_t uart_base[2][4] = {
    { 0x3e8, 0x338, 0x2e8, 0x220 },
    { 0x2e8, 0x238, 0x2e0, 0x228 }
};

static inline uint32_t get_uart_iobase(PC87312State *s, int i)
{
    int idx;
    idx = (s->regs[REG_FAR] >> (2 * i + 2)) & 0x3;
    if (idx == 0) {
        return 0x3f8;
    } else if (idx == 1) {
        return 0x2f8;
    } else {
        return uart_base[idx & 1][(s->regs[REG_FAR] & FAR_UART_3_4) >> 6];
    }
}

static inline uint32_t get_uart_irq(PC87312State *s, int i)
{
    int idx;
    idx = (s->regs[REG_FAR] >> (2 * i + 2)) & 0x3;
    return (idx & 1) ? 3 : 4;
}

static inline bool is_uart_enabled(PC87312State *s, int i)
{
    return s->regs[REG_FER] & (FER_UART1_EN << i);
}


/* Floppy controller */

static inline bool is_fdc_enabled(PC87312State *s)
{
    return s->regs[REG_FER] & FER_FDC_EN;
}

static inline uint32_t get_fdc_iobase(PC87312State *s)
{
    return (s->regs[REG_FER] & FER_FDC_ADDR) ? 0x370 : 0x3f0;
}


/* IDE controller */

static inline bool is_ide_enabled(PC87312State *s)
{
    return s->regs[REG_FER] & FER_IDE_EN;
}

static inline uint32_t get_ide_iobase(PC87312State *s)
{
    return (s->regs[REG_FER] & FER_IDE_ADDR) ? 0x170 : 0x1f0;
}


static void reconfigure_devices(PC87312State *s)
{
    error_report("pc87312: unsupported device reconfiguration (%02x %02x %02x)",
                 s->regs[REG_FER], s->regs[REG_FAR], s->regs[REG_PTR]);
}

static void pc87312_soft_reset(PC87312State *s)
{
    static const uint8_t fer_init[] = {
        0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4b, 0x4b,
        0x4b, 0x4b, 0x4b, 0x4b, 0x0f, 0x0f, 0x0f, 0x0f,
        0x49, 0x49, 0x49, 0x49, 0x07, 0x07, 0x07, 0x07,
        0x47, 0x47, 0x47, 0x47, 0x47, 0x47, 0x08, 0x00,
    };
    static const uint8_t far_init[] = {
        0x10, 0x11, 0x11, 0x39, 0x24, 0x38, 0x00, 0x01,
        0x01, 0x09, 0x08, 0x08, 0x10, 0x11, 0x39, 0x24,
        0x00, 0x01, 0x01, 0x00, 0x10, 0x11, 0x39, 0x24,
        0x10, 0x11, 0x11, 0x39, 0x24, 0x38, 0x10, 0x10,
    };
    static const uint8_t ptr_init[] = {
        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02,
    };

    s->read_id_step = 0;
    s->selected_index = REG_FER;

    s->regs[REG_FER] = fer_init[s->config & 0x1f];
    s->regs[REG_FAR] = far_init[s->config & 0x1f];
    s->regs[REG_PTR] = ptr_init[s->config & 0x1f];
}

static void pc87312_hard_reset(PC87312State *s)
{
    pc87312_soft_reset(s);
}

static void pc87312_io_write(void *opaque, hwaddr addr, uint64_t val,
                             unsigned int size)
{
    PC87312State *s = opaque;

    trace_pc87312_io_write(addr, val);

    if ((addr & 1) == 0) {
        /* Index register */
        s->read_id_step = 2;
        s->selected_index = val;
    } else {
        /* Data register */
        if (s->selected_index < 3) {
            s->regs[s->selected_index] = val;
            reconfigure_devices(s);
        }
    }
}

static uint64_t pc87312_io_read(void *opaque, hwaddr addr, unsigned int size)
{
    PC87312State *s = opaque;
    uint32_t val;

    if ((addr & 1) == 0) {
        /* Index register */
        if (s->read_id_step++ == 0) {
            val = 0x88;
        } else if (s->read_id_step++ == 1) {
            val = 0;
        } else {
            val = s->selected_index;
        }
    } else {
        /* Data register */
        if (s->selected_index < 3) {
            val = s->regs[s->selected_index];
        } else {
            /* Invalid selected index */
            val = 0;
        }
    }

    trace_pc87312_io_read(addr, val);
    return val;
}

static const MemoryRegionOps pc87312_io_ops = {
    .read  = pc87312_io_read,
    .write = pc87312_io_write,
    .endianness = DEVICE_LITTLE_ENDIAN,
    .valid = {
        .min_access_size = 1,
        .max_access_size = 1,
    },
};

static int pc87312_post_load(void *opaque, int version_id)
{
    PC87312State *s = opaque;

    reconfigure_devices(s);
    return 0;
}

static void pc87312_reset(DeviceState *d)
{
    PC87312State *s = PC87312(d);

    pc87312_soft_reset(s);
}

static void pc87312_realize(DeviceState *dev, Error **errp)
{
    PC87312State *s;
    DeviceState *d;
    ISADevice *isa;
    ISABus *bus;
    CharDriverState *chr;
    DriveInfo *drive;
    char name[5];
    int i;

    s = PC87312(dev);
    isa = ISA_DEVICE(dev);
    bus = isa_bus_from_device(isa);
    isa_register_ioport(isa, &s->io, s->iobase);
    pc87312_hard_reset(s);

    if (is_parallel_enabled(s)) {
        chr = parallel_hds[0];
        if (chr == NULL) {
            chr = qemu_chr_new("par0", "null", NULL);
        }
        isa = isa_create(bus, "isa-parallel");
        d = DEVICE(isa);
        qdev_prop_set_uint32(d, "index", 0);
        qdev_prop_set_uint32(d, "iobase", get_parallel_iobase(s));
        qdev_prop_set_uint32(d, "irq", get_parallel_irq(s));
        qdev_prop_set_chr(d, "chardev", chr);
        qdev_init_nofail(d);
        s->parallel.dev = isa;
        trace_pc87312_info_parallel(get_parallel_iobase(s),
                                    get_parallel_irq(s));
    }

    for (i = 0; i < 2; i++) {
        if (is_uart_enabled(s, i)) {
            chr = serial_hds[i];
            if (chr == NULL) {
                snprintf(name, sizeof(name), "ser%d", i);
                chr = qemu_chr_new(name, "null", NULL);
            }
            isa = isa_create(bus, "isa-serial");
            d = DEVICE(isa);
            qdev_prop_set_uint32(d, "index", i);
            qdev_prop_set_uint32(d, "iobase", get_uart_iobase(s, i));
            qdev_prop_set_uint32(d, "irq", get_uart_irq(s, i));
            qdev_prop_set_chr(d, "chardev", chr);
            qdev_init_nofail(d);
            s->uart[i].dev = isa;
            trace_pc87312_info_serial(i, get_uart_iobase(s, i),
                                      get_uart_irq(s, i));
        }
    }

    if (is_fdc_enabled(s)) {
        isa = isa_create(bus, "isa-fdc");
        d = DEVICE(isa);
        qdev_prop_set_uint32(d, "iobase", get_fdc_iobase(s));
        qdev_prop_set_uint32(d, "irq", 6);
        drive = drive_get(IF_FLOPPY, 0, 0);
        if (drive != NULL) {
            qdev_prop_set_drive_nofail(d, "driveA", drive->bdrv);
        }
        drive = drive_get(IF_FLOPPY, 0, 1);
        if (drive != NULL) {
            qdev_prop_set_drive_nofail(d, "driveB", drive->bdrv);
        }
        qdev_init_nofail(d);
        s->fdc.dev = isa;
        trace_pc87312_info_floppy(get_fdc_iobase(s));
    }

    if (is_ide_enabled(s)) {
        isa = isa_create(bus, "isa-ide");
        d = DEVICE(isa);
        qdev_prop_set_uint32(d, "iobase", get_ide_iobase(s));
        qdev_prop_set_uint32(d, "iobase2", get_ide_iobase(s) + 0x206);
        qdev_prop_set_uint32(d, "irq", 14);
        qdev_init_nofail(d);
        s->ide.dev = isa;
        trace_pc87312_info_ide(get_ide_iobase(s));
    }
}

static void pc87312_initfn(Object *obj)
{
    PC87312State *s = PC87312(obj);

    memory_region_init_io(&s->io, obj, &pc87312_io_ops, s, "pc87312", 2);
}

static const VMStateDescription vmstate_pc87312 = {
    .name = "pc87312",
    .version_id = 1,
    .minimum_version_id = 1,
    .post_load = pc87312_post_load,
    .fields = (VMStateField[]) {
        VMSTATE_UINT8(read_id_step, PC87312State),
        VMSTATE_UINT8(selected_index, PC87312State),
        VMSTATE_UINT8_ARRAY(regs, PC87312State, 3),
        VMSTATE_END_OF_LIST()
    }
};

static Property pc87312_properties[] = {
    DEFINE_PROP_HEX32("iobase", PC87312State, iobase, 0x398),
    DEFINE_PROP_UINT8("config", PC87312State, config, 1),
    DEFINE_PROP_END_OF_LIST()
};

static void pc87312_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);

    dc->realize = pc87312_realize;
    dc->reset = pc87312_reset;
    dc->vmsd = &vmstate_pc87312;
    dc->props = pc87312_properties;
}

static const TypeInfo pc87312_type_info = {
    .name          = TYPE_PC87312,
    .parent        = TYPE_ISA_DEVICE,
    .instance_size = sizeof(PC87312State),
    .instance_init = pc87312_initfn,
    .class_init    = pc87312_class_init,
};

static void pc87312_register_types(void)
{
    type_register_static(&pc87312_type_info);
}

type_init(pc87312_register_types)
Commit	Line	Data
1ae41f44 HP	1	/*
	2	* QEMU National Semiconductor PC87312 (Super I/O)
	3	*
	4	* Copyright (c) 2010-2012 Herve Poussineau
	5	* Copyright (c) 2011-2012 Andreas Färber
	6	*
	7	* Permission is hereby granted, free of charge, to any person obtaining a copy
	8	* of this software and associated documentation files (the "Software"), to deal
	9	* in the Software without restriction, including without limitation the rights
	10	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	11	* copies of the Software, and to permit persons to whom the Software is
	12	* furnished to do so, subject to the following conditions:
	13	*
	14	* The above copyright notice and this permission notice shall be included in
	15	* all copies or substantial portions of the Software.
	16	*
	17	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	18	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	19	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	20	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	21	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	22	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	23	* THE SOFTWARE.
	24	*/
	25
0d09e41a	26	#include "hw/isa/pc87312.h"
b4a42f81	27	#include "qemu/error-report.h"
63e3555e AF	28	#include "sysemu/blockdev.h"
63e3555e AF	29	#include "sysemu/sysemu.h"
dccfcd0e	30	#include "sysemu/char.h"
1ae41f44 HP	31	#include "trace.h"
	32
	33
	34	#define REG_FER 0
	35	#define REG_FAR 1
	36	#define REG_PTR 2
	37
1ae41f44 HP	38	#define FER_PARALLEL_EN 0x01
	39	#define FER_UART1_EN 0x02
	40	#define FER_UART2_EN 0x04
	41	#define FER_FDC_EN 0x08
	42	#define FER_FDC_4 0x10
	43	#define FER_FDC_ADDR 0x20
	44	#define FER_IDE_EN 0x40
	45	#define FER_IDE_ADDR 0x80
	46
	47	#define FAR_PARALLEL_ADDR 0x03
	48	#define FAR_UART1_ADDR 0x0C
	49	#define FAR_UART2_ADDR 0x30
	50	#define FAR_UART_3_4 0xC0
	51
	52	#define PTR_POWER_DOWN 0x01
	53	#define PTR_CLOCK_DOWN 0x02
	54	#define PTR_PWDN 0x04
	55	#define PTR_IRQ_5_7 0x08
	56	#define PTR_UART1_TEST 0x10
	57	#define PTR_UART2_TEST 0x20
	58	#define PTR_LOCK_CONF 0x40
	59	#define PTR_EPP_MODE 0x80
	60
	61
	62	/* Parallel port */
	63
	64	static inline bool is_parallel_enabled(PC87312State *s)
	65	{
08bb4a7c	66	return s->regs[REG_FER] & FER_PARALLEL_EN;
1ae41f44 HP	67	}
	68
	69	static const uint32_t parallel_base[] = { 0x378, 0x3bc, 0x278, 0x00 };
	70
	71	static inline uint32_t get_parallel_iobase(PC87312State *s)
	72	{
08bb4a7c	73	return parallel_base[s->regs[REG_FAR] & FAR_PARALLEL_ADDR];
1ae41f44 HP	74	}
	75
	76	static const uint32_t parallel_irq[] = { 5, 7, 5, 0 };
	77
	78	static inline uint32_t get_parallel_irq(PC87312State *s)
	79	{
	80	int idx;
08bb4a7c	81	idx = (s->regs[REG_FAR] & FAR_PARALLEL_ADDR);
1ae41f44	82	if (idx == 0) {
08bb4a7c	83	return (s->regs[REG_PTR] & PTR_IRQ_5_7) ? 7 : 5;
1ae41f44 HP	84	} else {
	85	return parallel_irq[idx];
	86	}
	87	}
	88
	89	static inline bool is_parallel_epp(PC87312State *s)
	90	{
08bb4a7c	91	return s->regs[REG_PTR] & PTR_EPP_MODE;
1ae41f44 HP	92	}
	93
	94
	95	/* UARTs */
	96
	97	static const uint32_t uart_base[2][4] = {
	98	{ 0x3e8, 0x338, 0x2e8, 0x220 },
	99	{ 0x2e8, 0x238, 0x2e0, 0x228 }
	100	};
	101
	102	static inline uint32_t get_uart_iobase(PC87312State *s, int i)
	103	{
	104	int idx;
08bb4a7c	105	idx = (s->regs[REG_FAR] >> (2 * i + 2)) & 0x3;
1ae41f44 HP	106	if (idx == 0) {
	107	return 0x3f8;
	108	} else if (idx == 1) {
	109	return 0x2f8;
	110	} else {
08bb4a7c	111	return uart_base[idx & 1][(s->regs[REG_FAR] & FAR_UART_3_4) >> 6];
1ae41f44 HP	112	}
	113	}
	114
	115	static inline uint32_t get_uart_irq(PC87312State *s, int i)
	116	{
	117	int idx;
08bb4a7c	118	idx = (s->regs[REG_FAR] >> (2 * i + 2)) & 0x3;
1ae41f44 HP	119	return (idx & 1) ? 3 : 4;
	120	}
	121
	122	static inline bool is_uart_enabled(PC87312State *s, int i)
	123	{
08bb4a7c	124	return s->regs[REG_FER] & (FER_UART1_EN << i);
1ae41f44 HP	125	}
	126
	127
	128	/* Floppy controller */
	129
	130	static inline bool is_fdc_enabled(PC87312State *s)
	131	{
08bb4a7c	132	return s->regs[REG_FER] & FER_FDC_EN;
1ae41f44 HP	133	}
	134
	135	static inline uint32_t get_fdc_iobase(PC87312State *s)
	136	{
08bb4a7c	137	return (s->regs[REG_FER] & FER_FDC_ADDR) ? 0x370 : 0x3f0;
1ae41f44 HP	138	}
	139
	140
	141	/* IDE controller */
	142
	143	static inline bool is_ide_enabled(PC87312State *s)
	144	{
08bb4a7c	145	return s->regs[REG_FER] & FER_IDE_EN;
1ae41f44 HP	146	}
	147
	148	static inline uint32_t get_ide_iobase(PC87312State *s)
	149	{
08bb4a7c	150	return (s->regs[REG_FER] & FER_IDE_ADDR) ? 0x170 : 0x1f0;
1ae41f44 HP	151	}
	152
	153
	154	static void reconfigure_devices(PC87312State *s)
	155	{
	156	error_report("pc87312: unsupported device reconfiguration (%02x %02x %02x)",
08bb4a7c	157	s->regs[REG_FER], s->regs[REG_FAR], s->regs[REG_PTR]);
1ae41f44 HP	158	}
	159
	160	static void pc87312_soft_reset(PC87312State *s)
	161	{
	162	static const uint8_t fer_init[] = {
	163	0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4b, 0x4b,
	164	0x4b, 0x4b, 0x4b, 0x4b, 0x0f, 0x0f, 0x0f, 0x0f,
	165	0x49, 0x49, 0x49, 0x49, 0x07, 0x07, 0x07, 0x07,
	166	0x47, 0x47, 0x47, 0x47, 0x47, 0x47, 0x08, 0x00,
	167	};
	168	static const uint8_t far_init[] = {
	169	0x10, 0x11, 0x11, 0x39, 0x24, 0x38, 0x00, 0x01,
	170	0x01, 0x09, 0x08, 0x08, 0x10, 0x11, 0x39, 0x24,
	171	0x00, 0x01, 0x01, 0x00, 0x10, 0x11, 0x39, 0x24,
	172	0x10, 0x11, 0x11, 0x39, 0x24, 0x38, 0x10, 0x10,
	173	};
	174	static const uint8_t ptr_init[] = {
	175	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
	176	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
	177	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
	178	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02,
	179	};
	180
	181	s->read_id_step = 0;
	182	s->selected_index = REG_FER;
	183
08bb4a7c BS	184	s->regs[REG_FER] = fer_init[s->config & 0x1f];
	185	s->regs[REG_FAR] = far_init[s->config & 0x1f];
	186	s->regs[REG_PTR] = ptr_init[s->config & 0x1f];
1ae41f44 HP	187	}
	188
	189	static void pc87312_hard_reset(PC87312State *s)
	190	{
	191	pc87312_soft_reset(s);
	192	}
	193
328c24a9 AF	194	static void pc87312_io_write(void *opaque, hwaddr addr, uint64_t val,
328c24a9 AF	195	unsigned int size)
1ae41f44 HP	196	{
	197	PC87312State *s = opaque;
	198
	199	trace_pc87312_io_write(addr, val);
	200
	201	if ((addr & 1) == 0) {
	202	/* Index register */
	203	s->read_id_step = 2;
	204	s->selected_index = val;
	205	} else {
	206	/* Data register */
	207	if (s->selected_index < 3) {
	208	s->regs[s->selected_index] = val;
	209	reconfigure_devices(s);
	210	}
	211	}
	212	}
	213
328c24a9	214	static uint64_t pc87312_io_read(void *opaque, hwaddr addr, unsigned int size)
1ae41f44 HP	215	{
	216	PC87312State *s = opaque;
	217	uint32_t val;
	218
	219	if ((addr & 1) == 0) {
	220	/* Index register */
	221	if (s->read_id_step++ == 0) {
	222	val = 0x88;
	223	} else if (s->read_id_step++ == 1) {
	224	val = 0;
	225	} else {
	226	val = s->selected_index;
	227	}
	228	} else {
	229	/* Data register */
	230	if (s->selected_index < 3) {
	231	val = s->regs[s->selected_index];
	232	} else {
	233	/* Invalid selected index */
	234	val = 0;
	235	}
	236	}
	237
	238	trace_pc87312_io_read(addr, val);
	239	return val;
	240	}
	241
328c24a9 AF	242	static const MemoryRegionOps pc87312_io_ops = {
	243	.read = pc87312_io_read,
	244	.write = pc87312_io_write,
	245	.endianness = DEVICE_LITTLE_ENDIAN,
	246	.valid = {
	247	.min_access_size = 1,
	248	.max_access_size = 1,
	249	},
	250	};
	251
1ae41f44 HP	252	static int pc87312_post_load(void *opaque, int version_id)
	253	{
	254	PC87312State *s = opaque;
	255
	256	reconfigure_devices(s);
	257	return 0;
	258	}
	259
	260	static void pc87312_reset(DeviceState *d)
	261	{
	262	PC87312State *s = PC87312(d);
	263
	264	pc87312_soft_reset(s);
	265	}
	266
db895a1e	267	static void pc87312_realize(DeviceState dev, Error *errp)
1ae41f44 HP	268	{
	269	PC87312State *s;
	270	DeviceState *d;
	271	ISADevice *isa;
	272	ISABus *bus;
	273	CharDriverState *chr;
	274	DriveInfo *drive;
	275	char name[5];
	276	int i;
	277
	278	s = PC87312(dev);
db895a1e AF	279	isa = ISA_DEVICE(dev);
	280	bus = isa_bus_from_device(isa);
	281	isa_register_ioport(isa, &s->io, s->iobase);
1ae41f44 HP	282	pc87312_hard_reset(s);
	283
	284	if (is_parallel_enabled(s)) {
	285	chr = parallel_hds[0];
	286	if (chr == NULL) {
	287	chr = qemu_chr_new("par0", "null", NULL);
	288	}
	289	isa = isa_create(bus, "isa-parallel");
	290	d = DEVICE(isa);
	291	qdev_prop_set_uint32(d, "index", 0);
	292	qdev_prop_set_uint32(d, "iobase", get_parallel_iobase(s));
	293	qdev_prop_set_uint32(d, "irq", get_parallel_irq(s));
	294	qdev_prop_set_chr(d, "chardev", chr);
	295	qdev_init_nofail(d);
	296	s->parallel.dev = isa;
	297	trace_pc87312_info_parallel(get_parallel_iobase(s),
	298	get_parallel_irq(s));
	299	}
	300
	301	for (i = 0; i < 2; i++) {
	302	if (is_uart_enabled(s, i)) {
	303	chr = serial_hds[i];
	304	if (chr == NULL) {
	305	snprintf(name, sizeof(name), "ser%d", i);
	306	chr = qemu_chr_new(name, "null", NULL);
	307	}
	308	isa = isa_create(bus, "isa-serial");
	309	d = DEVICE(isa);
	310	qdev_prop_set_uint32(d, "index", i);
	311	qdev_prop_set_uint32(d, "iobase", get_uart_iobase(s, i));
	312	qdev_prop_set_uint32(d, "irq", get_uart_irq(s, i));
	313	qdev_prop_set_chr(d, "chardev", chr);
	314	qdev_init_nofail(d);
	315	s->uart[i].dev = isa;
	316	trace_pc87312_info_serial(i, get_uart_iobase(s, i),
	317	get_uart_irq(s, i));
	318	}
	319	}
	320
	321	if (is_fdc_enabled(s)) {
	322	isa = isa_create(bus, "isa-fdc");
	323	d = DEVICE(isa);
	324	qdev_prop_set_uint32(d, "iobase", get_fdc_iobase(s));
	325	qdev_prop_set_uint32(d, "irq", 6);
	326	drive = drive_get(IF_FLOPPY, 0, 0);
	327	if (drive != NULL) {
	328	qdev_prop_set_drive_nofail(d, "driveA", drive->bdrv);
	329	}
	330	drive = drive_get(IF_FLOPPY, 0, 1);
	331	if (drive != NULL) {
	332	qdev_prop_set_drive_nofail(d, "driveB", drive->bdrv);
	333	}
	334	qdev_init_nofail(d);
	335	s->fdc.dev = isa;
	336	trace_pc87312_info_floppy(get_fdc_iobase(s));
	337	}
	338
	339	if (is_ide_enabled(s)) {
	340	isa = isa_create(bus, "isa-ide");
	341	d = DEVICE(isa);
	342	qdev_prop_set_uint32(d, "iobase", get_ide_iobase(s));
	343	qdev_prop_set_uint32(d, "iobase2", get_ide_iobase(s) + 0x206);
	344	qdev_prop_set_uint32(d, "irq", 14);
	345	qdev_init_nofail(d);
346	s->ide.dev = isa;
347	trace_pc87312_info_ide(get_ide_iobase(s));
348	}
1ae41f44 HP	349	}
1ae41f44 HP	350
328c24a9 AF	351	static void pc87312_initfn(Object *obj)
	352	{
	353	PC87312State *s = PC87312(obj);
	354
1437c94b	355	memory_region_init_io(&s->io, obj, &pc87312_io_ops, s, "pc87312", 2);
328c24a9 AF	356	}
328c24a9 AF	357
1ae41f44 HP	358	static const VMStateDescription vmstate_pc87312 = {
	359	.name = "pc87312",
	360	.version_id = 1,
	361	.minimum_version_id = 1,
	362	.post_load = pc87312_post_load,
	363	.fields = (VMStateField[]) {
	364	VMSTATE_UINT8(read_id_step, PC87312State),
	365	VMSTATE_UINT8(selected_index, PC87312State),
	366	VMSTATE_UINT8_ARRAY(regs, PC87312State, 3),
	367	VMSTATE_END_OF_LIST()
	368	}
	369	};
	370
	371	static Property pc87312_properties[] = {
	372	DEFINE_PROP_HEX32("iobase", PC87312State, iobase, 0x398),
	373	DEFINE_PROP_UINT8("config", PC87312State, config, 1),
	374	DEFINE_PROP_END_OF_LIST()
	375	};
	376
	377	static void pc87312_class_init(ObjectClass klass, void data)
	378	{
	379	DeviceClass *dc = DEVICE_CLASS(klass);
1ae41f44	380
db895a1e	381	dc->realize = pc87312_realize;
1ae41f44 HP	382	dc->reset = pc87312_reset;
	383	dc->vmsd = &vmstate_pc87312;
	384	dc->props = pc87312_properties;
	385	}
	386
	387	static const TypeInfo pc87312_type_info = {
	388	.name = TYPE_PC87312,
	389	.parent = TYPE_ISA_DEVICE,
	390	.instance_size = sizeof(PC87312State),
328c24a9	391	.instance_init = pc87312_initfn,
1ae41f44 HP	392	.class_init = pc87312_class_init,
	393	};
	394
	395	static void pc87312_register_types(void)
	396	{
	397	type_register_static(&pc87312_type_info);
	398	}
	399
	400	type_init(pc87312_register_types)