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ssi: change ssi_slave_init to be a realize ops
[qemu.git] / hw / block / m25p80.c
CommitLineData
82a24990
PC		 1/*
2 * ST M25P80 emulator. Emulate all SPI flash devices based on the m25p80 command
3 * set. Known devices table current as of Jun/2012 and taken from linux.
4 * See drivers/mtd/devices/m25p80.c.
5 *
6 * Copyright (C) 2011 Edgar E. Iglesias <edgar.iglesias@gmail.com>
7 * Copyright (C) 2012 Peter A. G. Crosthwaite <peter.crosthwaite@petalogix.com>
8 * Copyright (C) 2012 PetaLogix
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 or
13 * (at your option) a later version of the License.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License along
21 * with this program; if not, see <http://www.gnu.org/licenses/>.
22 */
23
80c71a24 24#include "qemu/osdep.h"
83c9f4ca 25#include "hw/hw.h"
fa1d36df 26#include "sysemu/block-backend.h"
9c17d615 27#include "sysemu/blockdev.h"
8fd06719 28#include "hw/ssi/ssi.h"
cb475951 29#include "qemu/bitops.h"
03dd024f 30#include "qemu/log.h"
7673bb4c 31#include "qapi/error.h"
82a24990 32
28097d02
PC		 33#ifndef M25P80_ERR_DEBUG
34#define M25P80_ERR_DEBUG 0
82a24990
PC		 35#endif
36
28097d02
PC		 37#define DB_PRINT_L(level, ...) do { \
38 if (M25P80_ERR_DEBUG > (level)) { \
39 fprintf(stderr, ": %s: ", __func__); \
40 fprintf(stderr, ## __VA_ARGS__); \
41 } \
42} while (0);
43
82a24990
PC		 44/* Fields for FlashPartInfo->flags */
45
46/* erase capabilities */
47#define ER_4K 1
48#define ER_32K 2
49/* set to allow the page program command to write 0s back to 1. Useful for
50 * modelling EEPROM with SPI flash command set
51 */
1435bcd6 52#define EEPROM 0x100
82a24990 53
d8a29a7a
MK		 54/* 16 MiB max in 3 byte address mode */
55#define MAX_3BYTES_SIZE 0x1000000
56
e3ba6cd6
MK		 57#define SPI_NOR_MAX_ID_LEN 6
58
82a24990
PC		 59typedef struct FlashPartInfo {
60 const char *part_name;
e3ba6cd6
MK		 61 /*
62 * This array stores the ID bytes.
63 * The first three bytes are the JEDIC ID.
64 * JEDEC ID zero means "no ID" (mostly older chips).
65 */
66 uint8_t id[SPI_NOR_MAX_ID_LEN];
67 uint8_t id_len;
82a24990
PC		 68 /* there is confusion between manufacturers as to what a sector is. In this
69 * device model, a "sector" is the size that is erased by the ERASE_SECTOR
70 * command (opcode 0xd8).
71 */
72 uint32_t sector_size;
73 uint32_t n_sectors;
74 uint32_t page_size;
76e87269 75 uint16_t flags;
82a24990
PC		 76} FlashPartInfo;
77
78/* adapted from linux */
e3ba6cd6
MK		 79/* Used when the "_ext_id" is two bytes at most */
80#define INFO(_part_name, _jedec_id, _ext_id, _sector_size, _n_sectors, _flags)\
81 .part_name = _part_name,\
82 .id = {\
83 ((_jedec_id) >> 16) & 0xff,\
84 ((_jedec_id) >> 8) & 0xff,\
85 (_jedec_id) & 0xff,\
86 ((_ext_id) >> 8) & 0xff,\
87 (_ext_id) & 0xff,\
88 },\
89 .id_len = (!(_jedec_id) ? 0 : (3 + ((_ext_id) ? 2 : 0))),\
90 .sector_size = (_sector_size),\
91 .n_sectors = (_n_sectors),\
92 .page_size = 256,\
93 .flags = (_flags),
94
95#define INFO6(_part_name, _jedec_id, _ext_id, _sector_size, _n_sectors, _flags)\
96 .part_name = _part_name,\
97 .id = {\
98 ((_jedec_id) >> 16) & 0xff,\
99 ((_jedec_id) >> 8) & 0xff,\
100 (_jedec_id) & 0xff,\
101 ((_ext_id) >> 16) & 0xff,\
102 ((_ext_id) >> 8) & 0xff,\
103 (_ext_id) & 0xff,\
104 },\
105 .id_len = 6,\
82a24990
PC		 106 .sector_size = (_sector_size),\
107 .n_sectors = (_n_sectors),\
108 .page_size = 256,\
109 .flags = (_flags),\
110
419336a9
PC		 111#define JEDEC_NUMONYX 0x20
112#define JEDEC_WINBOND 0xEF
113#define JEDEC_SPANSION 0x01
114
cb475951
MK		 115/* Numonyx (Micron) Configuration register macros */
116#define VCFG_DUMMY 0x1
117#define VCFG_WRAP_SEQUENTIAL 0x2
118#define NVCFG_XIP_MODE_DISABLED (7 << 9)
119#define NVCFG_XIP_MODE_MASK (7 << 9)
120#define VCFG_XIP_MODE_ENABLED (1 << 3)
121#define CFG_DUMMY_CLK_LEN 4
122#define NVCFG_DUMMY_CLK_POS 12
123#define VCFG_DUMMY_CLK_POS 4
124#define EVCFG_OUT_DRIVER_STRENGHT_DEF 7
125#define EVCFG_VPP_ACCELERATOR (1 << 3)
126#define EVCFG_RESET_HOLD_ENABLED (1 << 4)
127#define NVCFG_DUAL_IO_MASK (1 << 2)
128#define EVCFG_DUAL_IO_ENABLED (1 << 6)
129#define NVCFG_QUAD_IO_MASK (1 << 3)
130#define EVCFG_QUAD_IO_ENABLED (1 << 7)
131#define NVCFG_4BYTE_ADDR_MASK (1 << 0)
132#define NVCFG_LOWER_SEGMENT_MASK (1 << 1)
cb475951 133
9fbaa364
MK		 134/* Numonyx (Micron) Flag Status Register macros */
135#define FSR_4BYTE_ADDR_MODE_ENABLED 0x1
136#define FSR_FLASH_READY (1 << 7)
137
d9cc8701
MK		 138/* Spansion configuration registers macros. */
139#define SPANSION_QUAD_CFG_POS 0
140#define SPANSION_QUAD_CFG_LEN 1
141#define SPANSION_DUMMY_CLK_POS 0
142#define SPANSION_DUMMY_CLK_LEN 4
143#define SPANSION_ADDR_LEN_POS 7
144#define SPANSION_ADDR_LEN_LEN 1
145
cf6f1efe
MK		 146/*
147 * Spansion read mode command length in bytes,
148 * the mode is currently not supported.
149*/
150
151#define SPANSION_CONTINUOUS_READ_MODE_CMD_LEN 1
152
82a24990
PC		 153static const FlashPartInfo known_devices[] = {
154 /* Atmel -- some are (confusingly) marketed as "DataFlash" */
155 { INFO("at25fs010", 0x1f6601, 0, 32 << 10, 4, ER_4K) },
156 { INFO("at25fs040", 0x1f6604, 0, 64 << 10, 8, ER_4K) },
157
158 { INFO("at25df041a", 0x1f4401, 0, 64 << 10, 8, ER_4K) },
159 { INFO("at25df321a", 0x1f4701, 0, 64 << 10, 64, ER_4K) },
160 { INFO("at25df641", 0x1f4800, 0, 64 << 10, 128, ER_4K) },
161
162 { INFO("at26f004", 0x1f0400, 0, 64 << 10, 8, ER_4K) },
163 { INFO("at26df081a", 0x1f4501, 0, 64 << 10, 16, ER_4K) },
164 { INFO("at26df161a", 0x1f4601, 0, 64 << 10, 32, ER_4K) },
165 { INFO("at26df321", 0x1f4700, 0, 64 << 10, 64, ER_4K) },
166
3e758c1d
EM		 167 { INFO("at45db081d", 0x1f2500, 0, 64 << 10, 16, ER_4K) },
168
1435bcd6
MK		 169 /* Atmel EEPROMS - it is assumed, that don't care bit in command
170 * is set to 0. Block protection is not supported.
171 */
172 { INFO("at25128a-nonjedec", 0x0, 0, 1, 131072, EEPROM) },
173 { INFO("at25256a-nonjedec", 0x0, 0, 1, 262144, EEPROM) },
174
82a24990
PC		 175 /* EON -- en25xxx */
176 { INFO("en25f32", 0x1c3116, 0, 64 << 10, 64, ER_4K) },
177 { INFO("en25p32", 0x1c2016, 0, 64 << 10, 64, 0) },
178 { INFO("en25q32b", 0x1c3016, 0, 64 << 10, 64, 0) },
179 { INFO("en25p64", 0x1c2017, 0, 64 << 10, 128, 0) },
3e758c1d
EM		 180 { INFO("en25q64", 0x1c3017, 0, 64 << 10, 128, ER_4K) },
181
182 /* GigaDevice */
183 { INFO("gd25q32", 0xc84016, 0, 64 << 10, 64, ER_4K) },
184 { INFO("gd25q64", 0xc84017, 0, 64 << 10, 128, ER_4K) },
82a24990
PC		 185
186 /* Intel/Numonyx -- xxxs33b */
187 { INFO("160s33b", 0x898911, 0, 64 << 10, 32, 0) },
188 { INFO("320s33b", 0x898912, 0, 64 << 10, 64, 0) },
189 { INFO("640s33b", 0x898913, 0, 64 << 10, 128, 0) },
3e758c1d 190 { INFO("n25q064", 0x20ba17, 0, 64 << 10, 128, 0) },
82a24990
PC		 191
192 /* Macronix */
3e758c1d 193 { INFO("mx25l2005a", 0xc22012, 0, 64 << 10, 4, ER_4K) },
82a24990
PC		 194 { INFO("mx25l4005a", 0xc22013, 0, 64 << 10, 8, ER_4K) },
195 { INFO("mx25l8005", 0xc22014, 0, 64 << 10, 16, 0) },
196 { INFO("mx25l1606e", 0xc22015, 0, 64 << 10, 32, ER_4K) },
197 { INFO("mx25l3205d", 0xc22016, 0, 64 << 10, 64, 0) },
198 { INFO("mx25l6405d", 0xc22017, 0, 64 << 10, 128, 0) },
199 { INFO("mx25l12805d", 0xc22018, 0, 64 << 10, 256, 0) },
200 { INFO("mx25l12855e", 0xc22618, 0, 64 << 10, 256, 0) },
201 { INFO("mx25l25635e", 0xc22019, 0, 64 << 10, 512, 0) },
202 { INFO("mx25l25655e", 0xc22619, 0, 64 << 10, 512, 0) },
dadb2f90
MK		 203 { INFO("mx66u51235f", 0xc2253a, 0, 64 << 10, 1024, ER_4K | ER_32K) },
204 { INFO("mx66u1g45g", 0xc2253b, 0, 64 << 10, 2048, ER_4K | ER_32K) },
82a24990 205
3e758c1d 206 /* Micron */
f5aac8e0
EM		 207 { INFO("n25q032a11", 0x20bb16, 0, 64 << 10, 64, ER_4K) },
208 { INFO("n25q032a13", 0x20ba16, 0, 64 << 10, 64, ER_4K) },
209 { INFO("n25q064a11", 0x20bb17, 0, 64 << 10, 128, ER_4K) },
210 { INFO("n25q064a13", 0x20ba17, 0, 64 << 10, 128, ER_4K) },
211 { INFO("n25q128a11", 0x20bb18, 0, 64 << 10, 256, ER_4K) },
212 { INFO("n25q128a13", 0x20ba18, 0, 64 << 10, 256, ER_4K) },
213 { INFO("n25q256a11", 0x20bb19, 0, 64 << 10, 512, ER_4K) },
214 { INFO("n25q256a13", 0x20ba19, 0, 64 << 10, 512, ER_4K) },
dadb2f90
MK		 215 { INFO("n25q128", 0x20ba18, 0, 64 << 10, 256, 0) },
216 { INFO("n25q256a", 0x20ba19, 0, 64 << 10, 512, ER_4K) },
217 { INFO("n25q512a", 0x20ba20, 0, 64 << 10, 1024, ER_4K) },
218 { INFO("mt25ql01g", 0x20ba21, 0, 64 << 10, 2048, ER_4K) },
219 { INFO("mt25qu01g", 0x20bb21, 0, 64 << 10, 2048, ER_4K) },
3e758c1d 220
82a24990
PC		 221 /* Spansion -- single (large) sector size only, at least
222 * for the chips listed here (without boot sectors).
223 */
82a24990 224 { INFO("s25sl032p", 0x010215, 0x4d00, 64 << 10, 64, ER_4K) },
3e758c1d 225 { INFO("s25sl064p", 0x010216, 0x4d00, 64 << 10, 128, ER_4K) },
82a24990
PC		 226 { INFO("s25fl256s0", 0x010219, 0x4d00, 256 << 10, 128, 0) },
227 { INFO("s25fl256s1", 0x010219, 0x4d01, 64 << 10, 512, 0) },
dadb2f90
MK		 228 { INFO6("s25fl512s", 0x010220, 0x4d0080, 256 << 10, 256, 0) },
229 { INFO6("s70fl01gs", 0x010221, 0x4d0080, 256 << 10, 512, 0) },
82a24990
PC		 230 { INFO("s25sl12800", 0x012018, 0x0300, 256 << 10, 64, 0) },
231 { INFO("s25sl12801", 0x012018, 0x0301, 64 << 10, 256, 0) },
232 { INFO("s25fl129p0", 0x012018, 0x4d00, 256 << 10, 64, 0) },
233 { INFO("s25fl129p1", 0x012018, 0x4d01, 64 << 10, 256, 0) },
3e758c1d
EM		 234 { INFO("s25sl004a", 0x010212, 0, 64 << 10, 8, 0) },
235 { INFO("s25sl008a", 0x010213, 0, 64 << 10, 16, 0) },
236 { INFO("s25sl016a", 0x010214, 0, 64 << 10, 32, 0) },
237 { INFO("s25sl032a", 0x010215, 0, 64 << 10, 64, 0) },
238 { INFO("s25sl064a", 0x010216, 0, 64 << 10, 128, 0) },
82a24990
PC		 239 { INFO("s25fl016k", 0xef4015, 0, 64 << 10, 32, ER_4K | ER_32K) },
240 { INFO("s25fl064k", 0xef4017, 0, 64 << 10, 128, ER_4K | ER_32K) },
241
dadb2f90
MK		 242 /* Spansion -- boot sectors support */
243 { INFO6("s25fs512s", 0x010220, 0x4d0081, 256 << 10, 256, 0) },
244 { INFO6("s70fs01gs", 0x010221, 0x4d0081, 256 << 10, 512, 0) },
245
82a24990
PC		 246 /* SST -- large erase sizes are "overlays", "sectors" are 4<< 10 */
247 { INFO("sst25vf040b", 0xbf258d, 0, 64 << 10, 8, ER_4K) },
248 { INFO("sst25vf080b", 0xbf258e, 0, 64 << 10, 16, ER_4K) },
249 { INFO("sst25vf016b", 0xbf2541, 0, 64 << 10, 32, ER_4K) },
250 { INFO("sst25vf032b", 0xbf254a, 0, 64 << 10, 64, ER_4K) },
251 { INFO("sst25wf512", 0xbf2501, 0, 64 << 10, 1, ER_4K) },
252 { INFO("sst25wf010", 0xbf2502, 0, 64 << 10, 2, ER_4K) },
253 { INFO("sst25wf020", 0xbf2503, 0, 64 << 10, 4, ER_4K) },
254 { INFO("sst25wf040", 0xbf2504, 0, 64 << 10, 8, ER_4K) },
d857c4c0 255 { INFO("sst25wf080", 0xbf2505, 0, 64 << 10, 16, ER_4K) },
82a24990
PC		 256
257 /* ST Microelectronics -- newer production may have feature updates */
258 { INFO("m25p05", 0x202010, 0, 32 << 10, 2, 0) },
259 { INFO("m25p10", 0x202011, 0, 32 << 10, 4, 0) },
260 { INFO("m25p20", 0x202012, 0, 64 << 10, 4, 0) },
261 { INFO("m25p40", 0x202013, 0, 64 << 10, 8, 0) },
262 { INFO("m25p80", 0x202014, 0, 64 << 10, 16, 0) },
263 { INFO("m25p16", 0x202015, 0, 64 << 10, 32, 0) },
264 { INFO("m25p32", 0x202016, 0, 64 << 10, 64, 0) },
265 { INFO("m25p64", 0x202017, 0, 64 << 10, 128, 0) },
266 { INFO("m25p128", 0x202018, 0, 256 << 10, 64, 0) },
3e758c1d 267 { INFO("n25q032", 0x20ba16, 0, 64 << 10, 64, 0) },
82a24990
PC		 268
269 { INFO("m45pe10", 0x204011, 0, 64 << 10, 2, 0) },
270 { INFO("m45pe80", 0x204014, 0, 64 << 10, 16, 0) },
271 { INFO("m45pe16", 0x204015, 0, 64 << 10, 32, 0) },
272
3e758c1d 273 { INFO("m25pe20", 0x208012, 0, 64 << 10, 4, 0) },
82a24990
PC		 274 { INFO("m25pe80", 0x208014, 0, 64 << 10, 16, 0) },
275 { INFO("m25pe16", 0x208015, 0, 64 << 10, 32, ER_4K) },
276
277 { INFO("m25px32", 0x207116, 0, 64 << 10, 64, ER_4K) },
278 { INFO("m25px32-s0", 0x207316, 0, 64 << 10, 64, ER_4K) },
279 { INFO("m25px32-s1", 0x206316, 0, 64 << 10, 64, ER_4K) },
280 { INFO("m25px64", 0x207117, 0, 64 << 10, 128, 0) },
281
282 /* Winbond -- w25x "blocks" are 64k, "sectors" are 4KiB */
283 { INFO("w25x10", 0xef3011, 0, 64 << 10, 2, ER_4K) },
284 { INFO("w25x20", 0xef3012, 0, 64 << 10, 4, ER_4K) },
285 { INFO("w25x40", 0xef3013, 0, 64 << 10, 8, ER_4K) },
286 { INFO("w25x80", 0xef3014, 0, 64 << 10, 16, ER_4K) },
287 { INFO("w25x16", 0xef3015, 0, 64 << 10, 32, ER_4K) },
288 { INFO("w25x32", 0xef3016, 0, 64 << 10, 64, ER_4K) },
289 { INFO("w25q32", 0xef4016, 0, 64 << 10, 64, ER_4K) },
3e758c1d 290 { INFO("w25q32dw", 0xef6016, 0, 64 << 10, 64, ER_4K) },
82a24990
PC		 291 { INFO("w25x64", 0xef3017, 0, 64 << 10, 128, ER_4K) },
292 { INFO("w25q64", 0xef4017, 0, 64 << 10, 128, ER_4K) },
3e758c1d
EM		 293 { INFO("w25q80", 0xef5014, 0, 64 << 10, 16, ER_4K) },
294 { INFO("w25q80bl", 0xef4014, 0, 64 << 10, 16, ER_4K) },
295 { INFO("w25q256", 0xef4019, 0, 64 << 10, 512, ER_4K) },
82a24990
PC		 296};
297
298typedef enum {
299 NOP = 0,
03ec2f83 300 WRSR = 0x1,
82a24990
PC		 301 WRDI = 0x4,
302 RDSR = 0x5,
303 WREN = 0x6,
419336a9
PC		 304 JEDEC_READ = 0x9f,
305 BULK_ERASE = 0xc7,
9fbaa364 306 READ_FSR = 0x70,
7a69c100 307 RDCR = 0x15,
419336a9 308
63e47f6f
MK		 309 READ = 0x03,
310 READ4 = 0x13,
311 FAST_READ = 0x0b,
312 FAST_READ4 = 0x0c,
419336a9 313 DOR = 0x3b,
63e47f6f 314 DOR4 = 0x3c,
419336a9 315 QOR = 0x6b,
63e47f6f 316 QOR4 = 0x6c,
419336a9 317 DIOR = 0xbb,
63e47f6f 318 DIOR4 = 0xbc,
419336a9 319 QIOR = 0xeb,
63e47f6f 320 QIOR4 = 0xec,
419336a9 321
63e47f6f
MK		 322 PP = 0x02,
323 PP4 = 0x12,
30467afe 324 PP4_4 = 0x3e,
419336a9
PC		 325 DPP = 0xa2,
326 QPP = 0x32,
327
82a24990 328 ERASE_4K = 0x20,
63e47f6f 329 ERASE4_4K = 0x21,
82a24990 330 ERASE_32K = 0x52,
30467afe 331 ERASE4_32K = 0x5c,
82a24990 332 ERASE_SECTOR = 0xd8,
63e47f6f 333 ERASE4_SECTOR = 0xdc,
187c2636 334
c0f3f675
MK		 335 EN_4BYTE_ADDR = 0xB7,
336 EX_4BYTE_ADDR = 0xE9,
337
d8a29a7a
MK		 338 EXTEND_ADDR_READ = 0xC8,
339 EXTEND_ADDR_WRITE = 0xC5,
340
187c2636
MK		 341 RESET_ENABLE = 0x66,
342 RESET_MEMORY = 0x99,
cb475951 343
7a69c100
MK		 344 /*
345 * Micron: 0x35 - enable QPI
346 * Spansion: 0x35 - read control register
347 */
348 RDCR_EQIO = 0x35,
349 RSTQIO = 0xf5,
350
cb475951
MK		 351 RNVCR = 0xB5,
352 WNVCR = 0xB1,
353
354 RVCR = 0x85,
355 WVCR = 0x81,
356
357 REVCR = 0x65,
358 WEVCR = 0x61,
82a24990
PC		 359} FlashCMD;
360
361typedef enum {
362 STATE_IDLE,
363 STATE_PAGE_PROGRAM,
364 STATE_READ,
365 STATE_COLLECTING_DATA,
9964674e 366 STATE_COLLECTING_VAR_LEN_DATA,
82a24990
PC		 367 STATE_READING_DATA,
368} CMDState;
369
c7cd0a6c
MK		 370typedef enum {
371 MAN_SPANSION,
372 MAN_MACRONIX,
373 MAN_NUMONYX,
374 MAN_WINBOND,
375 MAN_GENERIC,
376} Manufacturer;
377
82a24990 378typedef struct Flash {
cdccf7d7
PC		 379 SSISlave parent_obj;
380
4be74634 381 BlockBackend *blk;
82a24990
PC		 382
383 uint8_t *storage;
384 uint32_t size;
385 int page_size;
386
387 uint8_t state;
388 uint8_t data[16];
389 uint32_t len;
390 uint32_t pos;
391 uint8_t needed_bytes;
392 uint8_t cmd_in_progress;
393 uint64_t cur_addr;
cb475951 394 uint32_t nonvolatile_cfg;
d9cc8701 395 /* Configuration register for Macronix */
cb475951
MK		 396 uint32_t volatile_cfg;
397 uint32_t enh_volatile_cfg;
d9cc8701
MK		 398 /* Spansion cfg registers. */
399 uint8_t spansion_cr1nv;
400 uint8_t spansion_cr2nv;
401 uint8_t spansion_cr3nv;
402 uint8_t spansion_cr4nv;
403 uint8_t spansion_cr1v;
404 uint8_t spansion_cr2v;
405 uint8_t spansion_cr3v;
406 uint8_t spansion_cr4v;
82a24990 407 bool write_enable;
c0f3f675 408 bool four_bytes_address_mode;
187c2636 409 bool reset_enable;
7a69c100 410 bool quad_enable;
d8a29a7a 411 uint8_t ear;
82a24990
PC		 412
413 int64_t dirty_page;
414
82a24990
PC		 415 const FlashPartInfo *pi;
416
417} Flash;
418
a7fd6915
PC		 419typedef struct M25P80Class {
420 SSISlaveClass parent_class;
421 FlashPartInfo *pi;
422} M25P80Class;
423
424#define TYPE_M25P80 "m25p80-generic"
425#define M25P80(obj) \
426 OBJECT_CHECK(Flash, (obj), TYPE_M25P80)
427#define M25P80_CLASS(klass) \
428 OBJECT_CLASS_CHECK(M25P80Class, (klass), TYPE_M25P80)
429#define M25P80_GET_CLASS(obj) \
430 OBJECT_GET_CLASS(M25P80Class, (obj), TYPE_M25P80)
431
c7cd0a6c
MK		 432static inline Manufacturer get_man(Flash *s)
433{
e3ba6cd6 434 switch (s->pi->id[0]) {
c7cd0a6c
MK		 435 case 0x20:
436 return MAN_NUMONYX;
437 case 0xEF:
438 return MAN_WINBOND;
439 case 0x01:
440 return MAN_SPANSION;
441 case 0xC2:
442 return MAN_MACRONIX;
443 default:
444 return MAN_GENERIC;
445 }
446}
447
4be74634 448static void blk_sync_complete(void *opaque, int ret)
82a24990
PC		 449{
450 /* do nothing. Masters do not directly interact with the backing store,
451 * only the working copy so no mutexing required.
452 */
453}
454
455static void flash_sync_page(Flash *s, int page)
456{
fc1084aa
PC		 457 QEMUIOVector iov;
458
4be74634 459 if (!s->blk || blk_is_read_only(s->blk)) {
fc1084aa 460 return;
82a24990 461 }
fc1084aa 462
fc1084aa 463 qemu_iovec_init(&iov, 1);
243e6f69
EB		 464 qemu_iovec_add(&iov, s->storage + page * s->pi->page_size,
465 s->pi->page_size);
466 blk_aio_pwritev(s->blk, page * s->pi->page_size, &iov, 0,
467 blk_sync_complete, NULL);
82a24990
PC		 468}
469
470static inline void flash_sync_area(Flash *s, int64_t off, int64_t len)
471{
82a24990
PC		 472 QEMUIOVector iov;
473
4be74634 474 if (!s->blk || blk_is_read_only(s->blk)) {
82a24990
PC		 475 return;
476 }
477
478 assert(!(len % BDRV_SECTOR_SIZE));
82a24990 479 qemu_iovec_init(&iov, 1);
243e6f69
EB		 480 qemu_iovec_add(&iov, s->storage + off, len);
481 blk_aio_pwritev(s->blk, off, &iov, 0, blk_sync_complete, NULL);
82a24990
PC		 482}
483
484static void flash_erase(Flash *s, int offset, FlashCMD cmd)
485{
486 uint32_t len;
487 uint8_t capa_to_assert = 0;
488
489 switch (cmd) {
490 case ERASE_4K:
63e47f6f 491 case ERASE4_4K:
82a24990
PC		 492 len = 4 << 10;
493 capa_to_assert = ER_4K;
494 break;
495 case ERASE_32K:
30467afe 496 case ERASE4_32K:
82a24990
PC		 497 len = 32 << 10;
498 capa_to_assert = ER_32K;
499 break;
500 case ERASE_SECTOR:
63e47f6f 501 case ERASE4_SECTOR:
82a24990
PC		 502 len = s->pi->sector_size;
503 break;
504 case BULK_ERASE:
505 len = s->size;
506 break;
507 default:
508 abort();
509 }
510
28097d02 511 DB_PRINT_L(0, "offset = %#x, len = %d\n", offset, len);
82a24990 512 if ((s->pi->flags & capa_to_assert) != capa_to_assert) {
e9711b4d
PC		 513 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: %d erase size not supported by"
514 " device\n", len);
82a24990
PC		 515 }
516
517 if (!s->write_enable) {
e9711b4d 518 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: erase with write protect!\n");
82a24990
PC		 519 return;
520 }
521 memset(s->storage + offset, 0xff, len);
522 flash_sync_area(s, offset, len);
523}
524
525static inline void flash_sync_dirty(Flash *s, int64_t newpage)
526{
527 if (s->dirty_page >= 0 && s->dirty_page != newpage) {
528 flash_sync_page(s, s->dirty_page);
529 s->dirty_page = newpage;
530 }
531}
532
533static inline
534void flash_write8(Flash *s, uint64_t addr, uint8_t data)
535{
536 int64_t page = addr / s->pi->page_size;
537 uint8_t prev = s->storage[s->cur_addr];
538
539 if (!s->write_enable) {
e9711b4d 540 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: write with write protect!\n");
82a24990
PC		 541 }
542
543 if ((prev ^ data) & data) {
28097d02
PC		 544 DB_PRINT_L(1, "programming zero to one! addr=%" PRIx64 " %" PRIx8
545 " -> %" PRIx8 "\n", addr, prev, data);
82a24990
PC		 546 }
547
1435bcd6 548 if (s->pi->flags & EEPROM) {
82a24990
PC		 549 s->storage[s->cur_addr] = data;
550 } else {
551 s->storage[s->cur_addr] &= data;
552 }
553
554 flash_sync_dirty(s, page);
555 s->dirty_page = page;
556}
557
c0f3f675
MK		 558static inline int get_addr_length(Flash *s)
559{
1435bcd6
MK		 560 /* check if eeprom is in use */
561 if (s->pi->flags == EEPROM) {
562 return 2;
563 }
564
63e47f6f
MK		 565 switch (s->cmd_in_progress) {
566 case PP4:
30467afe 567 case PP4_4:
63e47f6f
MK		 568 case READ4:
569 case QIOR4:
570 case ERASE4_4K:
30467afe 571 case ERASE4_32K:
63e47f6f
MK		 572 case ERASE4_SECTOR:
573 case FAST_READ4:
574 case DOR4:
575 case QOR4:
576 case DIOR4:
577 return 4;
578 default:
579 return s->four_bytes_address_mode ? 4 : 3;
580 }
c0f3f675
MK		 581}
582
82a24990
PC		 583static void complete_collecting_data(Flash *s)
584{
c0f3f675
MK		 585 int i;
586
587 s->cur_addr = 0;
588
589 for (i = 0; i < get_addr_length(s); ++i) {
590 s->cur_addr <<= 8;
591 s->cur_addr |= s->data[i];
592 }
593
594 if (get_addr_length(s) == 3) {
e02b3bf2 595 s->cur_addr += s->ear * MAX_3BYTES_SIZE;
c0f3f675 596 }
82a24990 597
a56d305a
PC		 598 s->state = STATE_IDLE;
599
82a24990 600 switch (s->cmd_in_progress) {
419336a9
PC		 601 case DPP:
602 case QPP:
82a24990 603 case PP:
63e47f6f 604 case PP4:
30467afe 605 case PP4_4:
82a24990
PC		 606 s->state = STATE_PAGE_PROGRAM;
607 break;
608 case READ:
63e47f6f 609 case READ4:
82a24990 610 case FAST_READ:
63e47f6f 611 case FAST_READ4:
419336a9 612 case DOR:
63e47f6f 613 case DOR4:
419336a9 614 case QOR:
63e47f6f 615 case QOR4:
419336a9 616 case DIOR:
63e47f6f 617 case DIOR4:
419336a9 618 case QIOR:
63e47f6f 619 case QIOR4:
82a24990
PC		 620 s->state = STATE_READ;
621 break;
622 case ERASE_4K:
63e47f6f 623 case ERASE4_4K:
82a24990 624 case ERASE_32K:
30467afe 625 case ERASE4_32K:
82a24990 626 case ERASE_SECTOR:
63e47f6f 627 case ERASE4_SECTOR:
82a24990
PC		 628 flash_erase(s, s->cur_addr, s->cmd_in_progress);
629 break;
03ec2f83 630 case WRSR:
7a69c100
MK		 631 switch (get_man(s)) {
632 case MAN_SPANSION:
633 s->quad_enable = !!(s->data[1] & 0x02);
634 break;
635 case MAN_MACRONIX:
636 s->quad_enable = extract32(s->data[0], 6, 1);
d9cc8701
MK		 637 if (s->len > 1) {
638 s->four_bytes_address_mode = extract32(s->data[1], 5, 1);
639 }
7a69c100
MK		 640 break;
641 default:
642 break;
643 }
03ec2f83
KJS		 644 if (s->write_enable) {
645 s->write_enable = false;
646 }
647 break;
d8a29a7a
MK		 648 case EXTEND_ADDR_WRITE:
649 s->ear = s->data[0];
650 break;
cb475951
MK		 651 case WNVCR:
652 s->nonvolatile_cfg = s->data[0] | (s->data[1] << 8);
653 break;
654 case WVCR:
655 s->volatile_cfg = s->data[0];
656 break;
657 case WEVCR:
658 s->enh_volatile_cfg = s->data[0];
659 break;
82a24990
PC		 660 default:
661 break;
662 }
663}
664
187c2636
MK		 665static void reset_memory(Flash *s)
666{
667 s->cmd_in_progress = NOP;
668 s->cur_addr = 0;
d8a29a7a 669 s->ear = 0;
c0f3f675 670 s->four_bytes_address_mode = false;
187c2636
MK		 671 s->len = 0;
672 s->needed_bytes = 0;
673 s->pos = 0;
674 s->state = STATE_IDLE;
675 s->write_enable = false;
676 s->reset_enable = false;
7a69c100 677 s->quad_enable = false;
187c2636 678
c7cd0a6c
MK		 679 switch (get_man(s)) {
680 case MAN_NUMONYX:
cb475951
MK		 681 s->volatile_cfg = 0;
682 s->volatile_cfg |= VCFG_DUMMY;
683 s->volatile_cfg |= VCFG_WRAP_SEQUENTIAL;
684 if ((s->nonvolatile_cfg & NVCFG_XIP_MODE_MASK)
685 != NVCFG_XIP_MODE_DISABLED) {
686 s->volatile_cfg |= VCFG_XIP_MODE_ENABLED;
687 }
688 s->volatile_cfg |= deposit32(s->volatile_cfg,
689 VCFG_DUMMY_CLK_POS,
690 CFG_DUMMY_CLK_LEN,
691 extract32(s->nonvolatile_cfg,
692 NVCFG_DUMMY_CLK_POS,
693 CFG_DUMMY_CLK_LEN)
694 );
695
696 s->enh_volatile_cfg = 0;
697 s->enh_volatile_cfg |= EVCFG_OUT_DRIVER_STRENGHT_DEF;
698 s->enh_volatile_cfg |= EVCFG_VPP_ACCELERATOR;
699 s->enh_volatile_cfg |= EVCFG_RESET_HOLD_ENABLED;
700 if (s->nonvolatile_cfg & NVCFG_DUAL_IO_MASK) {
701 s->enh_volatile_cfg |= EVCFG_DUAL_IO_ENABLED;
702 }
703 if (s->nonvolatile_cfg & NVCFG_QUAD_IO_MASK) {
704 s->enh_volatile_cfg |= EVCFG_QUAD_IO_ENABLED;
705 }
706 if (!(s->nonvolatile_cfg & NVCFG_4BYTE_ADDR_MASK)) {
707 s->four_bytes_address_mode = true;
708 }
709 if (!(s->nonvolatile_cfg & NVCFG_LOWER_SEGMENT_MASK)) {
e02b3bf2 710 s->ear = s->size / MAX_3BYTES_SIZE - 1;
cb475951 711 }
c7cd0a6c 712 break;
d9cc8701
MK		 713 case MAN_MACRONIX:
714 s->volatile_cfg = 0x7;
715 break;
716 case MAN_SPANSION:
717 s->spansion_cr1v = s->spansion_cr1nv;
718 s->spansion_cr2v = s->spansion_cr2nv;
719 s->spansion_cr3v = s->spansion_cr3nv;
720 s->spansion_cr4v = s->spansion_cr4nv;
721 s->quad_enable = extract32(s->spansion_cr1v,
722 SPANSION_QUAD_CFG_POS,
723 SPANSION_QUAD_CFG_LEN
724 );
725 s->four_bytes_address_mode = extract32(s->spansion_cr2v,
726 SPANSION_ADDR_LEN_POS,
727 SPANSION_ADDR_LEN_LEN
728 );
729 break;
c7cd0a6c
MK		 730 default:
731 break;
cb475951
MK		 732 }
733
187c2636
MK		 734 DB_PRINT_L(0, "Reset done.\n");
735}
736
cf6f1efe
MK		 737static void decode_fast_read_cmd(Flash *s)
738{
739 s->needed_bytes = get_addr_length(s);
740 switch (get_man(s)) {
741 /* Dummy cycles - modeled with bytes writes instead of bits */
3830c7a4
MK		 742 case MAN_WINBOND:
743 s->needed_bytes += 8;
744 break;
cf6f1efe
MK		 745 case MAN_NUMONYX:
746 s->needed_bytes += extract32(s->volatile_cfg, 4, 4);
747 break;
748 case MAN_MACRONIX:
749 if (extract32(s->volatile_cfg, 6, 2) == 1) {
750 s->needed_bytes += 6;
751 } else {
752 s->needed_bytes += 8;
753 }
754 break;
755 case MAN_SPANSION:
756 s->needed_bytes += extract32(s->spansion_cr2v,
757 SPANSION_DUMMY_CLK_POS,
758 SPANSION_DUMMY_CLK_LEN
759 );
760 break;
761 default:
762 break;
763 }
764 s->pos = 0;
765 s->len = 0;
766 s->state = STATE_COLLECTING_DATA;
767}
768
769static void decode_dio_read_cmd(Flash *s)
770{
771 s->needed_bytes = get_addr_length(s);
772 /* Dummy cycles modeled with bytes writes instead of bits */
773 switch (get_man(s)) {
774 case MAN_WINBOND:
3830c7a4 775 s->needed_bytes += 8;
cf6f1efe
MK		 776 break;
777 case MAN_SPANSION:
778 s->needed_bytes += SPANSION_CONTINUOUS_READ_MODE_CMD_LEN;
779 s->needed_bytes += extract32(s->spansion_cr2v,
780 SPANSION_DUMMY_CLK_POS,
781 SPANSION_DUMMY_CLK_LEN
782 );
783 break;
784 case MAN_NUMONYX:
785 s->needed_bytes += extract32(s->volatile_cfg, 4, 4);
786 break;
787 case MAN_MACRONIX:
788 switch (extract32(s->volatile_cfg, 6, 2)) {
789 case 1:
790 s->needed_bytes += 6;
791 break;
792 case 2:
793 s->needed_bytes += 8;
794 break;
795 default:
796 s->needed_bytes += 4;
797 break;
798 }
799 break;
800 default:
801 break;
802 }
803 s->pos = 0;
804 s->len = 0;
805 s->state = STATE_COLLECTING_DATA;
806}
807
808static void decode_qio_read_cmd(Flash *s)
809{
810 s->needed_bytes = get_addr_length(s);
811 /* Dummy cycles modeled with bytes writes instead of bits */
812 switch (get_man(s)) {
813 case MAN_WINBOND:
3830c7a4 814 s->needed_bytes += 8;
cf6f1efe
MK		 815 break;
816 case MAN_SPANSION:
817 s->needed_bytes += SPANSION_CONTINUOUS_READ_MODE_CMD_LEN;
818 s->needed_bytes += extract32(s->spansion_cr2v,
819 SPANSION_DUMMY_CLK_POS,
820 SPANSION_DUMMY_CLK_LEN
821 );
822 break;
823 case MAN_NUMONYX:
824 s->needed_bytes += extract32(s->volatile_cfg, 4, 4);
825 break;
826 case MAN_MACRONIX:
827 switch (extract32(s->volatile_cfg, 6, 2)) {
828 case 1:
829 s->needed_bytes += 4;
830 break;
831 case 2:
832 s->needed_bytes += 8;
833 break;
834 default:
835 s->needed_bytes += 6;
836 break;
837 }
838 break;
839 default:
840 break;
841 }
842 s->pos = 0;
843 s->len = 0;
844 s->state = STATE_COLLECTING_DATA;
845}
846
82a24990
PC		 847static void decode_new_cmd(Flash *s, uint32_t value)
848{
849 s->cmd_in_progress = value;
e3ba6cd6 850 int i;
28097d02 851 DB_PRINT_L(0, "decoded new command:%x\n", value);
82a24990 852
187c2636
MK		 853 if (value != RESET_MEMORY) {
854 s->reset_enable = false;
855 }
856
82a24990
PC		 857 switch (value) {
858
859 case ERASE_4K:
63e47f6f 860 case ERASE4_4K:
82a24990 861 case ERASE_32K:
30467afe 862 case ERASE4_32K:
82a24990 863 case ERASE_SECTOR:
63e47f6f 864 case ERASE4_SECTOR:
82a24990 865 case READ:
63e47f6f 866 case READ4:
419336a9
PC		 867 case DPP:
868 case QPP:
82a24990 869 case PP:
63e47f6f 870 case PP4:
30467afe 871 case PP4_4:
c0f3f675 872 s->needed_bytes = get_addr_length(s);
82a24990
PC		 873 s->pos = 0;
874 s->len = 0;
875 s->state = STATE_COLLECTING_DATA;
876 break;
877
878 case FAST_READ:
63e47f6f 879 case FAST_READ4:
419336a9 880 case DOR:
63e47f6f 881 case DOR4:
419336a9 882 case QOR:
63e47f6f 883 case QOR4:
cf6f1efe 884 decode_fast_read_cmd(s);
82a24990
PC		 885 break;
886
419336a9 887 case DIOR:
63e47f6f 888 case DIOR4:
cf6f1efe 889 decode_dio_read_cmd(s);
419336a9
PC		 890 break;
891
892 case QIOR:
63e47f6f 893 case QIOR4:
cf6f1efe 894 decode_qio_read_cmd(s);
419336a9
PC		 895 break;
896
03ec2f83
KJS		 897 case WRSR:
898 if (s->write_enable) {
7a69c100
MK		 899 switch (get_man(s)) {
900 case MAN_SPANSION:
901 s->needed_bytes = 2;
902 s->state = STATE_COLLECTING_DATA;
903 break;
904 case MAN_MACRONIX:
905 s->needed_bytes = 2;
906 s->state = STATE_COLLECTING_VAR_LEN_DATA;
907 break;
908 default:
909 s->needed_bytes = 1;
910 s->state = STATE_COLLECTING_DATA;
911 }
03ec2f83 912 s->pos = 0;
03ec2f83
KJS		 913 }
914 break;
915
82a24990
PC		 916 case WRDI:
917 s->write_enable = false;
918 break;
919 case WREN:
920 s->write_enable = true;
921 break;
922
923 case RDSR:
924 s->data[0] = (!!s->write_enable) << 1;
7a69c100
MK		 925 if (get_man(s) == MAN_MACRONIX) {
926 s->data[0] |= (!!s->quad_enable) << 6;
927 }
82a24990
PC		 928 s->pos = 0;
929 s->len = 1;
930 s->state = STATE_READING_DATA;
931 break;
932
9fbaa364
MK		 933 case READ_FSR:
934 s->data[0] = FSR_FLASH_READY;
935 if (s->four_bytes_address_mode) {
936 s->data[0] |= FSR_4BYTE_ADDR_MODE_ENABLED;
937 }
938 s->pos = 0;
939 s->len = 1;
940 s->state = STATE_READING_DATA;
941 break;
942
82a24990 943 case JEDEC_READ:
28097d02 944 DB_PRINT_L(0, "populated jedec code\n");
e3ba6cd6
MK		 945 for (i = 0; i < s->pi->id_len; i++) {
946 s->data[i] = s->pi->id[i];
82a24990 947 }
e3ba6cd6
MK		 948
949 s->len = s->pi->id_len;
82a24990
PC		 950 s->pos = 0;
951 s->state = STATE_READING_DATA;
952 break;
953
7a69c100
MK		 954 case RDCR:
955 s->data[0] = s->volatile_cfg & 0xFF;
956 s->data[0] |= (!!s->four_bytes_address_mode) << 5;
957 s->pos = 0;
958 s->len = 1;
959 s->state = STATE_READING_DATA;
960 break;
961
82a24990
PC		 962 case BULK_ERASE:
963 if (s->write_enable) {
28097d02 964 DB_PRINT_L(0, "chip erase\n");
82a24990
PC		 965 flash_erase(s, 0, BULK_ERASE);
966 } else {
e9711b4d
PC		 967 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: chip erase with write "
968 "protect!\n");
82a24990
PC		 969 }
970 break;
971 case NOP:
972 break;
c0f3f675
MK		 973 case EN_4BYTE_ADDR:
974 s->four_bytes_address_mode = true;
975 break;
976 case EX_4BYTE_ADDR:
977 s->four_bytes_address_mode = false;
978 break;
d8a29a7a
MK		 979 case EXTEND_ADDR_READ:
980 s->data[0] = s->ear;
981 s->pos = 0;
982 s->len = 1;
983 s->state = STATE_READING_DATA;
984 break;
985 case EXTEND_ADDR_WRITE:
986 if (s->write_enable) {
987 s->needed_bytes = 1;
988 s->pos = 0;
989 s->len = 0;
990 s->state = STATE_COLLECTING_DATA;
991 }
992 break;
cb475951
MK		 993 case RNVCR:
994 s->data[0] = s->nonvolatile_cfg & 0xFF;
995 s->data[1] = (s->nonvolatile_cfg >> 8) & 0xFF;
996 s->pos = 0;
997 s->len = 2;
998 s->state = STATE_READING_DATA;
999 break;
1000 case WNVCR:
7a69c100 1001 if (s->write_enable && get_man(s) == MAN_NUMONYX) {
cb475951
MK		 1002 s->needed_bytes = 2;
1003 s->pos = 0;
1004 s->len = 0;
1005 s->state = STATE_COLLECTING_DATA;
1006 }
1007 break;
1008 case RVCR:
1009 s->data[0] = s->volatile_cfg & 0xFF;
1010 s->pos = 0;
1011 s->len = 1;
1012 s->state = STATE_READING_DATA;
1013 break;
1014 case WVCR:
1015 if (s->write_enable) {
1016 s->needed_bytes = 1;
1017 s->pos = 0;
1018 s->len = 0;
1019 s->state = STATE_COLLECTING_DATA;
1020 }
1021 break;
1022 case REVCR:
1023 s->data[0] = s->enh_volatile_cfg & 0xFF;
1024 s->pos = 0;
1025 s->len = 1;
1026 s->state = STATE_READING_DATA;
1027 break;
1028 case WEVCR:
1029 if (s->write_enable) {
1030 s->needed_bytes = 1;
1031 s->pos = 0;
1032 s->len = 0;
1033 s->state = STATE_COLLECTING_DATA;
1034 }
1035 break;
187c2636
MK		 1036 case RESET_ENABLE:
1037 s->reset_enable = true;
1038 break;
1039 case RESET_MEMORY:
1040 if (s->reset_enable) {
1041 reset_memory(s);
1042 }
1043 break;
7a69c100
MK		 1044 case RDCR_EQIO:
1045 switch (get_man(s)) {
1046 case MAN_SPANSION:
1047 s->data[0] = (!!s->quad_enable) << 1;
1048 s->pos = 0;
1049 s->len = 1;
1050 s->state = STATE_READING_DATA;
1051 break;
1052 case MAN_MACRONIX:
1053 s->quad_enable = true;
1054 break;
1055 default:
1056 break;
1057 }
1058 break;
1059 case RSTQIO:
1060 s->quad_enable = false;
1061 break;
82a24990 1062 default:
e9711b4d 1063 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Unknown cmd %x\n", value);
82a24990
PC		 1064 break;
1065 }
1066}
1067
1068static int m25p80_cs(SSISlave *ss, bool select)
1069{
cdccf7d7 1070 Flash *s = M25P80(ss);
82a24990
PC		 1071
1072 if (select) {
9964674e
MK		 1073 if (s->state == STATE_COLLECTING_VAR_LEN_DATA) {
1074 complete_collecting_data(s);
1075 }
82a24990
PC		 1076 s->len = 0;
1077 s->pos = 0;
1078 s->state = STATE_IDLE;
1079 flash_sync_dirty(s, -1);
1080 }
1081
28097d02 1082 DB_PRINT_L(0, "%sselect\n", select ? "de" : "");
82a24990
PC		 1083
1084 return 0;
1085}
1086
1087static uint32_t m25p80_transfer8(SSISlave *ss, uint32_t tx)
1088{
cdccf7d7 1089 Flash *s = M25P80(ss);
82a24990
PC		 1090 uint32_t r = 0;
1091
1092 switch (s->state) {
1093
1094 case STATE_PAGE_PROGRAM:
28097d02
PC		 1095 DB_PRINT_L(1, "page program cur_addr=%#" PRIx64 " data=%" PRIx8 "\n",
1096 s->cur_addr, (uint8_t)tx);
82a24990
PC		 1097 flash_write8(s, s->cur_addr, (uint8_t)tx);
1098 s->cur_addr++;
1099 break;
1100
1101 case STATE_READ:
1102 r = s->storage[s->cur_addr];
28097d02
PC		 1103 DB_PRINT_L(1, "READ 0x%" PRIx64 "=%" PRIx8 "\n", s->cur_addr,
1104 (uint8_t)r);
82a24990
PC		 1105 s->cur_addr = (s->cur_addr + 1) % s->size;
1106 break;
1107
1108 case STATE_COLLECTING_DATA:
9964674e 1109 case STATE_COLLECTING_VAR_LEN_DATA:
82a24990
PC		 1110 s->data[s->len] = (uint8_t)tx;
1111 s->len++;
1112
1113 if (s->len == s->needed_bytes) {
1114 complete_collecting_data(s);
1115 }
1116 break;
1117
1118 case STATE_READING_DATA:
1119 r = s->data[s->pos];
1120 s->pos++;
1121 if (s->pos == s->len) {
1122 s->pos = 0;
1123 s->state = STATE_IDLE;
1124 }
1125 break;
1126
1127 default:
1128 case STATE_IDLE:
1129 decode_new_cmd(s, (uint8_t)tx);
1130 break;
1131 }
1132
1133 return r;
1134}
1135
7673bb4c 1136static void m25p80_realize(SSISlave *ss, Error **errp)
82a24990
PC		 1137{
1138 DriveInfo *dinfo;
cdccf7d7 1139 Flash *s = M25P80(ss);
a7fd6915 1140 M25P80Class *mc = M25P80_GET_CLASS(s);
82a24990 1141
a7fd6915 1142 s->pi = mc->pi;
82a24990
PC		 1143
1144 s->size = s->pi->sector_size * s->pi->n_sectors;
1145 s->dirty_page = -1;
82a24990 1146
af9e40aa 1147 /* FIXME use a qdev drive property instead of drive_get_next() */
82a24990
PC		 1148 dinfo = drive_get_next(IF_MTD);
1149
fa1d36df 1150 if (dinfo) {
28097d02 1151 DB_PRINT_L(0, "Binding to IF_MTD drive\n");
4be74634 1152 s->blk = blk_by_legacy_dinfo(dinfo);
d07063e4 1153 blk_attach_dev_nofail(s->blk, s);
4f8a066b 1154
c485cf9c
SH		 1155 s->storage = blk_blockalign(s->blk, s->size);
1156
9e19036e 1157 if (blk_pread(s->blk, 0, s->storage, s->size) != s->size) {
7673bb4c
CLG		 1158 error_setg(errp, "failed to read the initial flash content");
1159 return;
82a24990
PC		 1160 }
1161 } else {
095b9c48 1162 DB_PRINT_L(0, "No BDRV - binding to RAM\n");
c485cf9c 1163 s->storage = blk_blockalign(NULL, s->size);
82a24990
PC		 1164 memset(s->storage, 0xFF, s->size);
1165 }
82a24990
PC		 1166}
1167
187c2636
MK		 1168static void m25p80_reset(DeviceState *d)
1169{
1170 Flash *s = M25P80(d);
1171
1172 reset_memory(s);
1173}
1174
82a24990
PC		 1175static void m25p80_pre_save(void *opaque)
1176{
1177 flash_sync_dirty((Flash *)opaque, -1);
1178}
1179
cb475951 1180static Property m25p80_properties[] = {
d9cc8701 1181 /* This is default value for Micron flash */
cb475951 1182 DEFINE_PROP_UINT32("nonvolatile-cfg", Flash, nonvolatile_cfg, 0x8FFF),
d9cc8701
MK		 1183 DEFINE_PROP_UINT8("spansion-cr1nv", Flash, spansion_cr1nv, 0x0),
1184 DEFINE_PROP_UINT8("spansion-cr2nv", Flash, spansion_cr2nv, 0x8),
1185 DEFINE_PROP_UINT8("spansion-cr3nv", Flash, spansion_cr3nv, 0x2),
1186 DEFINE_PROP_UINT8("spansion-cr4nv", Flash, spansion_cr4nv, 0x10),
cb475951
MK		 1187 DEFINE_PROP_END_OF_LIST(),
1188};
1189
82a24990
PC		 1190static const VMStateDescription vmstate_m25p80 = {
1191 .name = "xilinx_spi",
7a69c100 1192 .version_id = 3,
82a24990 1193 .minimum_version_id = 1,
82a24990
PC		 1194 .pre_save = m25p80_pre_save,
1195 .fields = (VMStateField[]) {
1196 VMSTATE_UINT8(state, Flash),
1197 VMSTATE_UINT8_ARRAY(data, Flash, 16),
1198 VMSTATE_UINT32(len, Flash),
1199 VMSTATE_UINT32(pos, Flash),
1200 VMSTATE_UINT8(needed_bytes, Flash),
1201 VMSTATE_UINT8(cmd_in_progress, Flash),
1202 VMSTATE_UINT64(cur_addr, Flash),
1203 VMSTATE_BOOL(write_enable, Flash),
187c2636 1204 VMSTATE_BOOL_V(reset_enable, Flash, 2),
d8a29a7a 1205 VMSTATE_UINT8_V(ear, Flash, 2),
c0f3f675 1206 VMSTATE_BOOL_V(four_bytes_address_mode, Flash, 2),
cb475951
MK		 1207 VMSTATE_UINT32_V(nonvolatile_cfg, Flash, 2),
1208 VMSTATE_UINT32_V(volatile_cfg, Flash, 2),
1209 VMSTATE_UINT32_V(enh_volatile_cfg, Flash, 2),
7a69c100 1210 VMSTATE_BOOL_V(quad_enable, Flash, 3),
d9cc8701
MK		 1211 VMSTATE_UINT8_V(spansion_cr1nv, Flash, 3),
1212 VMSTATE_UINT8_V(spansion_cr2nv, Flash, 3),
1213 VMSTATE_UINT8_V(spansion_cr3nv, Flash, 3),
1214 VMSTATE_UINT8_V(spansion_cr4nv, Flash, 3),
82a24990
PC		 1215 VMSTATE_END_OF_LIST()
1216 }
1217};
1218
82a24990
PC		 1219static void m25p80_class_init(ObjectClass *klass, void *data)
1220{
1221 DeviceClass *dc = DEVICE_CLASS(klass);
1222 SSISlaveClass *k = SSI_SLAVE_CLASS(klass);
a7fd6915 1223 M25P80Class *mc = M25P80_CLASS(klass);
82a24990 1224
7673bb4c 1225 k->realize = m25p80_realize;
82a24990
PC		 1226 k->transfer = m25p80_transfer8;
1227 k->set_cs = m25p80_cs;
1228 k->cs_polarity = SSI_CS_LOW;
82a24990 1229 dc->vmsd = &vmstate_m25p80;
cb475951 1230 dc->props = m25p80_properties;
187c2636 1231 dc->reset = m25p80_reset;
a7fd6915 1232 mc->pi = data;
82a24990
PC		 1233}
1234
1235static const TypeInfo m25p80_info = {
a7fd6915 1236 .name = TYPE_M25P80,
82a24990
PC		 1237 .parent = TYPE_SSI_SLAVE,
1238 .instance_size = sizeof(Flash),
a7fd6915
PC		 1239 .class_size = sizeof(M25P80Class),
1240 .abstract = true,
82a24990
PC		 1241};
1242
1243static void m25p80_register_types(void)
1244{
a7fd6915
PC		 1245 int i;
1246
82a24990 1247 type_register_static(&m25p80_info);
a7fd6915
PC		 1248 for (i = 0; i < ARRAY_SIZE(known_devices); ++i) {
1249 TypeInfo ti = {
1250 .name = known_devices[i].part_name,
1251 .parent = TYPE_M25P80,
1252 .class_init = m25p80_class_init,
1253 .class_data = (void *)&known_devices[i],
1254 };
1255 type_register(&ti);
1256 }
82a24990
PC		 1257}
1258
1259type_init(m25p80_register_types)
Empty description
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