[qemu.git] / tests / i440fx-test.c

/*
 * qtest I440FX test case
 *
 * Copyright IBM, Corp. 2012-2013
 * Copyright Red Hat, Inc. 2013
 *
 * Authors:
 *  Anthony Liguori   <[email protected]>
 *  Laszlo Ersek      <[email protected]>
 *
 * This work is licensed under the terms of the GNU GPL, version 2 or later.
 * See the COPYING file in the top-level directory.
 */

#include "libqos/pci.h"
#include "libqos/pci-pc.h"
#include "libqtest.h"

#include "hw/pci/pci_regs.h"

#include <glib.h>
#include <string.h>
#include <stdio.h>
#include <unistd.h>
#include <errno.h>
#include <sys/mman.h>
#include <stdlib.h>

#define BROKEN 1

#define ARRAY_SIZE(array) (sizeof(array) / sizeof((array)[0]))

typedef struct TestData
{
    int num_cpus;
} TestData;

typedef struct FirmwareTestFixture {
    /* decides whether we're testing -bios or -pflash */
    bool is_bios;
} FirmwareTestFixture;

static QPCIBus *test_start_get_bus(const TestData *s)
{
    char *cmdline;

    cmdline = g_strdup_printf("-smp %d", s->num_cpus);
    qtest_start(cmdline);
    g_free(cmdline);
    return qpci_init_pc();
}

static void test_i440fx_defaults(gconstpointer opaque)
{
    const TestData *s = opaque;
    QPCIBus *bus;
    QPCIDevice *dev;
    uint32_t value;

    bus = test_start_get_bus(s);
    dev = qpci_device_find(bus, QPCI_DEVFN(0, 0));
    g_assert(dev != NULL);

    /* 3.2.2 */
    g_assert_cmpint(qpci_config_readw(dev, PCI_VENDOR_ID), ==, 0x8086);
    /* 3.2.3 */
    g_assert_cmpint(qpci_config_readw(dev, PCI_DEVICE_ID), ==, 0x1237);
#ifndef BROKEN
    /* 3.2.4 */
    g_assert_cmpint(qpci_config_readw(dev, PCI_COMMAND), ==, 0x0006);
    /* 3.2.5 */
    g_assert_cmpint(qpci_config_readw(dev, PCI_STATUS), ==, 0x0280);
#endif
    /* 3.2.7 */
    g_assert_cmpint(qpci_config_readb(dev, PCI_CLASS_PROG), ==, 0x00);
    g_assert_cmpint(qpci_config_readw(dev, PCI_CLASS_DEVICE), ==, 0x0600);
    /* 3.2.8 */
    g_assert_cmpint(qpci_config_readb(dev, PCI_LATENCY_TIMER), ==, 0x00);
    /* 3.2.9 */
    g_assert_cmpint(qpci_config_readb(dev, PCI_HEADER_TYPE), ==, 0x00);
    /* 3.2.10 */
    g_assert_cmpint(qpci_config_readb(dev, PCI_BIST), ==, 0x00);

    /* 3.2.11 */
    value = qpci_config_readw(dev, 0x50); /* PMCCFG */
    if (s->num_cpus == 1) { /* WPE */
        g_assert(!(value & (1 << 15)));
    } else {
        g_assert((value & (1 << 15)));
    }

    g_assert(!(value & (1 << 6))); /* EPTE */

    /* 3.2.12 */
    g_assert_cmpint(qpci_config_readb(dev, 0x52), ==, 0x00); /* DETURBO */
    /* 3.2.13 */
#ifndef BROKEN
    g_assert_cmpint(qpci_config_readb(dev, 0x53), ==, 0x80); /* DBC */
#endif
    /* 3.2.14 */
    g_assert_cmpint(qpci_config_readb(dev, 0x54), ==, 0x00); /* AXC */
    /* 3.2.15 */
    g_assert_cmpint(qpci_config_readw(dev, 0x55), ==, 0x0000); /* DRT */
#ifndef BROKEN
    /* 3.2.16 */
    g_assert_cmpint(qpci_config_readb(dev, 0x57), ==, 0x01); /* DRAMC */
    /* 3.2.17 */
    g_assert_cmpint(qpci_config_readb(dev, 0x58), ==, 0x10); /* DRAMT */
#endif
    /* 3.2.18 */
    g_assert_cmpint(qpci_config_readb(dev, 0x59), ==, 0x00); /* PAM0 */
    g_assert_cmpint(qpci_config_readb(dev, 0x5A), ==, 0x00); /* PAM1 */
    g_assert_cmpint(qpci_config_readb(dev, 0x5B), ==, 0x00); /* PAM2 */
    g_assert_cmpint(qpci_config_readb(dev, 0x5C), ==, 0x00); /* PAM3 */
    g_assert_cmpint(qpci_config_readb(dev, 0x5D), ==, 0x00); /* PAM4 */
    g_assert_cmpint(qpci_config_readb(dev, 0x5E), ==, 0x00); /* PAM5 */
    g_assert_cmpint(qpci_config_readb(dev, 0x5F), ==, 0x00); /* PAM6 */
#ifndef BROKEN
    /* 3.2.19 */
    g_assert_cmpint(qpci_config_readb(dev, 0x60), ==, 0x01); /* DRB0 */
    g_assert_cmpint(qpci_config_readb(dev, 0x61), ==, 0x01); /* DRB1 */
    g_assert_cmpint(qpci_config_readb(dev, 0x62), ==, 0x01); /* DRB2 */
    g_assert_cmpint(qpci_config_readb(dev, 0x63), ==, 0x01); /* DRB3 */
    g_assert_cmpint(qpci_config_readb(dev, 0x64), ==, 0x01); /* DRB4 */
    g_assert_cmpint(qpci_config_readb(dev, 0x65), ==, 0x01); /* DRB5 */
    g_assert_cmpint(qpci_config_readb(dev, 0x66), ==, 0x01); /* DRB6 */
    g_assert_cmpint(qpci_config_readb(dev, 0x67), ==, 0x01); /* DRB7 */
#endif
    /* 3.2.20 */
    g_assert_cmpint(qpci_config_readb(dev, 0x68), ==, 0x00); /* FDHC */
    /* 3.2.21 */
    g_assert_cmpint(qpci_config_readb(dev, 0x70), ==, 0x00); /* MTT */
#ifndef BROKEN
    /* 3.2.22 */
    g_assert_cmpint(qpci_config_readb(dev, 0x71), ==, 0x10); /* CLT */
#endif
    /* 3.2.23 */
    g_assert_cmpint(qpci_config_readb(dev, 0x72), ==, 0x02); /* SMRAM */
    /* 3.2.24 */
    g_assert_cmpint(qpci_config_readb(dev, 0x90), ==, 0x00); /* ERRCMD */
    /* 3.2.25 */
    g_assert_cmpint(qpci_config_readb(dev, 0x91), ==, 0x00); /* ERRSTS */
    /* 3.2.26 */
    g_assert_cmpint(qpci_config_readb(dev, 0x93), ==, 0x00); /* TRC */

    qtest_end();
}

#define PAM_RE 1
#define PAM_WE 2

static void pam_set(QPCIDevice *dev, int index, int flags)
{
    int regno = 0x59 + (index / 2);
    uint8_t reg;

    reg = qpci_config_readb(dev, regno);
    if (index & 1) {
        reg = (reg & 0x0F) | (flags << 4);
    } else {
        reg = (reg & 0xF0) | flags;
    }
    qpci_config_writeb(dev, regno, reg);
}

static gboolean verify_area(uint32_t start, uint32_t end, uint8_t value)
{
    uint32_t size = end - start + 1;
    gboolean ret = TRUE;
    uint8_t *data;
    int i;

    data = g_malloc0(size);
    memread(start, data, size);

    g_test_message("verify_area: data[0] = 0x%x", data[0]);

    for (i = 0; i < size; i++) {
        if (data[i] != value) {
            ret = FALSE;
            break;
        }
    }

    g_free(data);

    return ret;
}

static void write_area(uint32_t start, uint32_t end, uint8_t value)
{
    uint32_t size = end - start + 1;
    uint8_t *data;

    data = g_malloc0(size);
    memset(data, value, size);
    memwrite(start, data, size);

    g_free(data);
}

static void test_i440fx_pam(gconstpointer opaque)
{
    const TestData *s = opaque;
    QPCIBus *bus;
    QPCIDevice *dev;
    int i;
    static struct {
        uint32_t start;
        uint32_t end;
    } pam_area[] = {
        { 0, 0 },             /* Reserved */
        { 0xF0000, 0xFFFFF }, /* BIOS Area */
        { 0xC0000, 0xC3FFF }, /* Option ROM */
        { 0xC4000, 0xC7FFF }, /* Option ROM */
        { 0xC8000, 0xCBFFF }, /* Option ROM */
        { 0xCC000, 0xCFFFF }, /* Option ROM */
        { 0xD0000, 0xD3FFF }, /* Option ROM */
        { 0xD4000, 0xD7FFF }, /* Option ROM */
        { 0xD8000, 0xDBFFF }, /* Option ROM */
        { 0xDC000, 0xDFFFF }, /* Option ROM */
        { 0xE0000, 0xE3FFF }, /* BIOS Extension */
        { 0xE4000, 0xE7FFF }, /* BIOS Extension */
        { 0xE8000, 0xEBFFF }, /* BIOS Extension */
        { 0xEC000, 0xEFFFF }, /* BIOS Extension */
    };

    bus = test_start_get_bus(s);
    dev = qpci_device_find(bus, QPCI_DEVFN(0, 0));
    g_assert(dev != NULL);

    for (i = 0; i < ARRAY_SIZE(pam_area); i++) {
        if (pam_area[i].start == pam_area[i].end) {
            continue;
        }

        g_test_message("Checking area 0x%05x..0x%05x",
                       pam_area[i].start, pam_area[i].end);
        /* Switch to RE for the area */
        pam_set(dev, i, PAM_RE);
        /* Verify the RAM is all zeros */
        g_assert(verify_area(pam_area[i].start, pam_area[i].end, 0));

        /* Switch to WE for the area */
        pam_set(dev, i, PAM_RE | PAM_WE);
        /* Write out a non-zero mask to the full area */
        write_area(pam_area[i].start, pam_area[i].end, 0x42);

#ifndef BROKEN
        /* QEMU only supports a limited form of PAM */

        /* Switch to !RE for the area */
        pam_set(dev, i, PAM_WE);
        /* Verify the area is not our mask */
        g_assert(!verify_area(pam_area[i].start, pam_area[i].end, 0x42));
#endif

        /* Verify the area is our new mask */
        g_assert(verify_area(pam_area[i].start, pam_area[i].end, 0x42));

        /* Write out a new mask */
        write_area(pam_area[i].start, pam_area[i].end, 0x82);

#ifndef BROKEN
        /* QEMU only supports a limited form of PAM */

        /* Verify the area is not our mask */
        g_assert(!verify_area(pam_area[i].start, pam_area[i].end, 0x82));

        /* Switch to RE for the area */
        pam_set(dev, i, PAM_RE | PAM_WE);
#endif
        /* Verify the area is our new mask */
        g_assert(verify_area(pam_area[i].start, pam_area[i].end, 0x82));

        /* Reset area */
        pam_set(dev, i, 0);

        /* Verify the area is not our new mask */
        g_assert(!verify_area(pam_area[i].start, pam_area[i].end, 0x82));
    }
    qtest_end();
}

#define BLOB_SIZE ((size_t)65536)
#define ISA_BIOS_MAXSZ ((size_t)(128 * 1024))

/* Create a blob file, and return its absolute pathname as a dynamically
 * allocated string.
 * The file is closed before the function returns.
 * In case of error, NULL is returned. The function prints the error message.
 */
static char *create_blob_file(void)
{
    int ret, fd;
    char *pathname;
    GError *error = NULL;

    ret = -1;
    fd = g_file_open_tmp("blob_XXXXXX", &pathname, &error);
    if (fd == -1) {
        fprintf(stderr, "unable to create blob file: %s\n", error->message);
        g_error_free(error);
    } else {
        if (ftruncate(fd, BLOB_SIZE) == -1) {
            fprintf(stderr, "ftruncate(\"%s\", %zu): %s\n", pathname,
                    BLOB_SIZE, strerror(errno));
        } else {
            void *buf;

            buf = mmap(NULL, BLOB_SIZE, PROT_WRITE, MAP_SHARED, fd, 0);
            if (buf == MAP_FAILED) {
                fprintf(stderr, "mmap(\"%s\", %zu): %s\n", pathname, BLOB_SIZE,
                        strerror(errno));
            } else {
                size_t i;

                for (i = 0; i < BLOB_SIZE; ++i) {
                    ((uint8_t *)buf)[i] = i;
                }
                munmap(buf, BLOB_SIZE);
                ret = 0;
            }
        }
        close(fd);
        if (ret == -1) {
            unlink(pathname);
            g_free(pathname);
        }
    }

    return ret == -1 ? NULL : pathname;
}

static void test_i440fx_firmware(FirmwareTestFixture *fixture,
                                 gconstpointer user_data)
{
    char *fw_pathname, *cmdline;
    uint8_t *buf;
    size_t i, isa_bios_size;

    fw_pathname = create_blob_file();
    g_assert(fw_pathname != NULL);

    /* Better hope the user didn't put metacharacters in TMPDIR and co. */
    cmdline = g_strdup_printf("-S %s %s",
                              fixture->is_bios ? "-bios" : "-pflash",
                              fw_pathname);
    g_test_message("qemu cmdline: %s", cmdline);
    qtest_start(cmdline);
    g_free(cmdline);

    /* Qemu has loaded the firmware (because qtest_start() only returns after
     * the QMP handshake completes). We must unlink the firmware blob right
     * here, because any assertion firing below would leak it in the
     * filesystem. This is also the reason why we recreate the blob every time
     * this function is invoked.
     */
    unlink(fw_pathname);
    g_free(fw_pathname);

    /* check below 4G */
    buf = g_malloc0(BLOB_SIZE);
    memread(0x100000000ULL - BLOB_SIZE, buf, BLOB_SIZE);
    for (i = 0; i < BLOB_SIZE; ++i) {
        g_assert_cmphex(buf[i], ==, (uint8_t)i);
    }

    /* check in ISA space too */
    memset(buf, 0, BLOB_SIZE);
    isa_bios_size = ISA_BIOS_MAXSZ < BLOB_SIZE ? ISA_BIOS_MAXSZ : BLOB_SIZE;
    memread(0x100000 - isa_bios_size, buf, isa_bios_size);
    for (i = 0; i < isa_bios_size; ++i) {
        g_assert_cmphex(buf[i], ==,
                        (uint8_t)((BLOB_SIZE - isa_bios_size) + i));
    }

    g_free(buf);
    qtest_end();
}

static void add_firmware_test(const char *testpath,
                              void (*setup_fixture)(FirmwareTestFixture *f,
                                                    gconstpointer test_data))
{
    g_test_add(testpath, FirmwareTestFixture, NULL, setup_fixture,
               test_i440fx_firmware, NULL);
}

static void request_bios(FirmwareTestFixture *fixture,
                         gconstpointer user_data)
{
    fixture->is_bios = true;
}

static void request_pflash(FirmwareTestFixture *fixture,
                           gconstpointer user_data)
{
    fixture->is_bios = false;
}

int main(int argc, char **argv)
{
    TestData data;
    int ret;

    g_test_init(&argc, &argv, NULL);

    data.num_cpus = 1;

    g_test_add_data_func("/i440fx/defaults", &data, test_i440fx_defaults);
    g_test_add_data_func("/i440fx/pam", &data, test_i440fx_pam);
    add_firmware_test("/i440fx/firmware/bios", request_bios);
    add_firmware_test("/i440fx/firmware/pflash", request_pflash);

    ret = g_test_run();
    return ret;
}
Commit	Line	Data
9bda413c AL	1	/*
	2	* qtest I440FX test case
	3	*
	4	* Copyright IBM, Corp. 2012-2013
b817e3fb	5	* Copyright Red Hat, Inc. 2013
9bda413c AL	6	*
	7	* Authors:
	8	* Anthony Liguori <[email protected]>
b817e3fb	9	* Laszlo Ersek <[email protected]>
9bda413c AL	10	*
	11	* This work is licensed under the terms of the GNU GPL, version 2 or later.
	12	* See the COPYING file in the top-level directory.
	13	*/
	14
	15	#include "libqos/pci.h"
	16	#include "libqos/pci-pc.h"
	17	#include "libqtest.h"
	18
	19	#include "hw/pci/pci_regs.h"
	20
	21	#include <glib.h>
a875711a	22	#include <string.h>
27d59ccd LE	23	#include <stdio.h>
	24	#include <unistd.h>
	25	#include <errno.h>
	26	#include <sys/mman.h>
	27	#include <stdlib.h>
9bda413c AL	28
	29	#define BROKEN 1
	30
a875711a AL	31	#define ARRAY_SIZE(array) (sizeof(array) / sizeof((array)[0]))
a875711a AL	32
9bda413c AL	33	typedef struct TestData
	34	{
	35	int num_cpus;
9bda413c AL	36	} TestData;
9bda413c AL	37
3bcc77ae LE	38	typedef struct FirmwareTestFixture {
	39	/* decides whether we're testing -bios or -pflash */
	40	bool is_bios;
	41	} FirmwareTestFixture;
	42
c37805b6 LE	43	static QPCIBus test_start_get_bus(const TestData s)
	44	{
	45	char *cmdline;
	46
	47	cmdline = g_strdup_printf("-smp %d", s->num_cpus);
	48	qtest_start(cmdline);
	49	g_free(cmdline);
	50	return qpci_init_pc();
	51	}
	52
9bda413c AL	53	static void test_i440fx_defaults(gconstpointer opaque)
	54	{
	55	const TestData *s = opaque;
c37805b6	56	QPCIBus *bus;
9bda413c AL	57	QPCIDevice *dev;
	58	uint32_t value;
	59
c37805b6 LE	60	bus = test_start_get_bus(s);
c37805b6 LE	61	dev = qpci_device_find(bus, QPCI_DEVFN(0, 0));
9bda413c AL	62	g_assert(dev != NULL);
	63
	64	/* 3.2.2 */
	65	g_assert_cmpint(qpci_config_readw(dev, PCI_VENDOR_ID), ==, 0x8086);
	66	/* 3.2.3 */
	67	g_assert_cmpint(qpci_config_readw(dev, PCI_DEVICE_ID), ==, 0x1237);
	68	#ifndef BROKEN
	69	/* 3.2.4 */
	70	g_assert_cmpint(qpci_config_readw(dev, PCI_COMMAND), ==, 0x0006);
	71	/* 3.2.5 */
	72	g_assert_cmpint(qpci_config_readw(dev, PCI_STATUS), ==, 0x0280);
	73	#endif
	74	/* 3.2.7 */
	75	g_assert_cmpint(qpci_config_readb(dev, PCI_CLASS_PROG), ==, 0x00);
	76	g_assert_cmpint(qpci_config_readw(dev, PCI_CLASS_DEVICE), ==, 0x0600);
	77	/* 3.2.8 */
	78	g_assert_cmpint(qpci_config_readb(dev, PCI_LATENCY_TIMER), ==, 0x00);
	79	/* 3.2.9 */
	80	g_assert_cmpint(qpci_config_readb(dev, PCI_HEADER_TYPE), ==, 0x00);
	81	/* 3.2.10 */
	82	g_assert_cmpint(qpci_config_readb(dev, PCI_BIST), ==, 0x00);
	83
	84	/* 3.2.11 */
	85	value = qpci_config_readw(dev, 0x50); /* PMCCFG */
	86	if (s->num_cpus == 1) { /* WPE */
	87	g_assert(!(value & (1 << 15)));
	88	} else {
	89	g_assert((value & (1 << 15)));
	90	}
	91
	92	g_assert(!(value & (1 << 6))); /* EPTE */
	93
	94	/* 3.2.12 */
	95	g_assert_cmpint(qpci_config_readb(dev, 0x52), ==, 0x00); /* DETURBO */
	96	/* 3.2.13 */
	97	#ifndef BROKEN
	98	g_assert_cmpint(qpci_config_readb(dev, 0x53), ==, 0x80); /* DBC */
	99	#endif
	100	/* 3.2.14 */
	101	g_assert_cmpint(qpci_config_readb(dev, 0x54), ==, 0x00); /* AXC */
	102	/* 3.2.15 */
	103	g_assert_cmpint(qpci_config_readw(dev, 0x55), ==, 0x0000); /* DRT */
	104	#ifndef BROKEN
	105	/* 3.2.16 */
	106	g_assert_cmpint(qpci_config_readb(dev, 0x57), ==, 0x01); /* DRAMC */
	107	/* 3.2.17 */
	108	g_assert_cmpint(qpci_config_readb(dev, 0x58), ==, 0x10); /* DRAMT */
	109	#endif
	110	/* 3.2.18 */
	111	g_assert_cmpint(qpci_config_readb(dev, 0x59), ==, 0x00); /* PAM0 */
	112	g_assert_cmpint(qpci_config_readb(dev, 0x5A), ==, 0x00); /* PAM1 */
	113	g_assert_cmpint(qpci_config_readb(dev, 0x5B), ==, 0x00); /* PAM2 */
	114	g_assert_cmpint(qpci_config_readb(dev, 0x5C), ==, 0x00); /* PAM3 */
	115	g_assert_cmpint(qpci_config_readb(dev, 0x5D), ==, 0x00); /* PAM4 */
	116	g_assert_cmpint(qpci_config_readb(dev, 0x5E), ==, 0x00); /* PAM5 */
	117	g_assert_cmpint(qpci_config_readb(dev, 0x5F), ==, 0x00); /* PAM6 */
	118	#ifndef BROKEN
	119	/* 3.2.19 */
	120	g_assert_cmpint(qpci_config_readb(dev, 0x60), ==, 0x01); /* DRB0 */
	121	g_assert_cmpint(qpci_config_readb(dev, 0x61), ==, 0x01); /* DRB1 */
	122	g_assert_cmpint(qpci_config_readb(dev, 0x62), ==, 0x01); /* DRB2 */
	123	g_assert_cmpint(qpci_config_readb(dev, 0x63), ==, 0x01); /* DRB3 */
	124	g_assert_cmpint(qpci_config_readb(dev, 0x64), ==, 0x01); /* DRB4 */
	125	g_assert_cmpint(qpci_config_readb(dev, 0x65), ==, 0x01); /* DRB5 */
126	g_assert_cmpint(qpci_config_readb(dev, 0x66), ==, 0x01); /* DRB6 */
127	g_assert_cmpint(qpci_config_readb(dev, 0x67), ==, 0x01); /* DRB7 */
128	#endif
129	/* 3.2.20 */
130	g_assert_cmpint(qpci_config_readb(dev, 0x68), ==, 0x00); /* FDHC */
131	/* 3.2.21 */
132	g_assert_cmpint(qpci_config_readb(dev, 0x70), ==, 0x00); /* MTT */
133	#ifndef BROKEN
134	/* 3.2.22 */
135	g_assert_cmpint(qpci_config_readb(dev, 0x71), ==, 0x10); /* CLT */
136	#endif
137	/* 3.2.23 */
138	g_assert_cmpint(qpci_config_readb(dev, 0x72), ==, 0x02); /* SMRAM */
139	/* 3.2.24 */
140	g_assert_cmpint(qpci_config_readb(dev, 0x90), ==, 0x00); /* ERRCMD */
141	/* 3.2.25 */
142	g_assert_cmpint(qpci_config_readb(dev, 0x91), ==, 0x00); /* ERRSTS */
143	/* 3.2.26 */
144	g_assert_cmpint(qpci_config_readb(dev, 0x93), ==, 0x00); /* TRC */
c37805b6 LE	145
c37805b6 LE	146	qtest_end();
9bda413c AL	147	}
9bda413c AL	148
a875711a AL	149	#define PAM_RE 1
	150	#define PAM_WE 2
	151
	152	static void pam_set(QPCIDevice *dev, int index, int flags)
	153	{
	154	int regno = 0x59 + (index / 2);
	155	uint8_t reg;
	156
	157	reg = qpci_config_readb(dev, regno);
	158	if (index & 1) {
	159	reg = (reg & 0x0F) \| (flags << 4);
	160	} else {
	161	reg = (reg & 0xF0) \| flags;
	162	}
	163	qpci_config_writeb(dev, regno, reg);
	164	}
	165
	166	static gboolean verify_area(uint32_t start, uint32_t end, uint8_t value)
	167	{
	168	uint32_t size = end - start + 1;
	169	gboolean ret = TRUE;
	170	uint8_t *data;
	171	int i;
	172
	173	data = g_malloc0(size);
	174	memread(start, data, size);
	175
	176	g_test_message("verify_area: data[0] = 0x%x", data[0]);
	177
	178	for (i = 0; i < size; i++) {
	179	if (data[i] != value) {
	180	ret = FALSE;
	181	break;
	182	}
	183	}
	184
	185	g_free(data);
	186
	187	return ret;
	188	}
	189
	190	static void write_area(uint32_t start, uint32_t end, uint8_t value)
	191	{
	192	uint32_t size = end - start + 1;
	193	uint8_t *data;
	194
	195	data = g_malloc0(size);
	196	memset(data, value, size);
	197	memwrite(start, data, size);
	198
	199	g_free(data);
	200	}
	201
	202	static void test_i440fx_pam(gconstpointer opaque)
	203	{
	204	const TestData *s = opaque;
c37805b6	205	QPCIBus *bus;
a875711a AL	206	QPCIDevice *dev;
	207	int i;
	208	static struct {
	209	uint32_t start;
	210	uint32_t end;
	211	} pam_area[] = {
	212	{ 0, 0 }, /* Reserved */
	213	{ 0xF0000, 0xFFFFF }, /* BIOS Area */
	214	{ 0xC0000, 0xC3FFF }, /* Option ROM */
	215	{ 0xC4000, 0xC7FFF }, /* Option ROM */
	216	{ 0xC8000, 0xCBFFF }, /* Option ROM */
	217	{ 0xCC000, 0xCFFFF }, /* Option ROM */
	218	{ 0xD0000, 0xD3FFF }, /* Option ROM */
	219	{ 0xD4000, 0xD7FFF }, /* Option ROM */
	220	{ 0xD8000, 0xDBFFF }, /* Option ROM */
	221	{ 0xDC000, 0xDFFFF }, /* Option ROM */
	222	{ 0xE0000, 0xE3FFF }, /* BIOS Extension */
	223	{ 0xE4000, 0xE7FFF }, /* BIOS Extension */
	224	{ 0xE8000, 0xEBFFF }, /* BIOS Extension */
	225	{ 0xEC000, 0xEFFFF }, /* BIOS Extension */
	226	};
	227
c37805b6 LE	228	bus = test_start_get_bus(s);
c37805b6 LE	229	dev = qpci_device_find(bus, QPCI_DEVFN(0, 0));
a875711a AL	230	g_assert(dev != NULL);
	231
	232	for (i = 0; i < ARRAY_SIZE(pam_area); i++) {
	233	if (pam_area[i].start == pam_area[i].end) {
	234	continue;
	235	}
	236
	237	g_test_message("Checking area 0x%05x..0x%05x",
	238	pam_area[i].start, pam_area[i].end);
	239	/* Switch to RE for the area */
	240	pam_set(dev, i, PAM_RE);
	241	/* Verify the RAM is all zeros */
	242	g_assert(verify_area(pam_area[i].start, pam_area[i].end, 0));
	243
	244	/* Switch to WE for the area */
	245	pam_set(dev, i, PAM_RE \| PAM_WE);
	246	/* Write out a non-zero mask to the full area */
	247	write_area(pam_area[i].start, pam_area[i].end, 0x42);
	248
	249	#ifndef BROKEN
	250	/* QEMU only supports a limited form of PAM */
	251
	252	/* Switch to !RE for the area */
	253	pam_set(dev, i, PAM_WE);
	254	/* Verify the area is not our mask */
	255	g_assert(!verify_area(pam_area[i].start, pam_area[i].end, 0x42));
	256	#endif
	257
	258	/* Verify the area is our new mask */
	259	g_assert(verify_area(pam_area[i].start, pam_area[i].end, 0x42));
	260
	261	/* Write out a new mask */
	262	write_area(pam_area[i].start, pam_area[i].end, 0x82);
	263
	264	#ifndef BROKEN
	265	/* QEMU only supports a limited form of PAM */
	266
	267	/* Verify the area is not our mask */
	268	g_assert(!verify_area(pam_area[i].start, pam_area[i].end, 0x82));
	269
	270	/* Switch to RE for the area */
	271	pam_set(dev, i, PAM_RE \| PAM_WE);
	272	#endif
	273	/* Verify the area is our new mask */
	274	g_assert(verify_area(pam_area[i].start, pam_area[i].end, 0x82));
	275
	276	/* Reset area */
	277	pam_set(dev, i, 0);
	278
	279	/* Verify the area is not our new mask */
	280	g_assert(!verify_area(pam_area[i].start, pam_area[i].end, 0x82));
	281	}
c37805b6	282	qtest_end();
a875711a AL	283	}
a875711a AL	284
27d59ccd	285	#define BLOB_SIZE ((size_t)65536)
3bcc77ae	286	#define ISA_BIOS_MAXSZ ((size_t)(128 * 1024))
27d59ccd LE	287
	288	/* Create a blob file, and return its absolute pathname as a dynamically
	289	* allocated string.
	290	* The file is closed before the function returns.
	291	* In case of error, NULL is returned. The function prints the error message.
	292	*/
	293	static char *create_blob_file(void)
	294	{
	295	int ret, fd;
	296	char *pathname;
	297	GError *error = NULL;
	298
	299	ret = -1;
	300	fd = g_file_open_tmp("blob_XXXXXX", &pathname, &error);
	301	if (fd == -1) {
	302	fprintf(stderr, "unable to create blob file: %s\n", error->message);
	303	g_error_free(error);
	304	} else {
	305	if (ftruncate(fd, BLOB_SIZE) == -1) {
	306	fprintf(stderr, "ftruncate(\"%s\", %zu): %s\n", pathname,
	307	BLOB_SIZE, strerror(errno));
	308	} else {
	309	void *buf;
	310
	311	buf = mmap(NULL, BLOB_SIZE, PROT_WRITE, MAP_SHARED, fd, 0);
	312	if (buf == MAP_FAILED) {
	313	fprintf(stderr, "mmap(\"%s\", %zu): %s\n", pathname, BLOB_SIZE,
	314	strerror(errno));
	315	} else {
	316	size_t i;
	317
	318	for (i = 0; i < BLOB_SIZE; ++i) {
	319	((uint8_t *)buf)[i] = i;
	320	}
	321	munmap(buf, BLOB_SIZE);
	322	ret = 0;
	323	}
	324	}
	325	close(fd);
	326	if (ret == -1) {
	327	unlink(pathname);
	328	g_free(pathname);
	329	}
	330	}
	331
	332	return ret == -1 ? NULL : pathname;
	333	}
	334
3bcc77ae LE	335	static void test_i440fx_firmware(FirmwareTestFixture *fixture,
3bcc77ae LE	336	gconstpointer user_data)
9bda413c	337	{
3bcc77ae LE	338	char fw_pathname, cmdline;
	339	uint8_t *buf;
	340	size_t i, isa_bios_size;
9bda413c	341
27d59ccd LE	342	fw_pathname = create_blob_file();
27d59ccd LE	343	g_assert(fw_pathname != NULL);
3bcc77ae LE	344
	345	/* Better hope the user didn't put metacharacters in TMPDIR and co. */
	346	cmdline = g_strdup_printf("-S %s %s",
	347	fixture->is_bios ? "-bios" : "-pflash",
	348	fw_pathname);
	349	g_test_message("qemu cmdline: %s", cmdline);
	350	qtest_start(cmdline);
	351	g_free(cmdline);
	352
	353	/* Qemu has loaded the firmware (because qtest_start() only returns after
	354	* the QMP handshake completes). We must unlink the firmware blob right
	355	* here, because any assertion firing below would leak it in the
	356	* filesystem. This is also the reason why we recreate the blob every time
	357	* this function is invoked.
	358	*/
27d59ccd LE	359	unlink(fw_pathname);
	360	g_free(fw_pathname);
	361
3bcc77ae LE	362	/* check below 4G */
	363	buf = g_malloc0(BLOB_SIZE);
	364	memread(0x100000000ULL - BLOB_SIZE, buf, BLOB_SIZE);
	365	for (i = 0; i < BLOB_SIZE; ++i) {
	366	g_assert_cmphex(buf[i], ==, (uint8_t)i);
	367	}
	368
	369	/* check in ISA space too */
	370	memset(buf, 0, BLOB_SIZE);
	371	isa_bios_size = ISA_BIOS_MAXSZ < BLOB_SIZE ? ISA_BIOS_MAXSZ : BLOB_SIZE;
	372	memread(0x100000 - isa_bios_size, buf, isa_bios_size);
	373	for (i = 0; i < isa_bios_size; ++i) {
	374	g_assert_cmphex(buf[i], ==,
	375	(uint8_t)((BLOB_SIZE - isa_bios_size) + i));
	376	}
	377
	378	g_free(buf);
	379	qtest_end();
	380	}
	381
	382	static void add_firmware_test(const char *testpath,
	383	void (setup_fixture)(FirmwareTestFixture f,
	384	gconstpointer test_data))
	385	{
	386	g_test_add(testpath, FirmwareTestFixture, NULL, setup_fixture,
	387	test_i440fx_firmware, NULL);
	388	}
	389
	390	static void request_bios(FirmwareTestFixture *fixture,
	391	gconstpointer user_data)
	392	{
	393	fixture->is_bios = true;
	394	}
	395
	396	static void request_pflash(FirmwareTestFixture *fixture,
	397	gconstpointer user_data)
	398	{
	399	fixture->is_bios = false;
	400	}
	401
	402	int main(int argc, char **argv)
	403	{
	404	TestData data;
	405	int ret;
	406
	407	g_test_init(&argc, &argv, NULL);
	408
9bda413c AL	409	data.num_cpus = 1;
9bda413c AL	410
9bda413c	411	g_test_add_data_func("/i440fx/defaults", &data, test_i440fx_defaults);
a875711a	412	g_test_add_data_func("/i440fx/pam", &data, test_i440fx_pam);
3bcc77ae LE	413	add_firmware_test("/i440fx/firmware/bios", request_bios);
3bcc77ae LE	414	add_firmware_test("/i440fx/firmware/pflash", request_pflash);
9bda413c AL	415
9bda413c AL	416	ret = g_test_run();
9bda413c AL	417	return ret;
9bda413c AL	418	}