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hw/block/nvme: Align I/O BAR to 4 KiB
[qemu.git] / hw / sd / sdhci.c
CommitLineData
d7dfca08
IM		 1/*
2 * SD Association Host Standard Specification v2.0 controller emulation
3 *
4 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
5 * Mitsyanko Igor <[email protected]>
6 * Peter A.G. Crosthwaite <[email protected]>
7 *
8 * Based on MMC controller for Samsung S5PC1xx-based board emulation
9 * by Alexey Merkulov and Vladimir Monakhov.
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
19 * See the GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License along
22 * with this program; if not, see <http://www.gnu.org/licenses/>.
23 */
24
0430891c 25#include "qemu/osdep.h"
4c8f9735 26#include "qemu/units.h"
6ff37c3d 27#include "qemu/error-report.h"
b635d98c 28#include "qapi/error.h"
64552b6b 29#include "hw/irq.h"
a27bd6c7 30#include "hw/qdev-properties.h"
d7dfca08
IM		 31#include "sysemu/dma.h"
32#include "qemu/timer.h"
d7dfca08 33#include "qemu/bitops.h"
f82a0f44 34#include "hw/sd/sdhci.h"
d6454270 35#include "migration/vmstate.h"
637d23be 36#include "sdhci-internal.h"
03dd024f 37#include "qemu/log.h"
0b8fa32f 38#include "qemu/module.h"
8be487d8 39#include "trace.h"
d7dfca08 40
40bbc194
PM		 41#define TYPE_SDHCI_BUS "sdhci-bus"
42#define SDHCI_BUS(obj) OBJECT_CHECK(SDBus, (obj), TYPE_SDHCI_BUS)
43
aa164fbf
PMD		 44#define MASKED_WRITE(reg, mask, val) (reg = (reg & (mask)) | (val))
45
09b738ff
PMD		 46static inline unsigned int sdhci_get_fifolen(SDHCIState *s)
47{
48 return 1 << (9 + FIELD_EX32(s->capareg, SDHC_CAPAB, MAXBLOCKLENGTH));
49}
50
6ff37c3d
PMD		 51/* return true on error */
52static bool sdhci_check_capab_freq_range(SDHCIState *s, const char *desc,
53 uint8_t freq, Error **errp)
54{
4d67852d
PMD		 55 if (s->sd_spec_version >= 3) {
56 return false;
57 }
6ff37c3d
PMD		 58 switch (freq) {
59 case 0:
60 case 10 ... 63:
61 break;
62 default:
63 error_setg(errp, "SD %s clock frequency can have value"
64 "in range 0-63 only", desc);
65 return true;
66 }
67 return false;
68}
69
70static void sdhci_check_capareg(SDHCIState *s, Error **errp)
71{
72 uint64_t msk = s->capareg;
73 uint32_t val;
74 bool y;
75
76 switch (s->sd_spec_version) {
1e23b63f
PMD		 77 case 4:
78 val = FIELD_EX64(s->capareg, SDHC_CAPAB, BUS64BIT_V4);
79 trace_sdhci_capareg("64-bit system bus (v4)", val);
80 msk = FIELD_DP64(msk, SDHC_CAPAB, BUS64BIT_V4, 0);
81
82 val = FIELD_EX64(s->capareg, SDHC_CAPAB, UHS_II);
83 trace_sdhci_capareg("UHS-II", val);
84 msk = FIELD_DP64(msk, SDHC_CAPAB, UHS_II, 0);
85
86 val = FIELD_EX64(s->capareg, SDHC_CAPAB, ADMA3);
87 trace_sdhci_capareg("ADMA3", val);
88 msk = FIELD_DP64(msk, SDHC_CAPAB, ADMA3, 0);
89
90 /* fallthrough */
4d67852d
PMD		 91 case 3:
92 val = FIELD_EX64(s->capareg, SDHC_CAPAB, ASYNC_INT);
93 trace_sdhci_capareg("async interrupt", val);
94 msk = FIELD_DP64(msk, SDHC_CAPAB, ASYNC_INT, 0);
95
96 val = FIELD_EX64(s->capareg, SDHC_CAPAB, SLOT_TYPE);
97 if (val) {
98 error_setg(errp, "slot-type not supported");
99 return;
100 }
101 trace_sdhci_capareg("slot type", val);
102 msk = FIELD_DP64(msk, SDHC_CAPAB, SLOT_TYPE, 0);
103
104 if (val != 2) {
105 val = FIELD_EX64(s->capareg, SDHC_CAPAB, EMBEDDED_8BIT);
106 trace_sdhci_capareg("8-bit bus", val);
107 }
108 msk = FIELD_DP64(msk, SDHC_CAPAB, EMBEDDED_8BIT, 0);
109
110 val = FIELD_EX64(s->capareg, SDHC_CAPAB, BUS_SPEED);
111 trace_sdhci_capareg("bus speed mask", val);
112 msk = FIELD_DP64(msk, SDHC_CAPAB, BUS_SPEED, 0);
113
114 val = FIELD_EX64(s->capareg, SDHC_CAPAB, DRIVER_STRENGTH);
115 trace_sdhci_capareg("driver strength mask", val);
116 msk = FIELD_DP64(msk, SDHC_CAPAB, DRIVER_STRENGTH, 0);
117
118 val = FIELD_EX64(s->capareg, SDHC_CAPAB, TIMER_RETUNING);
119 trace_sdhci_capareg("timer re-tuning", val);
120 msk = FIELD_DP64(msk, SDHC_CAPAB, TIMER_RETUNING, 0);
121
122 val = FIELD_EX64(s->capareg, SDHC_CAPAB, SDR50_TUNING);
123 trace_sdhci_capareg("use SDR50 tuning", val);
124 msk = FIELD_DP64(msk, SDHC_CAPAB, SDR50_TUNING, 0);
125
126 val = FIELD_EX64(s->capareg, SDHC_CAPAB, RETUNING_MODE);
127 trace_sdhci_capareg("re-tuning mode", val);
128 msk = FIELD_DP64(msk, SDHC_CAPAB, RETUNING_MODE, 0);
129
130 val = FIELD_EX64(s->capareg, SDHC_CAPAB, CLOCK_MULT);
131 trace_sdhci_capareg("clock multiplier", val);
132 msk = FIELD_DP64(msk, SDHC_CAPAB, CLOCK_MULT, 0);
133
134 /* fallthrough */
6ff37c3d 135 case 2: /* default version */
0540fba9
PMD		 136 val = FIELD_EX64(s->capareg, SDHC_CAPAB, ADMA2);
137 trace_sdhci_capareg("ADMA2", val);
138 msk = FIELD_DP64(msk, SDHC_CAPAB, ADMA2, 0);
139
140 val = FIELD_EX64(s->capareg, SDHC_CAPAB, ADMA1);
141 trace_sdhci_capareg("ADMA1", val);
142 msk = FIELD_DP64(msk, SDHC_CAPAB, ADMA1, 0);
143
144 val = FIELD_EX64(s->capareg, SDHC_CAPAB, BUS64BIT);
1e23b63f 145 trace_sdhci_capareg("64-bit system bus (v3)", val);
0540fba9 146 msk = FIELD_DP64(msk, SDHC_CAPAB, BUS64BIT, 0);
6ff37c3d
PMD		 147
148 /* fallthrough */
149 case 1:
150 y = FIELD_EX64(s->capareg, SDHC_CAPAB, TOUNIT);
151 msk = FIELD_DP64(msk, SDHC_CAPAB, TOUNIT, 0);
152
153 val = FIELD_EX64(s->capareg, SDHC_CAPAB, TOCLKFREQ);
154 trace_sdhci_capareg(y ? "timeout (MHz)" : "Timeout (KHz)", val);
155 if (sdhci_check_capab_freq_range(s, "timeout", val, errp)) {
156 return;
157 }
158 msk = FIELD_DP64(msk, SDHC_CAPAB, TOCLKFREQ, 0);
159
160 val = FIELD_EX64(s->capareg, SDHC_CAPAB, BASECLKFREQ);
161 trace_sdhci_capareg(y ? "base (MHz)" : "Base (KHz)", val);
162 if (sdhci_check_capab_freq_range(s, "base", val, errp)) {
163 return;
164 }
165 msk = FIELD_DP64(msk, SDHC_CAPAB, BASECLKFREQ, 0);
166
167 val = FIELD_EX64(s->capareg, SDHC_CAPAB, MAXBLOCKLENGTH);
168 if (val >= 3) {
169 error_setg(errp, "block size can be 512, 1024 or 2048 only");
170 return;
171 }
172 trace_sdhci_capareg("max block length", sdhci_get_fifolen(s));
173 msk = FIELD_DP64(msk, SDHC_CAPAB, MAXBLOCKLENGTH, 0);
174
175 val = FIELD_EX64(s->capareg, SDHC_CAPAB, HIGHSPEED);
176 trace_sdhci_capareg("high speed", val);
177 msk = FIELD_DP64(msk, SDHC_CAPAB, HIGHSPEED, 0);
178
179 val = FIELD_EX64(s->capareg, SDHC_CAPAB, SDMA);
180 trace_sdhci_capareg("SDMA", val);
181 msk = FIELD_DP64(msk, SDHC_CAPAB, SDMA, 0);
182
183 val = FIELD_EX64(s->capareg, SDHC_CAPAB, SUSPRESUME);
184 trace_sdhci_capareg("suspend/resume", val);
185 msk = FIELD_DP64(msk, SDHC_CAPAB, SUSPRESUME, 0);
186
187 val = FIELD_EX64(s->capareg, SDHC_CAPAB, V33);
188 trace_sdhci_capareg("3.3v", val);
189 msk = FIELD_DP64(msk, SDHC_CAPAB, V33, 0);
190
191 val = FIELD_EX64(s->capareg, SDHC_CAPAB, V30);
192 trace_sdhci_capareg("3.0v", val);
193 msk = FIELD_DP64(msk, SDHC_CAPAB, V30, 0);
194
195 val = FIELD_EX64(s->capareg, SDHC_CAPAB, V18);
196 trace_sdhci_capareg("1.8v", val);
197 msk = FIELD_DP64(msk, SDHC_CAPAB, V18, 0);
198 break;
199
200 default:
201 error_setg(errp, "Unsupported spec version: %u", s->sd_spec_version);
202 }
203 if (msk) {
204 qemu_log_mask(LOG_UNIMP,
205 "SDHCI: unknown CAPAB mask: 0x%016" PRIx64 "\n", msk);
206 }
207}
208
d7dfca08
IM		 209static uint8_t sdhci_slotint(SDHCIState *s)
210{
211 return (s->norintsts & s->norintsigen) || (s->errintsts & s->errintsigen) ||
212 ((s->norintsts & SDHC_NIS_INSERT) && (s->wakcon & SDHC_WKUP_ON_INS)) ||
213 ((s->norintsts & SDHC_NIS_REMOVE) && (s->wakcon & SDHC_WKUP_ON_RMV));
214}
215
216static inline void sdhci_update_irq(SDHCIState *s)
217{
218 qemu_set_irq(s->irq, sdhci_slotint(s));
219}
220
221static void sdhci_raise_insertion_irq(void *opaque)
222{
223 SDHCIState *s = (SDHCIState *)opaque;
224
225 if (s->norintsts & SDHC_NIS_REMOVE) {
bc72ad67
AB		 226 timer_mod(s->insert_timer,
227 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + SDHC_INSERTION_DELAY);
d7dfca08
IM		 228 } else {
229 s->prnsts = 0x1ff0000;
230 if (s->norintstsen & SDHC_NISEN_INSERT) {
231 s->norintsts |= SDHC_NIS_INSERT;
232 }
233 sdhci_update_irq(s);
234 }
235}
236
40bbc194 237static void sdhci_set_inserted(DeviceState *dev, bool level)
d7dfca08 238{
40bbc194 239 SDHCIState *s = (SDHCIState *)dev;
d7dfca08 240
8be487d8 241 trace_sdhci_set_inserted(level ? "insert" : "eject");
d7dfca08
IM		 242 if ((s->norintsts & SDHC_NIS_REMOVE) && level) {
243 /* Give target some time to notice card ejection */
bc72ad67
AB		 244 timer_mod(s->insert_timer,
245 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + SDHC_INSERTION_DELAY);
d7dfca08
IM		 246 } else {
247 if (level) {
248 s->prnsts = 0x1ff0000;
249 if (s->norintstsen & SDHC_NISEN_INSERT) {
250 s->norintsts |= SDHC_NIS_INSERT;
251 }
252 } else {
253 s->prnsts = 0x1fa0000;
254 s->pwrcon &= ~SDHC_POWER_ON;
255 s->clkcon &= ~SDHC_CLOCK_SDCLK_EN;
256 if (s->norintstsen & SDHC_NISEN_REMOVE) {
257 s->norintsts |= SDHC_NIS_REMOVE;
258 }
259 }
260 sdhci_update_irq(s);
261 }
262}
263
40bbc194 264static void sdhci_set_readonly(DeviceState *dev, bool level)
d7dfca08 265{
40bbc194 266 SDHCIState *s = (SDHCIState *)dev;
d7dfca08
IM		 267
268 if (level) {
269 s->prnsts &= ~SDHC_WRITE_PROTECT;
270 } else {
271 /* Write enabled */
272 s->prnsts |= SDHC_WRITE_PROTECT;
273 }
274}
275
276static void sdhci_reset(SDHCIState *s)
277{
40bbc194
PM		 278 DeviceState *dev = DEVICE(s);
279
bc72ad67
AB		 280 timer_del(s->insert_timer);
281 timer_del(s->transfer_timer);
aceb5b06
PMD		 282
283 /* Set all registers to 0. Capabilities/Version registers are not cleared
d7dfca08
IM		 284 * and assumed to always preserve their value, given to them during
285 * initialization */
286 memset(&s->sdmasysad, 0, (uintptr_t)&s->capareg - (uintptr_t)&s->sdmasysad);
287
5c1bc9a2
AB		 288 /* Reset other state based on current card insertion/readonly status */
289 sdhci_set_inserted(dev, sdbus_get_inserted(&s->sdbus));
290 sdhci_set_readonly(dev, sdbus_get_readonly(&s->sdbus));
40bbc194 291
d7dfca08
IM		 292 s->data_count = 0;
293 s->stopped_state = sdhc_not_stopped;
0a7ac9f9 294 s->pending_insert_state = false;
d7dfca08
IM		 295}
296
8b41c305
PM		 297static void sdhci_poweron_reset(DeviceState *dev)
298{
299 /* QOM (ie power-on) reset. This is identical to reset
300 * commanded via device register apart from handling of the
301 * 'pending insert on powerup' quirk.
302 */
303 SDHCIState *s = (SDHCIState *)dev;
304
305 sdhci_reset(s);
306
307 if (s->pending_insert_quirk) {
308 s->pending_insert_state = true;
309 }
310}
311
d368ba43 312static void sdhci_data_transfer(void *opaque);
d7dfca08
IM		 313
314static void sdhci_send_command(SDHCIState *s)
315{
316 SDRequest request;
317 uint8_t response[16];
318 int rlen;
319
320 s->errintsts = 0;
321 s->acmd12errsts = 0;
322 request.cmd = s->cmdreg >> 8;
323 request.arg = s->argument;
8be487d8
PMD		 324
325 trace_sdhci_send_command(request.cmd, request.arg);
40bbc194 326 rlen = sdbus_do_command(&s->sdbus, &request, response);
d7dfca08
IM		 327
328 if (s->cmdreg & SDHC_CMD_RESPONSE) {
329 if (rlen == 4) {
b3141c06 330 s->rspreg[0] = ldl_be_p(response);
d7dfca08 331 s->rspreg[1] = s->rspreg[2] = s->rspreg[3] = 0;
8be487d8 332 trace_sdhci_response4(s->rspreg[0]);
d7dfca08 333 } else if (rlen == 16) {
b3141c06
PMD		 334 s->rspreg[0] = ldl_be_p(&response[11]);
335 s->rspreg[1] = ldl_be_p(&response[7]);
336 s->rspreg[2] = ldl_be_p(&response[3]);
d7dfca08
IM		 337 s->rspreg[3] = (response[0] << 16) | (response[1] << 8) |
338 response[2];
8be487d8
PMD		 339 trace_sdhci_response16(s->rspreg[3], s->rspreg[2],
340 s->rspreg[1], s->rspreg[0]);
d7dfca08 341 } else {
8be487d8 342 trace_sdhci_error("timeout waiting for command response");
d7dfca08
IM		 343 if (s->errintstsen & SDHC_EISEN_CMDTIMEOUT) {
344 s->errintsts |= SDHC_EIS_CMDTIMEOUT;
345 s->norintsts |= SDHC_NIS_ERR;
346 }
347 }
348
fd1e5c81
AS		 349 if (!(s->quirks & SDHCI_QUIRK_NO_BUSY_IRQ) &&
350 (s->norintstsen & SDHC_NISEN_TRSCMP) &&
d7dfca08
IM		 351 (s->cmdreg & SDHC_CMD_RESPONSE) == SDHC_CMD_RSP_WITH_BUSY) {
352 s->norintsts |= SDHC_NIS_TRSCMP;
353 }
d7dfca08
IM		 354 }
355
356 if (s->norintstsen & SDHC_NISEN_CMDCMP) {
357 s->norintsts |= SDHC_NIS_CMDCMP;
358 }
359
360 sdhci_update_irq(s);
361
362 if (s->blksize && (s->cmdreg & SDHC_CMD_DATA_PRESENT)) {
656f416c 363 s->data_count = 0;
d368ba43 364 sdhci_data_transfer(s);
d7dfca08
IM		 365 }
366}
367
368static void sdhci_end_transfer(SDHCIState *s)
369{
370 /* Automatically send CMD12 to stop transfer if AutoCMD12 enabled */
371 if ((s->trnmod & SDHC_TRNS_ACMD12) != 0) {
372 SDRequest request;
373 uint8_t response[16];
374
375 request.cmd = 0x0C;
376 request.arg = 0;
8be487d8 377 trace_sdhci_end_transfer(request.cmd, request.arg);
40bbc194 378 sdbus_do_command(&s->sdbus, &request, response);
d7dfca08 379 /* Auto CMD12 response goes to the upper Response register */
b3141c06 380 s->rspreg[3] = ldl_be_p(response);
d7dfca08
IM		 381 }
382
383 s->prnsts &= ~(SDHC_DOING_READ | SDHC_DOING_WRITE |
384 SDHC_DAT_LINE_ACTIVE | SDHC_DATA_INHIBIT |
385 SDHC_SPACE_AVAILABLE | SDHC_DATA_AVAILABLE);
386
387 if (s->norintstsen & SDHC_NISEN_TRSCMP) {
388 s->norintsts |= SDHC_NIS_TRSCMP;
389 }
390
391 sdhci_update_irq(s);
392}
393
394/*
395 * Programmed i/o data transfer
396 */
d23b6caa 397#define BLOCK_SIZE_MASK (4 * KiB - 1)
d7dfca08
IM		 398
399/* Fill host controller's read buffer with BLKSIZE bytes of data from card */
400static void sdhci_read_block_from_card(SDHCIState *s)
401{
ea55a221 402 const uint16_t blk_size = s->blksize & BLOCK_SIZE_MASK;
d7dfca08
IM		 403
404 if ((s->trnmod & SDHC_TRNS_MULTI) &&
405 (s->trnmod & SDHC_TRNS_BLK_CNT_EN) && (s->blkcnt == 0)) {
406 return;
407 }
408
618e0be1
PMD		 409 if (!FIELD_EX32(s->hostctl2, SDHC_HOSTCTL2, EXECUTE_TUNING)) {
410 /* Device is not in tuning */
411 sdbus_read_data(&s->sdbus, s->fifo_buffer, blk_size);
ea55a221
PMD		 412 }
413
414 if (FIELD_EX32(s->hostctl2, SDHC_HOSTCTL2, EXECUTE_TUNING)) {
08022a91 415 /* Device is in tuning */
ea55a221
PMD		 416 s->hostctl2 &= ~R_SDHC_HOSTCTL2_EXECUTE_TUNING_MASK;
417 s->hostctl2 |= R_SDHC_HOSTCTL2_SAMPLING_CLKSEL_MASK;
418 s->prnsts &= ~(SDHC_DAT_LINE_ACTIVE | SDHC_DOING_READ |
419 SDHC_DATA_INHIBIT);
420 goto read_done;
d7dfca08
IM		 421 }
422
423 /* New data now available for READ through Buffer Port Register */
424 s->prnsts |= SDHC_DATA_AVAILABLE;
425 if (s->norintstsen & SDHC_NISEN_RBUFRDY) {
426 s->norintsts |= SDHC_NIS_RBUFRDY;
427 }
428
429 /* Clear DAT line active status if that was the last block */
430 if ((s->trnmod & SDHC_TRNS_MULTI) == 0 ||
431 ((s->trnmod & SDHC_TRNS_MULTI) && s->blkcnt == 1)) {
432 s->prnsts &= ~SDHC_DAT_LINE_ACTIVE;
433 }
434
435 /* If stop at block gap request was set and it's not the last block of
436 * data - generate Block Event interrupt */
437 if (s->stopped_state == sdhc_gap_read && (s->trnmod & SDHC_TRNS_MULTI) &&
438 s->blkcnt != 1) {
439 s->prnsts &= ~SDHC_DAT_LINE_ACTIVE;
440 if (s->norintstsen & SDHC_EISEN_BLKGAP) {
441 s->norintsts |= SDHC_EIS_BLKGAP;
442 }
443 }
444
ea55a221 445read_done:
d7dfca08
IM		 446 sdhci_update_irq(s);
447}
448
449/* Read @size byte of data from host controller @s BUFFER DATA PORT register */
450static uint32_t sdhci_read_dataport(SDHCIState *s, unsigned size)
451{
452 uint32_t value = 0;
453 int i;
454
455 /* first check that a valid data exists in host controller input buffer */
456 if ((s->prnsts & SDHC_DATA_AVAILABLE) == 0) {
8be487d8 457 trace_sdhci_error("read from empty buffer");
d7dfca08
IM		 458 return 0;
459 }
460
461 for (i = 0; i < size; i++) {
462 value |= s->fifo_buffer[s->data_count] << i * 8;
463 s->data_count++;
464 /* check if we've read all valid data (blksize bytes) from buffer */
bf8ec38e 465 if ((s->data_count) >= (s->blksize & BLOCK_SIZE_MASK)) {
8be487d8 466 trace_sdhci_read_dataport(s->data_count);
d7dfca08
IM		 467 s->prnsts &= ~SDHC_DATA_AVAILABLE; /* no more data in a buffer */
468 s->data_count = 0; /* next buff read must start at position [0] */
469
470 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) {
471 s->blkcnt--;
472 }
473
474 /* if that was the last block of data */
475 if ((s->trnmod & SDHC_TRNS_MULTI) == 0 ||
476 ((s->trnmod & SDHC_TRNS_BLK_CNT_EN) && (s->blkcnt == 0)) ||
477 /* stop at gap request */
478 (s->stopped_state == sdhc_gap_read &&
479 !(s->prnsts & SDHC_DAT_LINE_ACTIVE))) {
d368ba43 480 sdhci_end_transfer(s);
d7dfca08 481 } else { /* if there are more data, read next block from card */
d368ba43 482 sdhci_read_block_from_card(s);
d7dfca08
IM		 483 }
484 break;
485 }
486 }
487
488 return value;
489}
490
491/* Write data from host controller FIFO to card */
492static void sdhci_write_block_to_card(SDHCIState *s)
493{
d7dfca08
IM		 494 if (s->prnsts & SDHC_SPACE_AVAILABLE) {
495 if (s->norintstsen & SDHC_NISEN_WBUFRDY) {
496 s->norintsts |= SDHC_NIS_WBUFRDY;
497 }
498 sdhci_update_irq(s);
499 return;
500 }
501
502 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) {
503 if (s->blkcnt == 0) {
504 return;
505 } else {
506 s->blkcnt--;
507 }
508 }
509
62a21be6 510 sdbus_write_data(&s->sdbus, s->fifo_buffer, s->blksize & BLOCK_SIZE_MASK);
d7dfca08
IM		 511
512 /* Next data can be written through BUFFER DATORT register */
513 s->prnsts |= SDHC_SPACE_AVAILABLE;
d7dfca08
IM		 514
515 /* Finish transfer if that was the last block of data */
516 if ((s->trnmod & SDHC_TRNS_MULTI) == 0 ||
517 ((s->trnmod & SDHC_TRNS_MULTI) &&
518 (s->trnmod & SDHC_TRNS_BLK_CNT_EN) && (s->blkcnt == 0))) {
d368ba43 519 sdhci_end_transfer(s);
dcdb4cd8
PC		 520 } else if (s->norintstsen & SDHC_NISEN_WBUFRDY) {
521 s->norintsts |= SDHC_NIS_WBUFRDY;
d7dfca08
IM		 522 }
523
524 /* Generate Block Gap Event if requested and if not the last block */
525 if (s->stopped_state == sdhc_gap_write && (s->trnmod & SDHC_TRNS_MULTI) &&
526 s->blkcnt > 0) {
527 s->prnsts &= ~SDHC_DOING_WRITE;
528 if (s->norintstsen & SDHC_EISEN_BLKGAP) {
529 s->norintsts |= SDHC_EIS_BLKGAP;
530 }
d368ba43 531 sdhci_end_transfer(s);
d7dfca08
IM		 532 }
533
534 sdhci_update_irq(s);
535}
536
537/* Write @size bytes of @value data to host controller @s Buffer Data Port
538 * register */
539static void sdhci_write_dataport(SDHCIState *s, uint32_t value, unsigned size)
540{
541 unsigned i;
542
543 /* Check that there is free space left in a buffer */
544 if (!(s->prnsts & SDHC_SPACE_AVAILABLE)) {
8be487d8 545 trace_sdhci_error("Can't write to data buffer: buffer full");
d7dfca08
IM		 546 return;
547 }
548
549 for (i = 0; i < size; i++) {
550 s->fifo_buffer[s->data_count] = value & 0xFF;
551 s->data_count++;
552 value >>= 8;
bf8ec38e 553 if (s->data_count >= (s->blksize & BLOCK_SIZE_MASK)) {
8be487d8 554 trace_sdhci_write_dataport(s->data_count);
d7dfca08
IM		 555 s->data_count = 0;
556 s->prnsts &= ~SDHC_SPACE_AVAILABLE;
557 if (s->prnsts & SDHC_DOING_WRITE) {
d368ba43 558 sdhci_write_block_to_card(s);
d7dfca08
IM		 559 }
560 }
561 }
562}
563
564/*
565 * Single DMA data transfer
566 */
567
568/* Multi block SDMA transfer */
569static void sdhci_sdma_transfer_multi_blocks(SDHCIState *s)
570{
571 bool page_aligned = false;
618e0be1 572 unsigned int begin;
bf8ec38e
PMD		 573 const uint16_t block_size = s->blksize & BLOCK_SIZE_MASK;
574 uint32_t boundary_chk = 1 << (((s->blksize & ~BLOCK_SIZE_MASK) >> 12) + 12);
d7dfca08
IM		 575 uint32_t boundary_count = boundary_chk - (s->sdmasysad % boundary_chk);
576
6e86d903
PP		 577 if (!(s->trnmod & SDHC_TRNS_BLK_CNT_EN) || !s->blkcnt) {
578 qemu_log_mask(LOG_UNIMP, "infinite transfer is not supported\n");
579 return;
580 }
581
d7dfca08
IM		 582 /* XXX: Some sd/mmc drivers (for example, u-boot-slp) do not account for
583 * possible stop at page boundary if initial address is not page aligned,
584 * allow them to work properly */
585 if ((s->sdmasysad % boundary_chk) == 0) {
586 page_aligned = true;
587 }
588
589 if (s->trnmod & SDHC_TRNS_READ) {
590 s->prnsts |= SDHC_DOING_READ | SDHC_DATA_INHIBIT |
591 SDHC_DAT_LINE_ACTIVE;
592 while (s->blkcnt) {
593 if (s->data_count == 0) {
618e0be1 594 sdbus_read_data(&s->sdbus, s->fifo_buffer, block_size);
d7dfca08
IM		 595 }
596 begin = s->data_count;
597 if (((boundary_count + begin) < block_size) && page_aligned) {
598 s->data_count = boundary_count + begin;
599 boundary_count = 0;
600 } else {
601 s->data_count = block_size;
602 boundary_count -= block_size - begin;
603 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) {
604 s->blkcnt--;
605 }
606 }
dd55c485 607 dma_memory_write(s->dma_as, s->sdmasysad,
d7dfca08
IM		 608 &s->fifo_buffer[begin], s->data_count - begin);
609 s->sdmasysad += s->data_count - begin;
610 if (s->data_count == block_size) {
611 s->data_count = 0;
612 }
613 if (page_aligned && boundary_count == 0) {
614 break;
615 }
616 }
617 } else {
618 s->prnsts |= SDHC_DOING_WRITE | SDHC_DATA_INHIBIT |
619 SDHC_DAT_LINE_ACTIVE;
620 while (s->blkcnt) {
621 begin = s->data_count;
622 if (((boundary_count + begin) < block_size) && page_aligned) {
623 s->data_count = boundary_count + begin;
624 boundary_count = 0;
625 } else {
626 s->data_count = block_size;
627 boundary_count -= block_size - begin;
628 }
dd55c485 629 dma_memory_read(s->dma_as, s->sdmasysad,
42922105 630 &s->fifo_buffer[begin], s->data_count - begin);
d7dfca08
IM		 631 s->sdmasysad += s->data_count - begin;
632 if (s->data_count == block_size) {
62a21be6 633 sdbus_write_data(&s->sdbus, s->fifo_buffer, block_size);
d7dfca08
IM		 634 s->data_count = 0;
635 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) {
636 s->blkcnt--;
637 }
638 }
639 if (page_aligned && boundary_count == 0) {
640 break;
641 }
642 }
643 }
644
645 if (s->blkcnt == 0) {
d368ba43 646 sdhci_end_transfer(s);
d7dfca08
IM		 647 } else {
648 if (s->norintstsen & SDHC_NISEN_DMA) {
649 s->norintsts |= SDHC_NIS_DMA;
650 }
651 sdhci_update_irq(s);
652 }
653}
654
655/* single block SDMA transfer */
d7dfca08
IM		 656static void sdhci_sdma_transfer_single_block(SDHCIState *s)
657{
bf8ec38e 658 uint32_t datacnt = s->blksize & BLOCK_SIZE_MASK;
d7dfca08
IM		 659
660 if (s->trnmod & SDHC_TRNS_READ) {
618e0be1 661 sdbus_read_data(&s->sdbus, s->fifo_buffer, datacnt);
dd55c485 662 dma_memory_write(s->dma_as, s->sdmasysad, s->fifo_buffer, datacnt);
d7dfca08 663 } else {
dd55c485 664 dma_memory_read(s->dma_as, s->sdmasysad, s->fifo_buffer, datacnt);
62a21be6 665 sdbus_write_data(&s->sdbus, s->fifo_buffer, datacnt);
d7dfca08 666 }
241999bf 667 s->blkcnt--;
d7dfca08 668
d368ba43 669 sdhci_end_transfer(s);
d7dfca08
IM		 670}
671
672typedef struct ADMADescr {
673 hwaddr addr;
674 uint16_t length;
675 uint8_t attr;
676 uint8_t incr;
677} ADMADescr;
678
679static void get_adma_description(SDHCIState *s, ADMADescr *dscr)
680{
681 uint32_t adma1 = 0;
682 uint64_t adma2 = 0;
683 hwaddr entry_addr = (hwaddr)s->admasysaddr;
06c5120b 684 switch (SDHC_DMA_TYPE(s->hostctl1)) {
d7dfca08 685 case SDHC_CTRL_ADMA2_32:
18610bfd 686 dma_memory_read(s->dma_as, entry_addr, &adma2, sizeof(adma2));
d7dfca08
IM		 687 adma2 = le64_to_cpu(adma2);
688 /* The spec does not specify endianness of descriptor table.
689 * We currently assume that it is LE.
690 */
691 dscr->addr = (hwaddr)extract64(adma2, 32, 32) & ~0x3ull;
692 dscr->length = (uint16_t)extract64(adma2, 16, 16);
693 dscr->attr = (uint8_t)extract64(adma2, 0, 7);
694 dscr->incr = 8;
695 break;
696 case SDHC_CTRL_ADMA1_32:
18610bfd 697 dma_memory_read(s->dma_as, entry_addr, &adma1, sizeof(adma1));
d7dfca08
IM		 698 adma1 = le32_to_cpu(adma1);
699 dscr->addr = (hwaddr)(adma1 & 0xFFFFF000);
700 dscr->attr = (uint8_t)extract32(adma1, 0, 7);
701 dscr->incr = 4;
702 if ((dscr->attr & SDHC_ADMA_ATTR_ACT_MASK) == SDHC_ADMA_ATTR_SET_LEN) {
703 dscr->length = (uint16_t)extract32(adma1, 12, 16);
704 } else {
4c8f9735 705 dscr->length = 4 * KiB;
d7dfca08
IM		 706 }
707 break;
708 case SDHC_CTRL_ADMA2_64:
18610bfd
PMD		 709 dma_memory_read(s->dma_as, entry_addr, &dscr->attr, 1);
710 dma_memory_read(s->dma_as, entry_addr + 2, &dscr->length, 2);
d7dfca08 711 dscr->length = le16_to_cpu(dscr->length);
18610bfd 712 dma_memory_read(s->dma_as, entry_addr + 4, &dscr->addr, 8);
04654b5a
SPB		 713 dscr->addr = le64_to_cpu(dscr->addr);
714 dscr->attr &= (uint8_t) ~0xC0;
d7dfca08
IM		 715 dscr->incr = 12;
716 break;
717 }
718}
719
720/* Advanced DMA data transfer */
721
722static void sdhci_do_adma(SDHCIState *s)
723{
618e0be1 724 unsigned int begin, length;
bf8ec38e 725 const uint16_t block_size = s->blksize & BLOCK_SIZE_MASK;
8be487d8 726 ADMADescr dscr = {};
d7dfca08
IM		 727 int i;
728
729 for (i = 0; i < SDHC_ADMA_DESCS_PER_DELAY; ++i) {
730 s->admaerr &= ~SDHC_ADMAERR_LENGTH_MISMATCH;
731
732 get_adma_description(s, &dscr);
8be487d8 733 trace_sdhci_adma_loop(dscr.addr, dscr.length, dscr.attr);
d7dfca08
IM		 734
735 if ((dscr.attr & SDHC_ADMA_ATTR_VALID) == 0) {
736 /* Indicate that error occurred in ST_FDS state */
737 s->admaerr &= ~SDHC_ADMAERR_STATE_MASK;
738 s->admaerr |= SDHC_ADMAERR_STATE_ST_FDS;
739
740 /* Generate ADMA error interrupt */
741 if (s->errintstsen & SDHC_EISEN_ADMAERR) {
742 s->errintsts |= SDHC_EIS_ADMAERR;
743 s->norintsts |= SDHC_NIS_ERR;
744 }
745
746 sdhci_update_irq(s);
747 return;
748 }
749
4c8f9735 750 length = dscr.length ? dscr.length : 64 * KiB;
d7dfca08
IM		 751
752 switch (dscr.attr & SDHC_ADMA_ATTR_ACT_MASK) {
753 case SDHC_ADMA_ATTR_ACT_TRAN: /* data transfer */
754
755 if (s->trnmod & SDHC_TRNS_READ) {
756 while (length) {
757 if (s->data_count == 0) {
618e0be1 758 sdbus_read_data(&s->sdbus, s->fifo_buffer, block_size);
d7dfca08
IM		 759 }
760 begin = s->data_count;
761 if ((length + begin) < block_size) {
762 s->data_count = length + begin;
763 length = 0;
764 } else {
765 s->data_count = block_size;
766 length -= block_size - begin;
767 }
dd55c485 768 dma_memory_write(s->dma_as, dscr.addr,
d7dfca08
IM		 769 &s->fifo_buffer[begin],
770 s->data_count - begin);
771 dscr.addr += s->data_count - begin;
772 if (s->data_count == block_size) {
773 s->data_count = 0;
774 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) {
775 s->blkcnt--;
776 if (s->blkcnt == 0) {
777 break;
778 }
779 }
780 }
781 }
782 } else {
783 while (length) {
784 begin = s->data_count;
785 if ((length + begin) < block_size) {
786 s->data_count = length + begin;
787 length = 0;
788 } else {
789 s->data_count = block_size;
790 length -= block_size - begin;
791 }
dd55c485 792 dma_memory_read(s->dma_as, dscr.addr,
9db11cef
PC		 793 &s->fifo_buffer[begin],
794 s->data_count - begin);
d7dfca08
IM		 795 dscr.addr += s->data_count - begin;
796 if (s->data_count == block_size) {
62a21be6 797 sdbus_write_data(&s->sdbus, s->fifo_buffer, block_size);
d7dfca08
IM		 798 s->data_count = 0;
799 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) {
800 s->blkcnt--;
801 if (s->blkcnt == 0) {
802 break;
803 }
804 }
805 }
806 }
807 }
808 s->admasysaddr += dscr.incr;
809 break;
810 case SDHC_ADMA_ATTR_ACT_LINK: /* link to next descriptor table */
811 s->admasysaddr = dscr.addr;
8be487d8 812 trace_sdhci_adma("link", s->admasysaddr);
d7dfca08
IM		 813 break;
814 default:
815 s->admasysaddr += dscr.incr;
816 break;
817 }
818
1d32c26f 819 if (dscr.attr & SDHC_ADMA_ATTR_INT) {
8be487d8 820 trace_sdhci_adma("interrupt", s->admasysaddr);
1d32c26f
PC		 821 if (s->norintstsen & SDHC_NISEN_DMA) {
822 s->norintsts |= SDHC_NIS_DMA;
823 }
824
825 sdhci_update_irq(s);
826 }
827
d7dfca08
IM		 828 /* ADMA transfer terminates if blkcnt == 0 or by END attribute */
829 if (((s->trnmod & SDHC_TRNS_BLK_CNT_EN) &&
830 (s->blkcnt == 0)) || (dscr.attr & SDHC_ADMA_ATTR_END)) {
8be487d8 831 trace_sdhci_adma_transfer_completed();
d7dfca08
IM		 832 if (length || ((dscr.attr & SDHC_ADMA_ATTR_END) &&
833 (s->trnmod & SDHC_TRNS_BLK_CNT_EN) &&
834 s->blkcnt != 0)) {
8be487d8 835 trace_sdhci_error("SD/MMC host ADMA length mismatch");
d7dfca08
IM		 836 s->admaerr |= SDHC_ADMAERR_LENGTH_MISMATCH |
837 SDHC_ADMAERR_STATE_ST_TFR;
838 if (s->errintstsen & SDHC_EISEN_ADMAERR) {
8be487d8 839 trace_sdhci_error("Set ADMA error flag");
d7dfca08
IM		 840 s->errintsts |= SDHC_EIS_ADMAERR;
841 s->norintsts |= SDHC_NIS_ERR;
842 }
843
844 sdhci_update_irq(s);
845 }
d368ba43 846 sdhci_end_transfer(s);
d7dfca08
IM		 847 return;
848 }
849
d7dfca08
IM		 850 }
851
085d8134 852 /* we have unfinished business - reschedule to continue ADMA */
bc72ad67
AB		 853 timer_mod(s->transfer_timer,
854 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + SDHC_TRANSFER_DELAY);
d7dfca08
IM		 855}
856
857/* Perform data transfer according to controller configuration */
858
d368ba43 859static void sdhci_data_transfer(void *opaque)
d7dfca08 860{
d368ba43 861 SDHCIState *s = (SDHCIState *)opaque;
d7dfca08
IM		 862
863 if (s->trnmod & SDHC_TRNS_DMA) {
06c5120b 864 switch (SDHC_DMA_TYPE(s->hostctl1)) {
d7dfca08 865 case SDHC_CTRL_SDMA:
d7dfca08 866 if ((s->blkcnt == 1) || !(s->trnmod & SDHC_TRNS_MULTI)) {
d368ba43 867 sdhci_sdma_transfer_single_block(s);
d7dfca08 868 } else {
d368ba43 869 sdhci_sdma_transfer_multi_blocks(s);
d7dfca08
IM		 870 }
871
872 break;
873 case SDHC_CTRL_ADMA1_32:
0540fba9 874 if (!(s->capareg & R_SDHC_CAPAB_ADMA1_MASK)) {
8be487d8 875 trace_sdhci_error("ADMA1 not supported");
d7dfca08
IM		 876 break;
877 }
878
d368ba43 879 sdhci_do_adma(s);
d7dfca08
IM		 880 break;
881 case SDHC_CTRL_ADMA2_32:
0540fba9 882 if (!(s->capareg & R_SDHC_CAPAB_ADMA2_MASK)) {
8be487d8 883 trace_sdhci_error("ADMA2 not supported");
d7dfca08
IM		 884 break;
885 }
886
d368ba43 887 sdhci_do_adma(s);
d7dfca08
IM		 888 break;
889 case SDHC_CTRL_ADMA2_64:
0540fba9
PMD		 890 if (!(s->capareg & R_SDHC_CAPAB_ADMA2_MASK) ||
891 !(s->capareg & R_SDHC_CAPAB_BUS64BIT_MASK)) {
8be487d8 892 trace_sdhci_error("64 bit ADMA not supported");
d7dfca08
IM		 893 break;
894 }
895
d368ba43 896 sdhci_do_adma(s);
d7dfca08
IM		 897 break;
898 default:
8be487d8 899 trace_sdhci_error("Unsupported DMA type");
d7dfca08
IM		 900 break;
901 }
902 } else {
40bbc194 903 if ((s->trnmod & SDHC_TRNS_READ) && sdbus_data_ready(&s->sdbus)) {
d7dfca08
IM		 904 s->prnsts |= SDHC_DOING_READ | SDHC_DATA_INHIBIT |
905 SDHC_DAT_LINE_ACTIVE;
d368ba43 906 sdhci_read_block_from_card(s);
d7dfca08
IM		 907 } else {
908 s->prnsts |= SDHC_DOING_WRITE | SDHC_DAT_LINE_ACTIVE |
909 SDHC_SPACE_AVAILABLE | SDHC_DATA_INHIBIT;
d368ba43 910 sdhci_write_block_to_card(s);
d7dfca08
IM		 911 }
912 }
913}
914
915static bool sdhci_can_issue_command(SDHCIState *s)
916{
6890a695 917 if (!SDHC_CLOCK_IS_ON(s->clkcon) ||
d7dfca08
IM		 918 (((s->prnsts & SDHC_DATA_INHIBIT) || s->stopped_state) &&
919 ((s->cmdreg & SDHC_CMD_DATA_PRESENT) ||
920 ((s->cmdreg & SDHC_CMD_RESPONSE) == SDHC_CMD_RSP_WITH_BUSY &&
921 !(SDHC_COMMAND_TYPE(s->cmdreg) == SDHC_CMD_ABORT))))) {
922 return false;
923 }
924
925 return true;
926}
927
928/* The Buffer Data Port register must be accessed in sequential and
929 * continuous manner */
930static inline bool
931sdhci_buff_access_is_sequential(SDHCIState *s, unsigned byte_num)
932{
933 if ((s->data_count & 0x3) != byte_num) {
8be487d8
PMD		 934 trace_sdhci_error("Non-sequential access to Buffer Data Port register"
935 "is prohibited\n");
d7dfca08
IM		 936 return false;
937 }
938 return true;
939}
940
d368ba43 941static uint64_t sdhci_read(void *opaque, hwaddr offset, unsigned size)
d7dfca08 942{
d368ba43 943 SDHCIState *s = (SDHCIState *)opaque;
d7dfca08
IM		 944 uint32_t ret = 0;
945
946 switch (offset & ~0x3) {
947 case SDHC_SYSAD:
948 ret = s->sdmasysad;
949 break;
950 case SDHC_BLKSIZE:
951 ret = s->blksize | (s->blkcnt << 16);
952 break;
953 case SDHC_ARGUMENT:
954 ret = s->argument;
955 break;
956 case SDHC_TRNMOD:
957 ret = s->trnmod | (s->cmdreg << 16);
958 break;
959 case SDHC_RSPREG0 ... SDHC_RSPREG3:
960 ret = s->rspreg[((offset & ~0x3) - SDHC_RSPREG0) >> 2];
961 break;
962 case SDHC_BDATA:
963 if (sdhci_buff_access_is_sequential(s, offset - SDHC_BDATA)) {
d368ba43 964 ret = sdhci_read_dataport(s, size);
8be487d8 965 trace_sdhci_access("rd", size << 3, offset, "->", ret, ret);
d7dfca08
IM		 966 return ret;
967 }
968 break;
969 case SDHC_PRNSTS:
970 ret = s->prnsts;
da346922
PMD		 971 ret = FIELD_DP32(ret, SDHC_PRNSTS, DAT_LVL,
972 sdbus_get_dat_lines(&s->sdbus));
973 ret = FIELD_DP32(ret, SDHC_PRNSTS, CMD_LVL,
974 sdbus_get_cmd_line(&s->sdbus));
d7dfca08
IM		 975 break;
976 case SDHC_HOSTCTL:
06c5120b 977 ret = s->hostctl1 | (s->pwrcon << 8) | (s->blkgap << 16) |
d7dfca08
IM		 978 (s->wakcon << 24);
979 break;
980 case SDHC_CLKCON:
981 ret = s->clkcon | (s->timeoutcon << 16);
982 break;
983 case SDHC_NORINTSTS:
984 ret = s->norintsts | (s->errintsts << 16);
985 break;
986 case SDHC_NORINTSTSEN:
987 ret = s->norintstsen | (s->errintstsen << 16);
988 break;
989 case SDHC_NORINTSIGEN:
990 ret = s->norintsigen | (s->errintsigen << 16);
991 break;
992 case SDHC_ACMD12ERRSTS:
ea55a221 993 ret = s->acmd12errsts | (s->hostctl2 << 16);
d7dfca08 994 break;
cd209421 995 case SDHC_CAPAB:
5efc9016
PMD		 996 ret = (uint32_t)s->capareg;
997 break;
998 case SDHC_CAPAB + 4:
999 ret = (uint32_t)(s->capareg >> 32);
d7dfca08
IM		 1000 break;
1001 case SDHC_MAXCURR:
5efc9016
PMD		 1002 ret = (uint32_t)s->maxcurr;
1003 break;
1004 case SDHC_MAXCURR + 4:
1005 ret = (uint32_t)(s->maxcurr >> 32);
d7dfca08
IM		 1006 break;
1007 case SDHC_ADMAERR:
1008 ret = s->admaerr;
1009 break;
1010 case SDHC_ADMASYSADDR:
1011 ret = (uint32_t)s->admasysaddr;
1012 break;
1013 case SDHC_ADMASYSADDR + 4:
1014 ret = (uint32_t)(s->admasysaddr >> 32);
1015 break;
1016 case SDHC_SLOT_INT_STATUS:
aceb5b06 1017 ret = (s->version << 16) | sdhci_slotint(s);
d7dfca08
IM		 1018 break;
1019 default:
00b004b3
PMD		 1020 qemu_log_mask(LOG_UNIMP, "SDHC rd_%ub @0x%02" HWADDR_PRIx " "
1021 "not implemented\n", size, offset);
d7dfca08
IM		 1022 break;
1023 }
1024
1025 ret >>= (offset & 0x3) * 8;
1026 ret &= (1ULL << (size * 8)) - 1;
8be487d8 1027 trace_sdhci_access("rd", size << 3, offset, "->", ret, ret);
d7dfca08
IM		 1028 return ret;
1029}
1030
1031static inline void sdhci_blkgap_write(SDHCIState *s, uint8_t value)
1032{
1033 if ((value & SDHC_STOP_AT_GAP_REQ) && (s->blkgap & SDHC_STOP_AT_GAP_REQ)) {
1034 return;
1035 }
1036 s->blkgap = value & SDHC_STOP_AT_GAP_REQ;
1037
1038 if ((value & SDHC_CONTINUE_REQ) && s->stopped_state &&
1039 (s->blkgap & SDHC_STOP_AT_GAP_REQ) == 0) {
1040 if (s->stopped_state == sdhc_gap_read) {
1041 s->prnsts |= SDHC_DAT_LINE_ACTIVE | SDHC_DOING_READ;
d368ba43 1042 sdhci_read_block_from_card(s);
d7dfca08
IM		 1043 } else {
1044 s->prnsts |= SDHC_DAT_LINE_ACTIVE | SDHC_DOING_WRITE;
d368ba43 1045 sdhci_write_block_to_card(s);
d7dfca08
IM		 1046 }
1047 s->stopped_state = sdhc_not_stopped;
1048 } else if (!s->stopped_state && (value & SDHC_STOP_AT_GAP_REQ)) {
1049 if (s->prnsts & SDHC_DOING_READ) {
1050 s->stopped_state = sdhc_gap_read;
1051 } else if (s->prnsts & SDHC_DOING_WRITE) {
1052 s->stopped_state = sdhc_gap_write;
1053 }
1054 }
1055}
1056
1057static inline void sdhci_reset_write(SDHCIState *s, uint8_t value)
1058{
1059 switch (value) {
1060 case SDHC_RESET_ALL:
d368ba43 1061 sdhci_reset(s);
d7dfca08
IM		 1062 break;
1063 case SDHC_RESET_CMD:
1064 s->prnsts &= ~SDHC_CMD_INHIBIT;
1065 s->norintsts &= ~SDHC_NIS_CMDCMP;
1066 break;
1067 case SDHC_RESET_DATA:
1068 s->data_count = 0;
1069 s->prnsts &= ~(SDHC_SPACE_AVAILABLE | SDHC_DATA_AVAILABLE |
1070 SDHC_DOING_READ | SDHC_DOING_WRITE |
1071 SDHC_DATA_INHIBIT | SDHC_DAT_LINE_ACTIVE);
1072 s->blkgap &= ~(SDHC_STOP_AT_GAP_REQ | SDHC_CONTINUE_REQ);
1073 s->stopped_state = sdhc_not_stopped;
1074 s->norintsts &= ~(SDHC_NIS_WBUFRDY | SDHC_NIS_RBUFRDY |
1075 SDHC_NIS_DMA | SDHC_NIS_TRSCMP | SDHC_NIS_BLKGAP);
1076 break;
1077 }
1078}
1079
1080static void
d368ba43 1081sdhci_write(void *opaque, hwaddr offset, uint64_t val, unsigned size)
d7dfca08 1082{
d368ba43 1083 SDHCIState *s = (SDHCIState *)opaque;
d7dfca08
IM		 1084 unsigned shift = 8 * (offset & 0x3);
1085 uint32_t mask = ~(((1ULL << (size * 8)) - 1) << shift);
d368ba43 1086 uint32_t value = val;
d7dfca08
IM		 1087 value <<= shift;
1088
1089 switch (offset & ~0x3) {
1090 case SDHC_SYSAD:
1091 s->sdmasysad = (s->sdmasysad & mask) | value;
1092 MASKED_WRITE(s->sdmasysad, mask, value);
1093 /* Writing to last byte of sdmasysad might trigger transfer */
1094 if (!(mask & 0xFF000000) && TRANSFERRING_DATA(s->prnsts) && s->blkcnt &&
06c5120b 1095 s->blksize && SDHC_DMA_TYPE(s->hostctl1) == SDHC_CTRL_SDMA) {
45ba9f76
PP		 1096 if (s->trnmod & SDHC_TRNS_MULTI) {
1097 sdhci_sdma_transfer_multi_blocks(s);
1098 } else {
1099 sdhci_sdma_transfer_single_block(s);
1100 }
d7dfca08
IM		 1101 }
1102 break;
1103 case SDHC_BLKSIZE:
1104 if (!TRANSFERRING_DATA(s->prnsts)) {
1105 MASKED_WRITE(s->blksize, mask, value);
1106 MASKED_WRITE(s->blkcnt, mask >> 16, value >> 16);
1107 }
9201bb9a
AF		 1108
1109 /* Limit block size to the maximum buffer size */
1110 if (extract32(s->blksize, 0, 12) > s->buf_maxsz) {
78ee6bd0 1111 qemu_log_mask(LOG_GUEST_ERROR, "%s: Size 0x%x is larger than "
9201bb9a
AF		 1112 "the maximum buffer 0x%x", __func__, s->blksize,
1113 s->buf_maxsz);
1114
1115 s->blksize = deposit32(s->blksize, 0, 12, s->buf_maxsz);
1116 }
1117
d7dfca08
IM		 1118 break;
1119 case SDHC_ARGUMENT:
1120 MASKED_WRITE(s->argument, mask, value);
1121 break;
1122 case SDHC_TRNMOD:
1123 /* DMA can be enabled only if it is supported as indicated by
1124 * capabilities register */
6ff37c3d 1125 if (!(s->capareg & R_SDHC_CAPAB_SDMA_MASK)) {
d7dfca08
IM		 1126 value &= ~SDHC_TRNS_DMA;
1127 }
24bddf9d 1128 MASKED_WRITE(s->trnmod, mask, value & SDHC_TRNMOD_MASK);
d7dfca08
IM		 1129 MASKED_WRITE(s->cmdreg, mask >> 16, value >> 16);
1130
1131 /* Writing to the upper byte of CMDREG triggers SD command generation */
d368ba43 1132 if ((mask & 0xFF000000) || !sdhci_can_issue_command(s)) {
d7dfca08
IM		 1133 break;
1134 }
1135
d368ba43 1136 sdhci_send_command(s);
d7dfca08
IM		 1137 break;
1138 case SDHC_BDATA:
1139 if (sdhci_buff_access_is_sequential(s, offset - SDHC_BDATA)) {
d368ba43 1140 sdhci_write_dataport(s, value >> shift, size);
d7dfca08
IM		 1141 }
1142 break;
1143 case SDHC_HOSTCTL:
1144 if (!(mask & 0xFF0000)) {
1145 sdhci_blkgap_write(s, value >> 16);
1146 }
06c5120b 1147 MASKED_WRITE(s->hostctl1, mask, value);
d7dfca08
IM		 1148 MASKED_WRITE(s->pwrcon, mask >> 8, value >> 8);
1149 MASKED_WRITE(s->wakcon, mask >> 24, value >> 24);
1150 if (!(s->prnsts & SDHC_CARD_PRESENT) || ((s->pwrcon >> 1) & 0x7) < 5 ||
1151 !(s->capareg & (1 << (31 - ((s->pwrcon >> 1) & 0x7))))) {
1152 s->pwrcon &= ~SDHC_POWER_ON;
1153 }
1154 break;
1155 case SDHC_CLKCON:
1156 if (!(mask & 0xFF000000)) {
1157 sdhci_reset_write(s, value >> 24);
1158 }
1159 MASKED_WRITE(s->clkcon, mask, value);
1160 MASKED_WRITE(s->timeoutcon, mask >> 16, value >> 16);
1161 if (s->clkcon & SDHC_CLOCK_INT_EN) {
1162 s->clkcon |= SDHC_CLOCK_INT_STABLE;
1163 } else {
1164 s->clkcon &= ~SDHC_CLOCK_INT_STABLE;
1165 }
1166 break;
1167 case SDHC_NORINTSTS:
1168 if (s->norintstsen & SDHC_NISEN_CARDINT) {
1169 value &= ~SDHC_NIS_CARDINT;
1170 }
1171 s->norintsts &= mask | ~value;
1172 s->errintsts &= (mask >> 16) | ~(value >> 16);
1173 if (s->errintsts) {
1174 s->norintsts |= SDHC_NIS_ERR;
1175 } else {
1176 s->norintsts &= ~SDHC_NIS_ERR;
1177 }
1178 sdhci_update_irq(s);
1179 break;
1180 case SDHC_NORINTSTSEN:
1181 MASKED_WRITE(s->norintstsen, mask, value);
1182 MASKED_WRITE(s->errintstsen, mask >> 16, value >> 16);
1183 s->norintsts &= s->norintstsen;
1184 s->errintsts &= s->errintstsen;
1185 if (s->errintsts) {
1186 s->norintsts |= SDHC_NIS_ERR;
1187 } else {
1188 s->norintsts &= ~SDHC_NIS_ERR;
1189 }
0a7ac9f9
AB		 1190 /* Quirk for Raspberry Pi: pending card insert interrupt
1191 * appears when first enabled after power on */
1192 if ((s->norintstsen & SDHC_NISEN_INSERT) && s->pending_insert_state) {
1193 assert(s->pending_insert_quirk);
1194 s->norintsts |= SDHC_NIS_INSERT;
1195 s->pending_insert_state = false;
1196 }
d7dfca08
IM		 1197 sdhci_update_irq(s);
1198 break;
1199 case SDHC_NORINTSIGEN:
1200 MASKED_WRITE(s->norintsigen, mask, value);
1201 MASKED_WRITE(s->errintsigen, mask >> 16, value >> 16);
1202 sdhci_update_irq(s);
1203 break;
1204 case SDHC_ADMAERR:
1205 MASKED_WRITE(s->admaerr, mask, value);
1206 break;
1207 case SDHC_ADMASYSADDR:
1208 s->admasysaddr = (s->admasysaddr & (0xFFFFFFFF00000000ULL |
1209 (uint64_t)mask)) | (uint64_t)value;
1210 break;
1211 case SDHC_ADMASYSADDR + 4:
1212 s->admasysaddr = (s->admasysaddr & (0x00000000FFFFFFFFULL |
1213 ((uint64_t)mask << 32))) | ((uint64_t)value << 32);
1214 break;
1215 case SDHC_FEAER:
1216 s->acmd12errsts |= value;
1217 s->errintsts |= (value >> 16) & s->errintstsen;
1218 if (s->acmd12errsts) {
1219 s->errintsts |= SDHC_EIS_CMD12ERR;
1220 }
1221 if (s->errintsts) {
1222 s->norintsts |= SDHC_NIS_ERR;
1223 }
1224 sdhci_update_irq(s);
1225 break;
5d2c0464 1226 case SDHC_ACMD12ERRSTS:
0034ebe6
PMD		 1227 MASKED_WRITE(s->acmd12errsts, mask, value & UINT16_MAX);
1228 if (s->uhs_mode >= UHS_I) {
1229 MASKED_WRITE(s->hostctl2, mask >> 16, value >> 16);
1230
1231 if (FIELD_EX32(s->hostctl2, SDHC_HOSTCTL2, V18_ENA)) {
1232 sdbus_set_voltage(&s->sdbus, SD_VOLTAGE_1_8V);
1233 } else {
1234 sdbus_set_voltage(&s->sdbus, SD_VOLTAGE_3_3V);
1235 }
1236 }
5d2c0464 1237 break;
5efc9016
PMD		 1238
1239 case SDHC_CAPAB:
1240 case SDHC_CAPAB + 4:
1241 case SDHC_MAXCURR:
1242 case SDHC_MAXCURR + 4:
1243 qemu_log_mask(LOG_GUEST_ERROR, "SDHC wr_%ub @0x%02" HWADDR_PRIx
1244 " <- 0x%08x read-only\n", size, offset, value >> shift);
1245 break;
1246
d7dfca08 1247 default:
00b004b3
PMD		 1248 qemu_log_mask(LOG_UNIMP, "SDHC wr_%ub @0x%02" HWADDR_PRIx " <- 0x%08x "
1249 "not implemented\n", size, offset, value >> shift);
d7dfca08
IM		 1250 break;
1251 }
8be487d8
PMD		 1252 trace_sdhci_access("wr", size << 3, offset, "<-",
1253 value >> shift, value >> shift);
d7dfca08
IM		 1254}
1255
1256static const MemoryRegionOps sdhci_mmio_ops = {
d368ba43
KC		 1257 .read = sdhci_read,
1258 .write = sdhci_write,
d7dfca08
IM		 1259 .valid = {
1260 .min_access_size = 1,
1261 .max_access_size = 4,
1262 .unaligned = false
1263 },
1264 .endianness = DEVICE_LITTLE_ENDIAN,
1265};
1266
aceb5b06
PMD		 1267static void sdhci_init_readonly_registers(SDHCIState *s, Error **errp)
1268{
de1b3800 1269 ERRP_GUARD();
6ff37c3d 1270
4d67852d
PMD		 1271 switch (s->sd_spec_version) {
1272 case 2 ... 3:
1273 break;
1274 default:
1275 error_setg(errp, "Only Spec v2/v3 are supported");
aceb5b06
PMD		 1276 return;
1277 }
1278 s->version = (SDHC_HCVER_VENDOR << 8) | (s->sd_spec_version - 1);
6ff37c3d 1279
de1b3800
VSO		 1280 sdhci_check_capareg(s, errp);
1281 if (*errp) {
6ff37c3d
PMD		 1282 return;
1283 }
aceb5b06
PMD		 1284}
1285
b635d98c
PMD		 1286/* --- qdev common --- */
1287
ce864603 1288void sdhci_initfn(SDHCIState *s)
d7dfca08 1289{
40bbc194
PM		 1290 qbus_create_inplace(&s->sdbus, sizeof(s->sdbus),
1291 TYPE_SDHCI_BUS, DEVICE(s), "sd-bus");
d7dfca08 1292
bc72ad67 1293 s->insert_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, sdhci_raise_insertion_irq, s);
d368ba43 1294 s->transfer_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, sdhci_data_transfer, s);
fd1e5c81
AS		 1295
1296 s->io_ops = &sdhci_mmio_ops;
d7dfca08
IM		 1297}
1298
ce864603 1299void sdhci_uninitfn(SDHCIState *s)
d7dfca08 1300{
bc72ad67
AB		 1301 timer_del(s->insert_timer);
1302 timer_free(s->insert_timer);
1303 timer_del(s->transfer_timer);
1304 timer_free(s->transfer_timer);
d7dfca08 1305
012aef07
MA		 1306 g_free(s->fifo_buffer);
1307 s->fifo_buffer = NULL;
d7dfca08
IM		 1308}
1309
ce864603 1310void sdhci_common_realize(SDHCIState *s, Error **errp)
25367498 1311{
de1b3800 1312 ERRP_GUARD();
aceb5b06 1313
de1b3800
VSO		 1314 sdhci_init_readonly_registers(s, errp);
1315 if (*errp) {
aceb5b06
PMD		 1316 return;
1317 }
25367498
PMD		 1318 s->buf_maxsz = sdhci_get_fifolen(s);
1319 s->fifo_buffer = g_malloc0(s->buf_maxsz);
1320
c0983085 1321 memory_region_init_io(&s->iomem, OBJECT(s), s->io_ops, s, "sdhci",
25367498
PMD		 1322 SDHC_REGISTERS_MAP_SIZE);
1323}
1324
b69c3c21 1325void sdhci_common_unrealize(SDHCIState *s)
8b7455c7
PMD		 1326{
1327 /* This function is expected to be called only once for each class:
1328 * - SysBus: via DeviceClass->unrealize(),
1329 * - PCI: via PCIDeviceClass->exit().
1330 * However to avoid double-free and/or use-after-free we still nullify
1331 * this variable (better safe than sorry!). */
1332 g_free(s->fifo_buffer);
1333 s->fifo_buffer = NULL;
1334}
1335
0a7ac9f9
AB		 1336static bool sdhci_pending_insert_vmstate_needed(void *opaque)
1337{
1338 SDHCIState *s = opaque;
1339
1340 return s->pending_insert_state;
1341}
1342
1343static const VMStateDescription sdhci_pending_insert_vmstate = {
1344 .name = "sdhci/pending-insert",
1345 .version_id = 1,
1346 .minimum_version_id = 1,
1347 .needed = sdhci_pending_insert_vmstate_needed,
1348 .fields = (VMStateField[]) {
1349 VMSTATE_BOOL(pending_insert_state, SDHCIState),
1350 VMSTATE_END_OF_LIST()
1351 },
1352};
1353
d7dfca08
IM		 1354const VMStateDescription sdhci_vmstate = {
1355 .name = "sdhci",
1356 .version_id = 1,
1357 .minimum_version_id = 1,
35d08458 1358 .fields = (VMStateField[]) {
d7dfca08
IM		 1359 VMSTATE_UINT32(sdmasysad, SDHCIState),
1360 VMSTATE_UINT16(blksize, SDHCIState),
1361 VMSTATE_UINT16(blkcnt, SDHCIState),
1362 VMSTATE_UINT32(argument, SDHCIState),
1363 VMSTATE_UINT16(trnmod, SDHCIState),
1364 VMSTATE_UINT16(cmdreg, SDHCIState),
1365 VMSTATE_UINT32_ARRAY(rspreg, SDHCIState, 4),
1366 VMSTATE_UINT32(prnsts, SDHCIState),
06c5120b 1367 VMSTATE_UINT8(hostctl1, SDHCIState),
d7dfca08
IM		 1368 VMSTATE_UINT8(pwrcon, SDHCIState),
1369 VMSTATE_UINT8(blkgap, SDHCIState),
1370 VMSTATE_UINT8(wakcon, SDHCIState),
1371 VMSTATE_UINT16(clkcon, SDHCIState),
1372 VMSTATE_UINT8(timeoutcon, SDHCIState),
1373 VMSTATE_UINT8(admaerr, SDHCIState),
1374 VMSTATE_UINT16(norintsts, SDHCIState),
1375 VMSTATE_UINT16(errintsts, SDHCIState),
1376 VMSTATE_UINT16(norintstsen, SDHCIState),
1377 VMSTATE_UINT16(errintstsen, SDHCIState),
1378 VMSTATE_UINT16(norintsigen, SDHCIState),
1379 VMSTATE_UINT16(errintsigen, SDHCIState),
1380 VMSTATE_UINT16(acmd12errsts, SDHCIState),
1381 VMSTATE_UINT16(data_count, SDHCIState),
1382 VMSTATE_UINT64(admasysaddr, SDHCIState),
1383 VMSTATE_UINT8(stopped_state, SDHCIState),
59046ec2 1384 VMSTATE_VBUFFER_UINT32(fifo_buffer, SDHCIState, 1, NULL, buf_maxsz),
e720677e
PB		 1385 VMSTATE_TIMER_PTR(insert_timer, SDHCIState),
1386 VMSTATE_TIMER_PTR(transfer_timer, SDHCIState),
d7dfca08 1387 VMSTATE_END_OF_LIST()
0a7ac9f9
AB		 1388 },
1389 .subsections = (const VMStateDescription*[]) {
1390 &sdhci_pending_insert_vmstate,
1391 NULL
1392 },
d7dfca08
IM		 1393};
1394
ce864603 1395void sdhci_common_class_init(ObjectClass *klass, void *data)
1c92c505
PMD		 1396{
1397 DeviceClass *dc = DEVICE_CLASS(klass);
1398
1399 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
1400 dc->vmsd = &sdhci_vmstate;
1401 dc->reset = sdhci_poweron_reset;
1402}
1403
b635d98c
PMD		 1404/* --- qdev SysBus --- */
1405
5ec911c3 1406static Property sdhci_sysbus_properties[] = {
b635d98c 1407 DEFINE_SDHCI_COMMON_PROPERTIES(SDHCIState),
0a7ac9f9
AB		 1408 DEFINE_PROP_BOOL("pending-insert-quirk", SDHCIState, pending_insert_quirk,
1409 false),
60765b6c
PMD		 1410 DEFINE_PROP_LINK("dma", SDHCIState,
1411 dma_mr, TYPE_MEMORY_REGION, MemoryRegion *),
5ec911c3
KC		 1412 DEFINE_PROP_END_OF_LIST(),
1413};
1414
7302dcd6
KC		 1415static void sdhci_sysbus_init(Object *obj)
1416{
1417 SDHCIState *s = SYSBUS_SDHCI(obj);
5ec911c3 1418
40bbc194 1419 sdhci_initfn(s);
7302dcd6
KC		 1420}
1421
1422static void sdhci_sysbus_finalize(Object *obj)
1423{
1424 SDHCIState *s = SYSBUS_SDHCI(obj);
60765b6c
PMD		 1425
1426 if (s->dma_mr) {
1427 object_unparent(OBJECT(s->dma_mr));
1428 }
1429
7302dcd6
KC		 1430 sdhci_uninitfn(s);
1431}
1432
1019388c 1433static void sdhci_sysbus_realize(DeviceState *dev, Error **errp)
d7dfca08 1434{
de1b3800 1435 ERRP_GUARD();
7302dcd6 1436 SDHCIState *s = SYSBUS_SDHCI(dev);
d7dfca08
IM		 1437 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
1438
de1b3800
VSO		 1439 sdhci_common_realize(s, errp);
1440 if (*errp) {
25367498
PMD		 1441 return;
1442 }
1443
60765b6c 1444 if (s->dma_mr) {
02e57e1c 1445 s->dma_as = &s->sysbus_dma_as;
60765b6c
PMD		 1446 address_space_init(s->dma_as, s->dma_mr, "sdhci-dma");
1447 } else {
1448 /* use system_memory() if property "dma" not set */
1449 s->dma_as = &address_space_memory;
1450 }
dd55c485 1451
d7dfca08 1452 sysbus_init_irq(sbd, &s->irq);
fd1e5c81 1453
d7dfca08
IM		 1454 sysbus_init_mmio(sbd, &s->iomem);
1455}
1456
b69c3c21 1457static void sdhci_sysbus_unrealize(DeviceState *dev)
8b7455c7
PMD		 1458{
1459 SDHCIState *s = SYSBUS_SDHCI(dev);
1460
b69c3c21 1461 sdhci_common_unrealize(s);
60765b6c
PMD		 1462
1463 if (s->dma_mr) {
1464 address_space_destroy(s->dma_as);
1465 }
8b7455c7
PMD		 1466}
1467
7302dcd6 1468static void sdhci_sysbus_class_init(ObjectClass *klass, void *data)
d7dfca08
IM		 1469{
1470 DeviceClass *dc = DEVICE_CLASS(klass);
d7dfca08 1471
4f67d30b 1472 device_class_set_props(dc, sdhci_sysbus_properties);
7302dcd6 1473 dc->realize = sdhci_sysbus_realize;
8b7455c7 1474 dc->unrealize = sdhci_sysbus_unrealize;
1c92c505
PMD		 1475
1476 sdhci_common_class_init(klass, data);
d7dfca08
IM		 1477}
1478
7302dcd6
KC		 1479static const TypeInfo sdhci_sysbus_info = {
1480 .name = TYPE_SYSBUS_SDHCI,
d7dfca08
IM		 1481 .parent = TYPE_SYS_BUS_DEVICE,
1482 .instance_size = sizeof(SDHCIState),
7302dcd6
KC		 1483 .instance_init = sdhci_sysbus_init,
1484 .instance_finalize = sdhci_sysbus_finalize,
1485 .class_init = sdhci_sysbus_class_init,
d7dfca08
IM		 1486};
1487
b635d98c
PMD		 1488/* --- qdev bus master --- */
1489
40bbc194
PM		 1490static void sdhci_bus_class_init(ObjectClass *klass, void *data)
1491{
1492 SDBusClass *sbc = SD_BUS_CLASS(klass);
1493
1494 sbc->set_inserted = sdhci_set_inserted;
1495 sbc->set_readonly = sdhci_set_readonly;
1496}
1497
1498static const TypeInfo sdhci_bus_info = {
1499 .name = TYPE_SDHCI_BUS,
1500 .parent = TYPE_SD_BUS,
1501 .instance_size = sizeof(SDBus),
1502 .class_init = sdhci_bus_class_init,
1503};
1504
efadc818
PMD		 1505/* --- qdev i.MX eSDHC --- */
1506
fd1e5c81
AS		 1507static uint64_t usdhc_read(void *opaque, hwaddr offset, unsigned size)
1508{
1509 SDHCIState *s = SYSBUS_SDHCI(opaque);
1510 uint32_t ret;
06c5120b 1511 uint16_t hostctl1;
fd1e5c81
AS		 1512
1513 switch (offset) {
1514 default:
1515 return sdhci_read(opaque, offset, size);
1516
1517 case SDHC_HOSTCTL:
1518 /*
1519 * For a detailed explanation on the following bit
1520 * manipulation code see comments in a similar part of
1521 * usdhc_write()
1522 */
06c5120b 1523 hostctl1 = SDHC_DMA_TYPE(s->hostctl1) << (8 - 3);
fd1e5c81 1524
06c5120b
PMD		 1525 if (s->hostctl1 & SDHC_CTRL_8BITBUS) {
1526 hostctl1 |= ESDHC_CTRL_8BITBUS;
fd1e5c81
AS		 1527 }
1528
06c5120b
PMD		 1529 if (s->hostctl1 & SDHC_CTRL_4BITBUS) {
1530 hostctl1 |= ESDHC_CTRL_4BITBUS;
fd1e5c81
AS		 1531 }
1532
06c5120b 1533 ret = hostctl1;
fd1e5c81
AS		 1534 ret |= (uint32_t)s->blkgap << 16;
1535 ret |= (uint32_t)s->wakcon << 24;
1536
1537 break;
1538
6bfd06da
HEF		 1539 case SDHC_PRNSTS:
1540 /* Add SDSTB (SD Clock Stable) bit to PRNSTS */
1541 ret = sdhci_read(opaque, offset, size) & ~ESDHC_PRNSTS_SDSTB;
1542 if (s->clkcon & SDHC_CLOCK_INT_STABLE) {
1543 ret |= ESDHC_PRNSTS_SDSTB;
1544 }
1545 break;
1546
3b2d8176
GR		 1547 case ESDHC_VENDOR_SPEC:
1548 ret = s->vendor_spec;
1549 break;
fd1e5c81
AS		 1550 case ESDHC_DLL_CTRL:
1551 case ESDHC_TUNE_CTRL_STATUS:
1552 case ESDHC_UNDOCUMENTED_REG27:
1553 case ESDHC_TUNING_CTRL:
fd1e5c81
AS		 1554 case ESDHC_MIX_CTRL:
1555 case ESDHC_WTMK_LVL:
1556 ret = 0;
1557 break;
1558 }
1559
1560 return ret;
1561}
1562
1563static void
1564usdhc_write(void *opaque, hwaddr offset, uint64_t val, unsigned size)
1565{
1566 SDHCIState *s = SYSBUS_SDHCI(opaque);
06c5120b 1567 uint8_t hostctl1;
fd1e5c81
AS		 1568 uint32_t value = (uint32_t)val;
1569
1570 switch (offset) {
1571 case ESDHC_DLL_CTRL:
1572 case ESDHC_TUNE_CTRL_STATUS:
1573 case ESDHC_UNDOCUMENTED_REG27:
1574 case ESDHC_TUNING_CTRL:
1575 case ESDHC_WTMK_LVL:
3b2d8176
GR		 1576 break;
1577
fd1e5c81 1578 case ESDHC_VENDOR_SPEC:
3b2d8176
GR		 1579 s->vendor_spec = value;
1580 switch (s->vendor) {
1581 case SDHCI_VENDOR_IMX:
1582 if (value & ESDHC_IMX_FRC_SDCLK_ON) {
1583 s->prnsts &= ~SDHC_IMX_CLOCK_GATE_OFF;
1584 } else {
1585 s->prnsts |= SDHC_IMX_CLOCK_GATE_OFF;
1586 }
1587 break;
1588 default:
1589 break;
1590 }
fd1e5c81
AS		 1591 break;
1592
1593 case SDHC_HOSTCTL:
1594 /*
1595 * Here's What ESDHCI has at offset 0x28 (SDHC_HOSTCTL)
1596 *
1597 * 7 6 5 4 3 2 1 0
1598 * |-----------+--------+--------+-----------+----------+---------|
1599 * | Card | Card | Endian | DATA3 | Data | Led |
1600 * | Detect | Detect | Mode | as Card | Transfer | Control |
1601 * | Signal | Test | | Detection | Width | |
1602 * | Selection | Level | | Pin | | |
1603 * |-----------+--------+--------+-----------+----------+---------|
1604 *
1605 * and 0x29
1606 *
1607 * 15 10 9 8
1608 * |----------+------|
1609 * | Reserved | DMA |
1610 * | | Sel. |
1611 * | | |
1612 * |----------+------|
1613 *
1614 * and here's what SDCHI spec expects those offsets to be:
1615 *
1616 * 0x28 (Host Control Register)
1617 *
1618 * 7 6 5 4 3 2 1 0
1619 * |--------+--------+----------+------+--------+----------+---------|
1620 * | Card | Card | Extended | DMA | High | Data | LED |
1621 * | Detect | Detect | Data | Sel. | Speed | Transfer | Control |
1622 * | Signal | Test | Transfer | | Enable | Width | |
1623 * | Sel. | Level | Width | | | | |
1624 * |--------+--------+----------+------+--------+----------+---------|
1625 *
1626 * and 0x29 (Power Control Register)
1627 *
1628 * |----------------------------------|
1629 * | Power Control Register |
1630 * | |
1631 * | Description omitted, |
1632 * | since it has no analog in ESDHCI |
1633 * | |
1634 * |----------------------------------|
1635 *
1636 * Since offsets 0x2A and 0x2B should be compatible between
1637 * both IP specs we only need to reconcile least 16-bit of the
1638 * word we've been given.
1639 */
1640
1641 /*
1642 * First, save bits 7 6 and 0 since they are identical
1643 */
06c5120b
PMD		 1644 hostctl1 = value & (SDHC_CTRL_LED |
1645 SDHC_CTRL_CDTEST_INS |
1646 SDHC_CTRL_CDTEST_EN);
fd1e5c81
AS		 1647 /*
1648 * Second, split "Data Transfer Width" from bits 2 and 1 in to
1649 * bits 5 and 1
1650 */
1651 if (value & ESDHC_CTRL_8BITBUS) {
06c5120b 1652 hostctl1 |= SDHC_CTRL_8BITBUS;
fd1e5c81
AS		 1653 }
1654
1655 if (value & ESDHC_CTRL_4BITBUS) {
06c5120b 1656 hostctl1 |= ESDHC_CTRL_4BITBUS;
fd1e5c81
AS		 1657 }
1658
1659 /*
1660 * Third, move DMA select from bits 9 and 8 to bits 4 and 3
1661 */
06c5120b 1662 hostctl1 |= SDHC_DMA_TYPE(value >> (8 - 3));
fd1e5c81
AS		 1663
1664 /*
1665 * Now place the corrected value into low 16-bit of the value
1666 * we are going to give standard SDHCI write function
1667 *
1668 * NOTE: This transformation should be the inverse of what can
1669 * be found in drivers/mmc/host/sdhci-esdhc-imx.c in Linux
1670 * kernel
1671 */
1672 value &= ~UINT16_MAX;
06c5120b 1673 value |= hostctl1;
fd1e5c81
AS		 1674 value |= (uint16_t)s->pwrcon << 8;
1675
1676 sdhci_write(opaque, offset, value, size);
1677 break;
1678
1679 case ESDHC_MIX_CTRL:
1680 /*
1681 * So, when SD/MMC stack in Linux tries to write to "Transfer
1682 * Mode Register", ESDHC i.MX quirk code will translate it
1683 * into a write to ESDHC_MIX_CTRL, so we do the opposite in
1684 * order to get where we started
1685 *
1686 * Note that Auto CMD23 Enable bit is located in a wrong place
1687 * on i.MX, but since it is not used by QEMU we do not care.
1688 *
1689 * We don't want to call sdhci_write(.., SDHC_TRNMOD, ...)
1690 * here becuase it will result in a call to
1691 * sdhci_send_command(s) which we don't want.
1692 *
1693 */
1694 s->trnmod = value & UINT16_MAX;
1695 break;
1696 case SDHC_TRNMOD:
1697 /*
1698 * Similar to above, but this time a write to "Command
1699 * Register" will be translated into a 4-byte write to
1700 * "Transfer Mode register" where lower 16-bit of value would
1701 * be set to zero. So what we do is fill those bits with
1702 * cached value from s->trnmod and let the SDHCI
1703 * infrastructure handle the rest
1704 */
1705 sdhci_write(opaque, offset, val | s->trnmod, size);
1706 break;
1707 case SDHC_BLKSIZE:
1708 /*
1709 * ESDHCI does not implement "Host SDMA Buffer Boundary", and
1710 * Linux driver will try to zero this field out which will
1711 * break the rest of SDHCI emulation.
1712 *
1713 * Linux defaults to maximum possible setting (512K boundary)
1714 * and it seems to be the only option that i.MX IP implements,
1715 * so we artificially set it to that value.
1716 */
1717 val |= 0x7 << 12;
1718 /* FALLTHROUGH */
1719 default:
1720 sdhci_write(opaque, offset, val, size);
1721 break;
1722 }
1723}
1724
fd1e5c81
AS		 1725static const MemoryRegionOps usdhc_mmio_ops = {
1726 .read = usdhc_read,
1727 .write = usdhc_write,
1728 .valid = {
1729 .min_access_size = 1,
1730 .max_access_size = 4,
1731 .unaligned = false
1732 },
1733 .endianness = DEVICE_LITTLE_ENDIAN,
1734};
1735
1736static void imx_usdhc_init(Object *obj)
1737{
1738 SDHCIState *s = SYSBUS_SDHCI(obj);
1739
1740 s->io_ops = &usdhc_mmio_ops;
1741 s->quirks = SDHCI_QUIRK_NO_BUSY_IRQ;
1742}
1743
1744static const TypeInfo imx_usdhc_info = {
1745 .name = TYPE_IMX_USDHC,
1746 .parent = TYPE_SYSBUS_SDHCI,
1747 .instance_init = imx_usdhc_init,
1748};
1749
c85fba50
PMD		 1750/* --- qdev Samsung s3c --- */
1751
1752#define S3C_SDHCI_CONTROL2 0x80
1753#define S3C_SDHCI_CONTROL3 0x84
1754#define S3C_SDHCI_CONTROL4 0x8c
1755
1756static uint64_t sdhci_s3c_read(void *opaque, hwaddr offset, unsigned size)
1757{
1758 uint64_t ret;
1759
1760 switch (offset) {
1761 case S3C_SDHCI_CONTROL2:
1762 case S3C_SDHCI_CONTROL3:
1763 case S3C_SDHCI_CONTROL4:
1764 /* ignore */
1765 ret = 0;
1766 break;
1767 default:
1768 ret = sdhci_read(opaque, offset, size);
1769 break;
1770 }
1771
1772 return ret;
1773}
1774
1775static void sdhci_s3c_write(void *opaque, hwaddr offset, uint64_t val,
1776 unsigned size)
1777{
1778 switch (offset) {
1779 case S3C_SDHCI_CONTROL2:
1780 case S3C_SDHCI_CONTROL3:
1781 case S3C_SDHCI_CONTROL4:
1782 /* ignore */
1783 break;
1784 default:
1785 sdhci_write(opaque, offset, val, size);
1786 break;
1787 }
1788}
1789
1790static const MemoryRegionOps sdhci_s3c_mmio_ops = {
1791 .read = sdhci_s3c_read,
1792 .write = sdhci_s3c_write,
1793 .valid = {
1794 .min_access_size = 1,
1795 .max_access_size = 4,
1796 .unaligned = false
1797 },
1798 .endianness = DEVICE_LITTLE_ENDIAN,
1799};
1800
1801static void sdhci_s3c_init(Object *obj)
1802{
1803 SDHCIState *s = SYSBUS_SDHCI(obj);
1804
1805 s->io_ops = &sdhci_s3c_mmio_ops;
1806}
1807
1808static const TypeInfo sdhci_s3c_info = {
1809 .name = TYPE_S3C_SDHCI ,
1810 .parent = TYPE_SYSBUS_SDHCI,
1811 .instance_init = sdhci_s3c_init,
1812};
1813
d7dfca08
IM		 1814static void sdhci_register_types(void)
1815{
7302dcd6 1816 type_register_static(&sdhci_sysbus_info);
40bbc194 1817 type_register_static(&sdhci_bus_info);
fd1e5c81 1818 type_register_static(&imx_usdhc_info);
c85fba50 1819 type_register_static(&sdhci_s3c_info);
d7dfca08
IM		 1820}
1821
1822type_init(sdhci_register_types)
Empty description
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