[qemu.git] / hw / arm_timer.c

/*
 * ARM PrimeCell Timer modules.
 *
 * Copyright (c) 2005-2006 CodeSourcery.
 * Written by Paul Brook
 *
 * This code is licenced under the GPL.
 */

#include "sysbus.h"
#include "qemu-timer.h"

/* Common timer implementation.  */

#define TIMER_CTRL_ONESHOT      (1 << 0)
#define TIMER_CTRL_32BIT        (1 << 1)
#define TIMER_CTRL_DIV1         (0 << 2)
#define TIMER_CTRL_DIV16        (1 << 2)
#define TIMER_CTRL_DIV256       (2 << 2)
#define TIMER_CTRL_IE           (1 << 5)
#define TIMER_CTRL_PERIODIC     (1 << 6)
#define TIMER_CTRL_ENABLE       (1 << 7)

typedef struct {
    ptimer_state *timer;
    uint32_t control;
    uint32_t limit;
    int freq;
    int int_level;
    qemu_irq irq;
} arm_timer_state;

/* Check all active timers, and schedule the next timer interrupt.  */

static void arm_timer_update(arm_timer_state *s)
{
    /* Update interrupts.  */
    if (s->int_level && (s->control & TIMER_CTRL_IE)) {
        qemu_irq_raise(s->irq);
    } else {
        qemu_irq_lower(s->irq);
    }
}

static uint32_t arm_timer_read(void *opaque, target_phys_addr_t offset)
{
    arm_timer_state *s = (arm_timer_state *)opaque;

    switch (offset >> 2) {
    case 0: /* TimerLoad */
    case 6: /* TimerBGLoad */
        return s->limit;
    case 1: /* TimerValue */
        return ptimer_get_count(s->timer);
    case 2: /* TimerControl */
        return s->control;
    case 4: /* TimerRIS */
        return s->int_level;
    case 5: /* TimerMIS */
        if ((s->control & TIMER_CTRL_IE) == 0)
            return 0;
        return s->int_level;
    default:
        hw_error("arm_timer_read: Bad offset %x\n", (int)offset);
        return 0;
    }
}

/* Reset the timer limit after settings have changed.  */
static void arm_timer_recalibrate(arm_timer_state *s, int reload)
{
    uint32_t limit;

    if ((s->control & TIMER_CTRL_PERIODIC) == 0) {
        /* Free running.  */
        if (s->control & TIMER_CTRL_32BIT)
            limit = 0xffffffff;
        else
            limit = 0xffff;
    } else {
          /* Periodic.  */
          limit = s->limit;
    }
    ptimer_set_limit(s->timer, limit, reload);
}

static void arm_timer_write(void *opaque, target_phys_addr_t offset,
                            uint32_t value)
{
    arm_timer_state *s = (arm_timer_state *)opaque;
    int freq;

    switch (offset >> 2) {
    case 0: /* TimerLoad */
        s->limit = value;
        arm_timer_recalibrate(s, 1);
        break;
    case 1: /* TimerValue */
        /* ??? Linux seems to want to write to this readonly register.
           Ignore it.  */
        break;
    case 2: /* TimerControl */
        if (s->control & TIMER_CTRL_ENABLE) {
            /* Pause the timer if it is running.  This may cause some
               inaccuracy dure to rounding, but avoids a whole lot of other
               messyness.  */
            ptimer_stop(s->timer);
        }
        s->control = value;
        freq = s->freq;
        /* ??? Need to recalculate expiry time after changing divisor.  */
        switch ((value >> 2) & 3) {
        case 1: freq >>= 4; break;
        case 2: freq >>= 8; break;
        }
        arm_timer_recalibrate(s, 0);
        ptimer_set_freq(s->timer, freq);
        if (s->control & TIMER_CTRL_ENABLE) {
            /* Restart the timer if still enabled.  */
            ptimer_run(s->timer, (s->control & TIMER_CTRL_ONESHOT) != 0);
        }
        break;
    case 3: /* TimerIntClr */
        s->int_level = 0;
        break;
    case 6: /* TimerBGLoad */
        s->limit = value;
        arm_timer_recalibrate(s, 0);
        break;
    default:
        hw_error("arm_timer_write: Bad offset %x\n", (int)offset);
    }
    arm_timer_update(s);
}

static void arm_timer_tick(void *opaque)
{
    arm_timer_state *s = (arm_timer_state *)opaque;
    s->int_level = 1;
    arm_timer_update(s);
}

static void arm_timer_save(QEMUFile *f, void *opaque)
{
    arm_timer_state *s = (arm_timer_state *)opaque;
    qemu_put_be32(f, s->control);
    qemu_put_be32(f, s->limit);
    qemu_put_be32(f, s->int_level);
    qemu_put_ptimer(f, s->timer);
}

static int arm_timer_load(QEMUFile *f, void *opaque, int version_id)
{
    arm_timer_state *s = (arm_timer_state *)opaque;

    if (version_id != 1)
        return -EINVAL;

    s->control = qemu_get_be32(f);
    s->limit = qemu_get_be32(f);
    s->int_level = qemu_get_be32(f);
    qemu_get_ptimer(f, s->timer);
    return 0;
}

static arm_timer_state *arm_timer_init(uint32_t freq)
{
    arm_timer_state *s;
    QEMUBH *bh;

    s = (arm_timer_state *)qemu_mallocz(sizeof(arm_timer_state));
    s->freq = freq;
    s->control = TIMER_CTRL_IE;

    bh = qemu_bh_new(arm_timer_tick, s);
    s->timer = ptimer_init(bh);
    register_savevm("arm_timer", -1, 1, arm_timer_save, arm_timer_load, s);
    return s;
}

/* ARM PrimeCell SP804 dual timer module.
   Docs for this device don't seem to be publicly available.  This
   implementation is based on guesswork, the linux kernel sources and the
   Integrator/CP timer modules.  */

typedef struct {
    SysBusDevice busdev;
    arm_timer_state *timer[2];
    int level[2];
    qemu_irq irq;
} sp804_state;

/* Merge the IRQs from the two component devices.  */
static void sp804_set_irq(void *opaque, int irq, int level)
{
    sp804_state *s = (sp804_state *)opaque;

    s->level[irq] = level;
    qemu_set_irq(s->irq, s->level[0] || s->level[1]);
}

static uint32_t sp804_read(void *opaque, target_phys_addr_t offset)
{
    sp804_state *s = (sp804_state *)opaque;

    /* ??? Don't know the PrimeCell ID for this device.  */
    if (offset < 0x20) {
        return arm_timer_read(s->timer[0], offset);
    } else {
        return arm_timer_read(s->timer[1], offset - 0x20);
    }
}

static void sp804_write(void *opaque, target_phys_addr_t offset,
                        uint32_t value)
{
    sp804_state *s = (sp804_state *)opaque;

    if (offset < 0x20) {
        arm_timer_write(s->timer[0], offset, value);
    } else {
        arm_timer_write(s->timer[1], offset - 0x20, value);
    }
}

static CPUReadMemoryFunc * const sp804_readfn[] = {
   sp804_read,
   sp804_read,
   sp804_read
};

static CPUWriteMemoryFunc * const sp804_writefn[] = {
   sp804_write,
   sp804_write,
   sp804_write
};

static void sp804_save(QEMUFile *f, void *opaque)
{
    sp804_state *s = (sp804_state *)opaque;
    qemu_put_be32(f, s->level[0]);
    qemu_put_be32(f, s->level[1]);
}

static int sp804_load(QEMUFile *f, void *opaque, int version_id)
{
    sp804_state *s = (sp804_state *)opaque;

    if (version_id != 1)
        return -EINVAL;

    s->level[0] = qemu_get_be32(f);
    s->level[1] = qemu_get_be32(f);
    return 0;
}

static int sp804_init(SysBusDevice *dev)
{
    int iomemtype;
    sp804_state *s = FROM_SYSBUS(sp804_state, dev);
    qemu_irq *qi;

    qi = qemu_allocate_irqs(sp804_set_irq, s, 2);
    sysbus_init_irq(dev, &s->irq);
    /* ??? The timers are actually configurable between 32kHz and 1MHz, but
       we don't implement that.  */
    s->timer[0] = arm_timer_init(1000000);
    s->timer[1] = arm_timer_init(1000000);
    s->timer[0]->irq = qi[0];
    s->timer[1]->irq = qi[1];
    iomemtype = cpu_register_io_memory(sp804_readfn,
                                       sp804_writefn, s);
    sysbus_init_mmio(dev, 0x1000, iomemtype);
    register_savevm("sp804", -1, 1, sp804_save, sp804_load, s);
    return 0;
}


/* Integrator/CP timer module.  */

typedef struct {
    SysBusDevice busdev;
    arm_timer_state *timer[3];
} icp_pit_state;

static uint32_t icp_pit_read(void *opaque, target_phys_addr_t offset)
{
    icp_pit_state *s = (icp_pit_state *)opaque;
    int n;

    /* ??? Don't know the PrimeCell ID for this device.  */
    n = offset >> 8;
    if (n > 3) {
        hw_error("sp804_read: Bad timer %d\n", n);
    }

    return arm_timer_read(s->timer[n], offset & 0xff);
}

static void icp_pit_write(void *opaque, target_phys_addr_t offset,
                          uint32_t value)
{
    icp_pit_state *s = (icp_pit_state *)opaque;
    int n;

    n = offset >> 8;
    if (n > 3) {
        hw_error("sp804_write: Bad timer %d\n", n);
    }

    arm_timer_write(s->timer[n], offset & 0xff, value);
}


static CPUReadMemoryFunc * const icp_pit_readfn[] = {
   icp_pit_read,
   icp_pit_read,
   icp_pit_read
};

static CPUWriteMemoryFunc * const icp_pit_writefn[] = {
   icp_pit_write,
   icp_pit_write,
   icp_pit_write
};

static int icp_pit_init(SysBusDevice *dev)
{
    int iomemtype;
    icp_pit_state *s = FROM_SYSBUS(icp_pit_state, dev);

    /* Timer 0 runs at the system clock speed (40MHz).  */
    s->timer[0] = arm_timer_init(40000000);
    /* The other two timers run at 1MHz.  */
    s->timer[1] = arm_timer_init(1000000);
    s->timer[2] = arm_timer_init(1000000);

    sysbus_init_irq(dev, &s->timer[0]->irq);
    sysbus_init_irq(dev, &s->timer[1]->irq);
    sysbus_init_irq(dev, &s->timer[2]->irq);

    iomemtype = cpu_register_io_memory(icp_pit_readfn,
                                       icp_pit_writefn, s);
    sysbus_init_mmio(dev, 0x1000, iomemtype);
    /* This device has no state to save/restore.  The component timers will
       save themselves.  */
    return 0;
}

static void arm_timer_register_devices(void)
{
    sysbus_register_dev("integrator_pit", sizeof(icp_pit_state), icp_pit_init);
    sysbus_register_dev("sp804", sizeof(sp804_state), sp804_init);
}

device_init(arm_timer_register_devices)
Commit	Line	Data
5fafdf24	1	/*
cdbdb648 PB	2	* ARM PrimeCell Timer modules.
	3	*
	4	* Copyright (c) 2005-2006 CodeSourcery.
	5	* Written by Paul Brook
	6	*
	7	* This code is licenced under the GPL.
	8	*/
	9
6a824ec3	10	#include "sysbus.h"
87ecb68b	11	#include "qemu-timer.h"
cdbdb648 PB	12
	13	/* Common timer implementation. */
	14
	15	#define TIMER_CTRL_ONESHOT (1 << 0)
	16	#define TIMER_CTRL_32BIT (1 << 1)
	17	#define TIMER_CTRL_DIV1 (0 << 2)
	18	#define TIMER_CTRL_DIV16 (1 << 2)
	19	#define TIMER_CTRL_DIV256 (2 << 2)
	20	#define TIMER_CTRL_IE (1 << 5)
	21	#define TIMER_CTRL_PERIODIC (1 << 6)
	22	#define TIMER_CTRL_ENABLE (1 << 7)
	23
	24	typedef struct {
423f0742	25	ptimer_state *timer;
cdbdb648	26	uint32_t control;
cdbdb648	27	uint32_t limit;
cdbdb648 PB	28	int freq;
cdbdb648 PB	29	int int_level;
d537cf6c	30	qemu_irq irq;
cdbdb648 PB	31	} arm_timer_state;
cdbdb648 PB	32
cdbdb648 PB	33	/* Check all active timers, and schedule the next timer interrupt. */
cdbdb648 PB	34
423f0742	35	static void arm_timer_update(arm_timer_state *s)
cdbdb648	36	{
cdbdb648 PB	37	/* Update interrupts. */
cdbdb648 PB	38	if (s->int_level && (s->control & TIMER_CTRL_IE)) {
d537cf6c	39	qemu_irq_raise(s->irq);
cdbdb648	40	} else {
d537cf6c	41	qemu_irq_lower(s->irq);
cdbdb648	42	}
cdbdb648 PB	43	}
cdbdb648 PB	44
c227f099	45	static uint32_t arm_timer_read(void *opaque, target_phys_addr_t offset)
cdbdb648 PB	46	{
	47	arm_timer_state s = (arm_timer_state )opaque;
	48
	49	switch (offset >> 2) {
	50	case 0: /* TimerLoad */
	51	case 6: /* TimerBGLoad */
	52	return s->limit;
	53	case 1: /* TimerValue */
423f0742	54	return ptimer_get_count(s->timer);
cdbdb648 PB	55	case 2: /* TimerControl */
	56	return s->control;
	57	case 4: /* TimerRIS */
	58	return s->int_level;
	59	case 5: /* TimerMIS */
	60	if ((s->control & TIMER_CTRL_IE) == 0)
	61	return 0;
	62	return s->int_level;
	63	default:
2ac71179	64	hw_error("arm_timer_read: Bad offset %x\n", (int)offset);
cdbdb648 PB	65	return 0;
	66	}
	67	}
	68
423f0742 PB	69	/* Reset the timer limit after settings have changed. */
	70	static void arm_timer_recalibrate(arm_timer_state *s, int reload)
	71	{
	72	uint32_t limit;
	73
	74	if ((s->control & TIMER_CTRL_PERIODIC) == 0) {
	75	/* Free running. */
	76	if (s->control & TIMER_CTRL_32BIT)
	77	limit = 0xffffffff;
	78	else
	79	limit = 0xffff;
	80	} else {
	81	/* Periodic. */
	82	limit = s->limit;
	83	}
	84	ptimer_set_limit(s->timer, limit, reload);
	85	}
	86
c227f099	87	static void arm_timer_write(void *opaque, target_phys_addr_t offset,
cdbdb648 PB	88	uint32_t value)
	89	{
	90	arm_timer_state s = (arm_timer_state )opaque;
423f0742	91	int freq;
cdbdb648	92
cdbdb648 PB	93	switch (offset >> 2) {
	94	case 0: /* TimerLoad */
	95	s->limit = value;
423f0742	96	arm_timer_recalibrate(s, 1);
cdbdb648 PB	97	break;
	98	case 1: /* TimerValue */
	99	/* ??? Linux seems to want to write to this readonly register.
	100	Ignore it. */
	101	break;
	102	case 2: /* TimerControl */
	103	if (s->control & TIMER_CTRL_ENABLE) {
	104	/* Pause the timer if it is running. This may cause some
	105	inaccuracy dure to rounding, but avoids a whole lot of other
	106	messyness. */
423f0742	107	ptimer_stop(s->timer);
cdbdb648 PB	108	}
cdbdb648 PB	109	s->control = value;
423f0742	110	freq = s->freq;
cdbdb648 PB	111	/* ??? Need to recalculate expiry time after changing divisor. */
cdbdb648 PB	112	switch ((value >> 2) & 3) {
423f0742 PB	113	case 1: freq >>= 4; break;
423f0742 PB	114	case 2: freq >>= 8; break;
cdbdb648	115	}
423f0742 PB	116	arm_timer_recalibrate(s, 0);
423f0742 PB	117	ptimer_set_freq(s->timer, freq);
cdbdb648 PB	118	if (s->control & TIMER_CTRL_ENABLE) {
cdbdb648 PB	119	/* Restart the timer if still enabled. */
423f0742	120	ptimer_run(s->timer, (s->control & TIMER_CTRL_ONESHOT) != 0);
cdbdb648 PB	121	}
	122	break;
	123	case 3: /* TimerIntClr */
	124	s->int_level = 0;
	125	break;
	126	case 6: /* TimerBGLoad */
	127	s->limit = value;
423f0742	128	arm_timer_recalibrate(s, 0);
cdbdb648 PB	129	break;
cdbdb648 PB	130	default:
2ac71179	131	hw_error("arm_timer_write: Bad offset %x\n", (int)offset);
cdbdb648	132	}
423f0742	133	arm_timer_update(s);
cdbdb648 PB	134	}
	135
	136	static void arm_timer_tick(void *opaque)
	137	{
423f0742 PB	138	arm_timer_state s = (arm_timer_state )opaque;
	139	s->int_level = 1;
	140	arm_timer_update(s);
cdbdb648 PB	141	}
cdbdb648 PB	142
23e39294 PB	143	static void arm_timer_save(QEMUFile f, void opaque)
	144	{
	145	arm_timer_state s = (arm_timer_state )opaque;
	146	qemu_put_be32(f, s->control);
	147	qemu_put_be32(f, s->limit);
	148	qemu_put_be32(f, s->int_level);
	149	qemu_put_ptimer(f, s->timer);
	150	}
	151
	152	static int arm_timer_load(QEMUFile f, void opaque, int version_id)
	153	{
	154	arm_timer_state s = (arm_timer_state )opaque;
	155
	156	if (version_id != 1)
	157	return -EINVAL;
	158
	159	s->control = qemu_get_be32(f);
	160	s->limit = qemu_get_be32(f);
	161	s->int_level = qemu_get_be32(f);
	162	qemu_get_ptimer(f, s->timer);
	163	return 0;
	164	}
	165
6a824ec3	166	static arm_timer_state *arm_timer_init(uint32_t freq)
cdbdb648 PB	167	{
cdbdb648 PB	168	arm_timer_state *s;
423f0742	169	QEMUBH *bh;
cdbdb648 PB	170
cdbdb648 PB	171	s = (arm_timer_state *)qemu_mallocz(sizeof(arm_timer_state));
423f0742	172	s->freq = freq;
cdbdb648	173	s->control = TIMER_CTRL_IE;
cdbdb648	174
423f0742 PB	175	bh = qemu_bh_new(arm_timer_tick, s);
423f0742 PB	176	s->timer = ptimer_init(bh);
23e39294	177	register_savevm("arm_timer", -1, 1, arm_timer_save, arm_timer_load, s);
cdbdb648 PB	178	return s;
	179	}
	180
	181	/* ARM PrimeCell SP804 dual timer module.
	182	Docs for this device don't seem to be publicly available. This
d85fb99b	183	implementation is based on guesswork, the linux kernel sources and the
cdbdb648 PB	184	Integrator/CP timer modules. */
	185
	186	typedef struct {
6a824ec3 PB	187	SysBusDevice busdev;
6a824ec3 PB	188	arm_timer_state *timer[2];
cdbdb648	189	int level[2];
d537cf6c	190	qemu_irq irq;
cdbdb648 PB	191	} sp804_state;
cdbdb648 PB	192
d537cf6c	193	/* Merge the IRQs from the two component devices. */
cdbdb648 PB	194	static void sp804_set_irq(void *opaque, int irq, int level)
	195	{
	196	sp804_state s = (sp804_state )opaque;
	197
	198	s->level[irq] = level;
d537cf6c	199	qemu_set_irq(s->irq, s->level[0] \|\| s->level[1]);
cdbdb648 PB	200	}
cdbdb648 PB	201
c227f099	202	static uint32_t sp804_read(void *opaque, target_phys_addr_t offset)
cdbdb648 PB	203	{
	204	sp804_state s = (sp804_state )opaque;
	205
	206	/* ??? Don't know the PrimeCell ID for this device. */
cdbdb648 PB	207	if (offset < 0x20) {
	208	return arm_timer_read(s->timer[0], offset);
	209	} else {
	210	return arm_timer_read(s->timer[1], offset - 0x20);
	211	}
	212	}
	213
c227f099	214	static void sp804_write(void *opaque, target_phys_addr_t offset,
cdbdb648 PB	215	uint32_t value)
	216	{
	217	sp804_state s = (sp804_state )opaque;
	218
cdbdb648 PB	219	if (offset < 0x20) {
	220	arm_timer_write(s->timer[0], offset, value);
	221	} else {
	222	arm_timer_write(s->timer[1], offset - 0x20, value);
	223	}
	224	}
	225
d60efc6b	226	static CPUReadMemoryFunc * const sp804_readfn[] = {
cdbdb648 PB	227	sp804_read,
	228	sp804_read,
	229	sp804_read
	230	};
	231
d60efc6b	232	static CPUWriteMemoryFunc * const sp804_writefn[] = {
cdbdb648 PB	233	sp804_write,
	234	sp804_write,
	235	sp804_write
	236	};
	237
23e39294 PB	238	static void sp804_save(QEMUFile f, void opaque)
	239	{
	240	sp804_state s = (sp804_state )opaque;
	241	qemu_put_be32(f, s->level[0]);
	242	qemu_put_be32(f, s->level[1]);
	243	}
	244
	245	static int sp804_load(QEMUFile f, void opaque, int version_id)
	246	{
	247	sp804_state s = (sp804_state )opaque;
	248
	249	if (version_id != 1)
	250	return -EINVAL;
	251
	252	s->level[0] = qemu_get_be32(f);
	253	s->level[1] = qemu_get_be32(f);
	254	return 0;
	255	}
	256
81a322d4	257	static int sp804_init(SysBusDevice *dev)
cdbdb648 PB	258	{
cdbdb648 PB	259	int iomemtype;
6a824ec3	260	sp804_state *s = FROM_SYSBUS(sp804_state, dev);
d537cf6c	261	qemu_irq *qi;
cdbdb648	262
d537cf6c	263	qi = qemu_allocate_irqs(sp804_set_irq, s, 2);
6a824ec3	264	sysbus_init_irq(dev, &s->irq);
cdbdb648 PB	265	/* ??? The timers are actually configurable between 32kHz and 1MHz, but
cdbdb648 PB	266	we don't implement that. */
6a824ec3 PB	267	s->timer[0] = arm_timer_init(1000000);
	268	s->timer[1] = arm_timer_init(1000000);
	269	s->timer[0]->irq = qi[0];
	270	s->timer[1]->irq = qi[1];
1eed09cb	271	iomemtype = cpu_register_io_memory(sp804_readfn,
cdbdb648	272	sp804_writefn, s);
6a824ec3	273	sysbus_init_mmio(dev, 0x1000, iomemtype);
23e39294	274	register_savevm("sp804", -1, 1, sp804_save, sp804_load, s);
81a322d4	275	return 0;
cdbdb648 PB	276	}
	277
	278
	279	/* Integrator/CP timer module. */
	280
	281	typedef struct {
6a824ec3 PB	282	SysBusDevice busdev;
6a824ec3 PB	283	arm_timer_state *timer[3];
cdbdb648 PB	284	} icp_pit_state;
cdbdb648 PB	285
c227f099	286	static uint32_t icp_pit_read(void *opaque, target_phys_addr_t offset)
cdbdb648 PB	287	{
	288	icp_pit_state s = (icp_pit_state )opaque;
	289	int n;
	290
	291	/* ??? Don't know the PrimeCell ID for this device. */
cdbdb648	292	n = offset >> 8;
2ac71179 PB	293	if (n > 3) {
	294	hw_error("sp804_read: Bad timer %d\n", n);
	295	}
cdbdb648 PB	296
	297	return arm_timer_read(s->timer[n], offset & 0xff);
	298	}
	299
c227f099	300	static void icp_pit_write(void *opaque, target_phys_addr_t offset,
cdbdb648 PB	301	uint32_t value)
	302	{
	303	icp_pit_state s = (icp_pit_state )opaque;
	304	int n;
	305
cdbdb648	306	n = offset >> 8;
2ac71179 PB	307	if (n > 3) {
	308	hw_error("sp804_write: Bad timer %d\n", n);
	309	}
cdbdb648 PB	310
	311	arm_timer_write(s->timer[n], offset & 0xff, value);
	312	}
	313
	314
d60efc6b	315	static CPUReadMemoryFunc * const icp_pit_readfn[] = {
cdbdb648 PB	316	icp_pit_read,
	317	icp_pit_read,
	318	icp_pit_read
	319	};
	320
d60efc6b	321	static CPUWriteMemoryFunc * const icp_pit_writefn[] = {
cdbdb648 PB	322	icp_pit_write,
	323	icp_pit_write,
	324	icp_pit_write
	325	};
	326
81a322d4	327	static int icp_pit_init(SysBusDevice *dev)
cdbdb648 PB	328	{
cdbdb648 PB	329	int iomemtype;
6a824ec3	330	icp_pit_state *s = FROM_SYSBUS(icp_pit_state, dev);
cdbdb648	331
cdbdb648	332	/* Timer 0 runs at the system clock speed (40MHz). */
6a824ec3	333	s->timer[0] = arm_timer_init(40000000);
cdbdb648	334	/* The other two timers run at 1MHz. */
6a824ec3 PB	335	s->timer[1] = arm_timer_init(1000000);
	336	s->timer[2] = arm_timer_init(1000000);
	337
	338	sysbus_init_irq(dev, &s->timer[0]->irq);
	339	sysbus_init_irq(dev, &s->timer[1]->irq);
	340	sysbus_init_irq(dev, &s->timer[2]->irq);
cdbdb648	341
1eed09cb	342	iomemtype = cpu_register_io_memory(icp_pit_readfn,
cdbdb648	343	icp_pit_writefn, s);
6a824ec3	344	sysbus_init_mmio(dev, 0x1000, iomemtype);
23e39294 PB	345	/* This device has no state to save/restore. The component timers will
23e39294 PB	346	save themselves. */
81a322d4	347	return 0;
cdbdb648	348	}
6a824ec3 PB	349
	350	static void arm_timer_register_devices(void)
	351	{
	352	sysbus_register_dev("integrator_pit", sizeof(icp_pit_state), icp_pit_init);
	353	sysbus_register_dev("sp804", sizeof(sp804_state), sp804_init);
	354	}
	355
	356	device_init(arm_timer_register_devices)