[qemu.git] / hw / arm / pxa2xx_gpio.c

/*
 * Intel XScale PXA255/270 GPIO controller emulation.
 *
 * Copyright (c) 2006 Openedhand Ltd.
 * Written by Andrzej Zaborowski <[email protected]>
 *
 * This code is licensed under the GPL.
 */

#include "hw/hw.h"
#include "hw/sysbus.h"
#include "hw/arm/pxa.h"

#define PXA2XX_GPIO_BANKS	4

typedef struct PXA2xxGPIOInfo PXA2xxGPIOInfo;
struct PXA2xxGPIOInfo {
    SysBusDevice busdev;
    MemoryRegion iomem;
    qemu_irq irq0, irq1, irqX;
    int lines;
    int ncpu;
    ARMCPU *cpu;

    /* XXX: GNU C vectors are more suitable */
    uint32_t ilevel[PXA2XX_GPIO_BANKS];
    uint32_t olevel[PXA2XX_GPIO_BANKS];
    uint32_t dir[PXA2XX_GPIO_BANKS];
    uint32_t rising[PXA2XX_GPIO_BANKS];
    uint32_t falling[PXA2XX_GPIO_BANKS];
    uint32_t status[PXA2XX_GPIO_BANKS];
    uint32_t gpsr[PXA2XX_GPIO_BANKS];
    uint32_t gafr[PXA2XX_GPIO_BANKS * 2];

    uint32_t prev_level[PXA2XX_GPIO_BANKS];
    qemu_irq handler[PXA2XX_GPIO_BANKS * 32];
    qemu_irq read_notify;
};

static struct {
    enum {
        GPIO_NONE,
        GPLR,
        GPSR,
        GPCR,
        GPDR,
        GRER,
        GFER,
        GEDR,
        GAFR_L,
        GAFR_U,
    } reg;
    int bank;
} pxa2xx_gpio_regs[0x200] = {
    [0 ... 0x1ff] = { GPIO_NONE, 0 },
#define PXA2XX_REG(reg, a0, a1, a2, a3)	\
    [a0] = { reg, 0 }, [a1] = { reg, 1 }, [a2] = { reg, 2 }, [a3] = { reg, 3 },

    PXA2XX_REG(GPLR, 0x000, 0x004, 0x008, 0x100)
    PXA2XX_REG(GPSR, 0x018, 0x01c, 0x020, 0x118)
    PXA2XX_REG(GPCR, 0x024, 0x028, 0x02c, 0x124)
    PXA2XX_REG(GPDR, 0x00c, 0x010, 0x014, 0x10c)
    PXA2XX_REG(GRER, 0x030, 0x034, 0x038, 0x130)
    PXA2XX_REG(GFER, 0x03c, 0x040, 0x044, 0x13c)
    PXA2XX_REG(GEDR, 0x048, 0x04c, 0x050, 0x148)
    PXA2XX_REG(GAFR_L, 0x054, 0x05c, 0x064, 0x06c)
    PXA2XX_REG(GAFR_U, 0x058, 0x060, 0x068, 0x070)
};

static void pxa2xx_gpio_irq_update(PXA2xxGPIOInfo *s)
{
    if (s->status[0] & (1 << 0))
        qemu_irq_raise(s->irq0);
    else
        qemu_irq_lower(s->irq0);

    if (s->status[0] & (1 << 1))
        qemu_irq_raise(s->irq1);
    else
        qemu_irq_lower(s->irq1);

    if ((s->status[0] & ~3) | s->status[1] | s->status[2] | s->status[3])
        qemu_irq_raise(s->irqX);
    else
        qemu_irq_lower(s->irqX);
}

/* Bitmap of pins used as standby and sleep wake-up sources.  */
static const int pxa2xx_gpio_wake[PXA2XX_GPIO_BANKS] = {
    0x8003fe1b, 0x002001fc, 0xec080000, 0x0012007f,
};

static void pxa2xx_gpio_set(void *opaque, int line, int level)
{
    PXA2xxGPIOInfo *s = (PXA2xxGPIOInfo *) opaque;
    CPUState *cpu = CPU(s->cpu);
    int bank;
    uint32_t mask;

    if (line >= s->lines) {
        printf("%s: No GPIO pin %i\n", __FUNCTION__, line);
        return;
    }

    bank = line >> 5;
    mask = 1 << (line & 31);

    if (level) {
        s->status[bank] |= s->rising[bank] & mask &
                ~s->ilevel[bank] & ~s->dir[bank];
        s->ilevel[bank] |= mask;
    } else {
        s->status[bank] |= s->falling[bank] & mask &
                s->ilevel[bank] & ~s->dir[bank];
        s->ilevel[bank] &= ~mask;
    }

    if (s->status[bank] & mask)
        pxa2xx_gpio_irq_update(s);

    /* Wake-up GPIOs */
    if (cpu->halted && (mask & ~s->dir[bank] & pxa2xx_gpio_wake[bank])) {
        cpu_interrupt(cpu, CPU_INTERRUPT_EXITTB);
    }
}

static void pxa2xx_gpio_handler_update(PXA2xxGPIOInfo *s) {
    uint32_t level, diff;
    int i, bit, line;
    for (i = 0; i < PXA2XX_GPIO_BANKS; i ++) {
        level = s->olevel[i] & s->dir[i];

        for (diff = s->prev_level[i] ^ level; diff; diff ^= 1 << bit) {
            bit = ffs(diff) - 1;
            line = bit + 32 * i;
            qemu_set_irq(s->handler[line], (level >> bit) & 1);
        }

        s->prev_level[i] = level;
    }
}

static uint64_t pxa2xx_gpio_read(void *opaque, hwaddr offset,
                                 unsigned size)
{
    PXA2xxGPIOInfo *s = (PXA2xxGPIOInfo *) opaque;
    uint32_t ret;
    int bank;
    if (offset >= 0x200)
        return 0;

    bank = pxa2xx_gpio_regs[offset].bank;
    switch (pxa2xx_gpio_regs[offset].reg) {
    case GPDR:		/* GPIO Pin-Direction registers */
        return s->dir[bank];

    case GPSR:		/* GPIO Pin-Output Set registers */
        printf("%s: Read from a write-only register " REG_FMT "\n",
                        __FUNCTION__, offset);
        return s->gpsr[bank];	/* Return last written value.  */

    case GPCR:		/* GPIO Pin-Output Clear registers */
        printf("%s: Read from a write-only register " REG_FMT "\n",
                        __FUNCTION__, offset);
        return 31337;		/* Specified as unpredictable in the docs.  */

    case GRER:		/* GPIO Rising-Edge Detect Enable registers */
        return s->rising[bank];

    case GFER:		/* GPIO Falling-Edge Detect Enable registers */
        return s->falling[bank];

    case GAFR_L:	/* GPIO Alternate Function registers */
        return s->gafr[bank * 2];

    case GAFR_U:	/* GPIO Alternate Function registers */
        return s->gafr[bank * 2 + 1];

    case GPLR:		/* GPIO Pin-Level registers */
        ret = (s->olevel[bank] & s->dir[bank]) |
                (s->ilevel[bank] & ~s->dir[bank]);
        qemu_irq_raise(s->read_notify);
        return ret;

    case GEDR:		/* GPIO Edge Detect Status registers */
        return s->status[bank];

    default:
        hw_error("%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset);
    }

    return 0;
}

static void pxa2xx_gpio_write(void *opaque, hwaddr offset,
                              uint64_t value, unsigned size)
{
    PXA2xxGPIOInfo *s = (PXA2xxGPIOInfo *) opaque;
    int bank;
    if (offset >= 0x200)
        return;

    bank = pxa2xx_gpio_regs[offset].bank;
    switch (pxa2xx_gpio_regs[offset].reg) {
    case GPDR:		/* GPIO Pin-Direction registers */
        s->dir[bank] = value;
        pxa2xx_gpio_handler_update(s);
        break;

    case GPSR:		/* GPIO Pin-Output Set registers */
        s->olevel[bank] |= value;
        pxa2xx_gpio_handler_update(s);
        s->gpsr[bank] = value;
        break;

    case GPCR:		/* GPIO Pin-Output Clear registers */
        s->olevel[bank] &= ~value;
        pxa2xx_gpio_handler_update(s);
        break;

    case GRER:		/* GPIO Rising-Edge Detect Enable registers */
        s->rising[bank] = value;
        break;

    case GFER:		/* GPIO Falling-Edge Detect Enable registers */
        s->falling[bank] = value;
        break;

    case GAFR_L:	/* GPIO Alternate Function registers */
        s->gafr[bank * 2] = value;
        break;

    case GAFR_U:	/* GPIO Alternate Function registers */
        s->gafr[bank * 2 + 1] = value;
        break;

    case GEDR:		/* GPIO Edge Detect Status registers */
        s->status[bank] &= ~value;
        pxa2xx_gpio_irq_update(s);
        break;

    default:
        hw_error("%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset);
    }
}

static const MemoryRegionOps pxa_gpio_ops = {
    .read = pxa2xx_gpio_read,
    .write = pxa2xx_gpio_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
};

DeviceState *pxa2xx_gpio_init(hwaddr base,
                              ARMCPU *cpu, DeviceState *pic, int lines)
{
    CPUState *cs = CPU(cpu);
    DeviceState *dev;

    dev = qdev_create(NULL, "pxa2xx-gpio");
    qdev_prop_set_int32(dev, "lines", lines);
    qdev_prop_set_int32(dev, "ncpu", cs->cpu_index);
    qdev_init_nofail(dev);

    sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
    sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0,
                    qdev_get_gpio_in(pic, PXA2XX_PIC_GPIO_0));
    sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1,
                    qdev_get_gpio_in(pic, PXA2XX_PIC_GPIO_1));
    sysbus_connect_irq(SYS_BUS_DEVICE(dev), 2,
                    qdev_get_gpio_in(pic, PXA2XX_PIC_GPIO_X));

    return dev;
}

static int pxa2xx_gpio_initfn(SysBusDevice *dev)
{
    PXA2xxGPIOInfo *s;

    s = FROM_SYSBUS(PXA2xxGPIOInfo, dev);

    s->cpu = ARM_CPU(qemu_get_cpu(s->ncpu));

    qdev_init_gpio_in(&dev->qdev, pxa2xx_gpio_set, s->lines);
    qdev_init_gpio_out(&dev->qdev, s->handler, s->lines);

    memory_region_init_io(&s->iomem, &pxa_gpio_ops, s, "pxa2xx-gpio", 0x1000);
    sysbus_init_mmio(dev, &s->iomem);
    sysbus_init_irq(dev, &s->irq0);
    sysbus_init_irq(dev, &s->irq1);
    sysbus_init_irq(dev, &s->irqX);

    return 0;
}

/*
 * Registers a callback to notify on GPLR reads.  This normally
 * shouldn't be needed but it is used for the hack on Spitz machines.
 */
void pxa2xx_gpio_read_notifier(DeviceState *dev, qemu_irq handler)
{
    PXA2xxGPIOInfo *s = FROM_SYSBUS(PXA2xxGPIOInfo, SYS_BUS_DEVICE(dev));
    s->read_notify = handler;
}

static const VMStateDescription vmstate_pxa2xx_gpio_regs = {
    .name = "pxa2xx-gpio",
    .version_id = 1,
    .minimum_version_id = 1,
    .minimum_version_id_old = 1,
    .fields = (VMStateField []) {
        VMSTATE_INT32(lines, PXA2xxGPIOInfo),
        VMSTATE_UINT32_ARRAY(ilevel, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
        VMSTATE_UINT32_ARRAY(olevel, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
        VMSTATE_UINT32_ARRAY(dir, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
        VMSTATE_UINT32_ARRAY(rising, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
        VMSTATE_UINT32_ARRAY(falling, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
        VMSTATE_UINT32_ARRAY(status, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
        VMSTATE_UINT32_ARRAY(gafr, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS * 2),
        VMSTATE_END_OF_LIST(),
    },
};

static Property pxa2xx_gpio_properties[] = {
    DEFINE_PROP_INT32("lines", PXA2xxGPIOInfo, lines, 0),
    DEFINE_PROP_INT32("ncpu", PXA2xxGPIOInfo, ncpu, 0),
    DEFINE_PROP_END_OF_LIST(),
};

static void pxa2xx_gpio_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);
    SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);

    k->init = pxa2xx_gpio_initfn;
    dc->desc = "PXA2xx GPIO controller";
    dc->props = pxa2xx_gpio_properties;
}

static const TypeInfo pxa2xx_gpio_info = {
    .name          = "pxa2xx-gpio",
    .parent        = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(PXA2xxGPIOInfo),
    .class_init    = pxa2xx_gpio_class_init,
};

static void pxa2xx_gpio_register_types(void)
{
    type_register_static(&pxa2xx_gpio_info);
}

type_init(pxa2xx_gpio_register_types)
Commit	Line	Data
c1713132 AZ	1	/*
	2	* Intel XScale PXA255/270 GPIO controller emulation.
	3	*
	4	* Copyright (c) 2006 Openedhand Ltd.
	5	* Written by Andrzej Zaborowski <[email protected]>
	6	*
	7	* This code is licensed under the GPL.
	8	*/
	9
83c9f4ca PB	10	#include "hw/hw.h"
83c9f4ca PB	11	#include "hw/sysbus.h"
0d09e41a	12	#include "hw/arm/pxa.h"
c1713132 AZ	13
	14	#define PXA2XX_GPIO_BANKS 4
	15
0bb53337	16	typedef struct PXA2xxGPIOInfo PXA2xxGPIOInfo;
bc24a225	17	struct PXA2xxGPIOInfo {
0bb53337	18	SysBusDevice busdev;
55a8b801	19	MemoryRegion iomem;
0bb53337	20	qemu_irq irq0, irq1, irqX;
c1713132	21	int lines;
0bb53337	22	int ncpu;
95d42bb5	23	ARMCPU *cpu;
c1713132 AZ	24
	25	/* XXX: GNU C vectors are more suitable */
	26	uint32_t ilevel[PXA2XX_GPIO_BANKS];
	27	uint32_t olevel[PXA2XX_GPIO_BANKS];
	28	uint32_t dir[PXA2XX_GPIO_BANKS];
	29	uint32_t rising[PXA2XX_GPIO_BANKS];
	30	uint32_t falling[PXA2XX_GPIO_BANKS];
	31	uint32_t status[PXA2XX_GPIO_BANKS];
2b76bdc9	32	uint32_t gpsr[PXA2XX_GPIO_BANKS];
c1713132 AZ	33	uint32_t gafr[PXA2XX_GPIO_BANKS * 2];
	34
	35	uint32_t prev_level[PXA2XX_GPIO_BANKS];
38641a52 AZ	36	qemu_irq handler[PXA2XX_GPIO_BANKS * 32];
38641a52 AZ	37	qemu_irq read_notify;
c1713132 AZ	38	};
	39
	40	static struct {
	41	enum {
	42	GPIO_NONE,
	43	GPLR,
	44	GPSR,
	45	GPCR,
	46	GPDR,
	47	GRER,
	48	GFER,
	49	GEDR,
	50	GAFR_L,
	51	GAFR_U,
	52	} reg;
	53	int bank;
	54	} pxa2xx_gpio_regs[0x200] = {
	55	[0 ... 0x1ff] = { GPIO_NONE, 0 },
	56	#define PXA2XX_REG(reg, a0, a1, a2, a3) \
5fafdf24	57	[a0] = { reg, 0 }, [a1] = { reg, 1 }, [a2] = { reg, 2 }, [a3] = { reg, 3 },
c1713132 AZ	58
	59	PXA2XX_REG(GPLR, 0x000, 0x004, 0x008, 0x100)
	60	PXA2XX_REG(GPSR, 0x018, 0x01c, 0x020, 0x118)
	61	PXA2XX_REG(GPCR, 0x024, 0x028, 0x02c, 0x124)
	62	PXA2XX_REG(GPDR, 0x00c, 0x010, 0x014, 0x10c)
	63	PXA2XX_REG(GRER, 0x030, 0x034, 0x038, 0x130)
	64	PXA2XX_REG(GFER, 0x03c, 0x040, 0x044, 0x13c)
	65	PXA2XX_REG(GEDR, 0x048, 0x04c, 0x050, 0x148)
	66	PXA2XX_REG(GAFR_L, 0x054, 0x05c, 0x064, 0x06c)
	67	PXA2XX_REG(GAFR_U, 0x058, 0x060, 0x068, 0x070)
	68	};
	69
bc24a225	70	static void pxa2xx_gpio_irq_update(PXA2xxGPIOInfo *s)
c1713132 AZ	71	{
c1713132 AZ	72	if (s->status[0] & (1 << 0))
0bb53337	73	qemu_irq_raise(s->irq0);
c1713132	74	else
0bb53337	75	qemu_irq_lower(s->irq0);
c1713132 AZ	76
c1713132 AZ	77	if (s->status[0] & (1 << 1))
0bb53337	78	qemu_irq_raise(s->irq1);
c1713132	79	else
0bb53337	80	qemu_irq_lower(s->irq1);
c1713132 AZ	81
c1713132 AZ	82	if ((s->status[0] & ~3) \| s->status[1] \| s->status[2] \| s->status[3])
0bb53337	83	qemu_irq_raise(s->irqX);
c1713132	84	else
0bb53337	85	qemu_irq_lower(s->irqX);
c1713132 AZ	86	}
	87
	88	/* Bitmap of pins used as standby and sleep wake-up sources. */
38641a52	89	static const int pxa2xx_gpio_wake[PXA2XX_GPIO_BANKS] = {
c1713132 AZ	90	0x8003fe1b, 0x002001fc, 0xec080000, 0x0012007f,
	91	};
	92
38641a52	93	static void pxa2xx_gpio_set(void *opaque, int line, int level)
c1713132	94	{
bc24a225	95	PXA2xxGPIOInfo s = (PXA2xxGPIOInfo ) opaque;
259186a7	96	CPUState *cpu = CPU(s->cpu);
c1713132 AZ	97	int bank;
	98	uint32_t mask;
	99
	100	if (line >= s->lines) {
	101	printf("%s: No GPIO pin %i\n", __FUNCTION__, line);
	102	return;
	103	}
	104
	105	bank = line >> 5;
	106	mask = 1 << (line & 31);
	107
	108	if (level) {
	109	s->status[bank] \|= s->rising[bank] & mask &
	110	~s->ilevel[bank] & ~s->dir[bank];
	111	s->ilevel[bank] \|= mask;
	112	} else {
	113	s->status[bank] \|= s->falling[bank] & mask &
	114	s->ilevel[bank] & ~s->dir[bank];
	115	s->ilevel[bank] &= ~mask;
	116	}
	117
	118	if (s->status[bank] & mask)
	119	pxa2xx_gpio_irq_update(s);
	120
	121	/* Wake-up GPIOs */
259186a7	122	if (cpu->halted && (mask & ~s->dir[bank] & pxa2xx_gpio_wake[bank])) {
c3affe56	123	cpu_interrupt(cpu, CPU_INTERRUPT_EXITTB);
95d42bb5	124	}
c1713132 AZ	125	}
c1713132 AZ	126
bc24a225	127	static void pxa2xx_gpio_handler_update(PXA2xxGPIOInfo *s) {
c1713132 AZ	128	uint32_t level, diff;
	129	int i, bit, line;
	130	for (i = 0; i < PXA2XX_GPIO_BANKS; i ++) {
	131	level = s->olevel[i] & s->dir[i];
	132
	133	for (diff = s->prev_level[i] ^ level; diff; diff ^= 1 << bit) {
	134	bit = ffs(diff) - 1;
	135	line = bit + 32 * i;
38641a52	136	qemu_set_irq(s->handler[line], (level >> bit) & 1);
c1713132 AZ	137	}
	138
	139	s->prev_level[i] = level;
	140	}
	141	}
	142
a8170e5e	143	static uint64_t pxa2xx_gpio_read(void *opaque, hwaddr offset,
55a8b801	144	unsigned size)
c1713132	145	{
bc24a225	146	PXA2xxGPIOInfo s = (PXA2xxGPIOInfo ) opaque;
c1713132 AZ	147	uint32_t ret;
c1713132 AZ	148	int bank;
c1713132 AZ	149	if (offset >= 0x200)
	150	return 0;
	151
	152	bank = pxa2xx_gpio_regs[offset].bank;
	153	switch (pxa2xx_gpio_regs[offset].reg) {
	154	case GPDR: /* GPIO Pin-Direction registers */
	155	return s->dir[bank];
	156
2b76bdc9 AZ	157	case GPSR: /* GPIO Pin-Output Set registers */
	158	printf("%s: Read from a write-only register " REG_FMT "\n",
	159	__FUNCTION__, offset);
	160	return s->gpsr[bank]; /* Return last written value. */
	161
e1dad5a6 AZ	162	case GPCR: /* GPIO Pin-Output Clear registers */
	163	printf("%s: Read from a write-only register " REG_FMT "\n",
	164	__FUNCTION__, offset);
	165	return 31337; /* Specified as unpredictable in the docs. */
	166
c1713132 AZ	167	case GRER: /* GPIO Rising-Edge Detect Enable registers */
	168	return s->rising[bank];
	169
	170	case GFER: /* GPIO Falling-Edge Detect Enable registers */
	171	return s->falling[bank];
	172
	173	case GAFR_L: /* GPIO Alternate Function registers */
	174	return s->gafr[bank * 2];
	175
	176	case GAFR_U: /* GPIO Alternate Function registers */
	177	return s->gafr[bank * 2 + 1];
	178
	179	case GPLR: /* GPIO Pin-Level registers */
	180	ret = (s->olevel[bank] & s->dir[bank]) \|
	181	(s->ilevel[bank] & ~s->dir[bank]);
38641a52	182	qemu_irq_raise(s->read_notify);
c1713132 AZ	183	return ret;
	184
	185	case GEDR: /* GPIO Edge Detect Status registers */
	186	return s->status[bank];
	187
	188	default:
2ac71179	189	hw_error("%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset);
c1713132 AZ	190	}
	191
	192	return 0;
	193	}
	194
a8170e5e	195	static void pxa2xx_gpio_write(void *opaque, hwaddr offset,
55a8b801	196	uint64_t value, unsigned size)
c1713132	197	{
bc24a225	198	PXA2xxGPIOInfo s = (PXA2xxGPIOInfo ) opaque;
c1713132	199	int bank;
c1713132 AZ	200	if (offset >= 0x200)
	201	return;
	202
	203	bank = pxa2xx_gpio_regs[offset].bank;
	204	switch (pxa2xx_gpio_regs[offset].reg) {
	205	case GPDR: /* GPIO Pin-Direction registers */
	206	s->dir[bank] = value;
	207	pxa2xx_gpio_handler_update(s);
	208	break;
	209
	210	case GPSR: /* GPIO Pin-Output Set registers */
	211	s->olevel[bank] \|= value;
	212	pxa2xx_gpio_handler_update(s);
2b76bdc9	213	s->gpsr[bank] = value;
c1713132 AZ	214	break;
	215
	216	case GPCR: /* GPIO Pin-Output Clear registers */
	217	s->olevel[bank] &= ~value;
	218	pxa2xx_gpio_handler_update(s);
	219	break;
	220
	221	case GRER: /* GPIO Rising-Edge Detect Enable registers */
	222	s->rising[bank] = value;
	223	break;
	224
	225	case GFER: /* GPIO Falling-Edge Detect Enable registers */
	226	s->falling[bank] = value;
	227	break;
	228
	229	case GAFR_L: /* GPIO Alternate Function registers */
	230	s->gafr[bank * 2] = value;
	231	break;
	232
	233	case GAFR_U: /* GPIO Alternate Function registers */
	234	s->gafr[bank * 2 + 1] = value;
	235	break;
	236
	237	case GEDR: /* GPIO Edge Detect Status registers */
	238	s->status[bank] &= ~value;
	239	pxa2xx_gpio_irq_update(s);
	240	break;
	241
	242	default:
2ac71179	243	hw_error("%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset);
c1713132 AZ	244	}
	245	}
	246
55a8b801 BC	247	static const MemoryRegionOps pxa_gpio_ops = {
	248	.read = pxa2xx_gpio_read,
	249	.write = pxa2xx_gpio_write,
	250	.endianness = DEVICE_NATIVE_ENDIAN,
c1713132 AZ	251	};
c1713132 AZ	252
a8170e5e	253	DeviceState *pxa2xx_gpio_init(hwaddr base,
55e5c285	254	ARMCPU cpu, DeviceState pic, int lines)
aa941b94	255	{
55e5c285	256	CPUState *cs = CPU(cpu);
0bb53337	257	DeviceState *dev;
aa941b94	258
0bb53337 DES	259	dev = qdev_create(NULL, "pxa2xx-gpio");
0bb53337 DES	260	qdev_prop_set_int32(dev, "lines", lines);
55e5c285	261	qdev_prop_set_int32(dev, "ncpu", cs->cpu_index);
0bb53337	262	qdev_init_nofail(dev);
aa941b94	263
1356b98d AF	264	sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
1356b98d AF	265	sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0,
e1f8c729	266	qdev_get_gpio_in(pic, PXA2XX_PIC_GPIO_0));
1356b98d	267	sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1,
e1f8c729	268	qdev_get_gpio_in(pic, PXA2XX_PIC_GPIO_1));
1356b98d	269	sysbus_connect_irq(SYS_BUS_DEVICE(dev), 2,
e1f8c729	270	qdev_get_gpio_in(pic, PXA2XX_PIC_GPIO_X));
aa941b94	271
0bb53337	272	return dev;
aa941b94 AZ	273	}
aa941b94 AZ	274
0bb53337	275	static int pxa2xx_gpio_initfn(SysBusDevice *dev)
c1713132	276	{
bc24a225	277	PXA2xxGPIOInfo *s;
c1713132	278
0bb53337	279	s = FROM_SYSBUS(PXA2xxGPIOInfo, dev);
c1713132	280
38d8f5c8	281	s->cpu = ARM_CPU(qemu_get_cpu(s->ncpu));
c1713132	282
0bb53337 DES	283	qdev_init_gpio_in(&dev->qdev, pxa2xx_gpio_set, s->lines);
0bb53337 DES	284	qdev_init_gpio_out(&dev->qdev, s->handler, s->lines);
c1713132	285
55a8b801	286	memory_region_init_io(&s->iomem, &pxa_gpio_ops, s, "pxa2xx-gpio", 0x1000);
750ecd44	287	sysbus_init_mmio(dev, &s->iomem);
0bb53337 DES	288	sysbus_init_irq(dev, &s->irq0);
	289	sysbus_init_irq(dev, &s->irq1);
	290	sysbus_init_irq(dev, &s->irqX);
c1713132	291
0bb53337	292	return 0;
c1713132 AZ	293	}
	294
	295	/*
	296	* Registers a callback to notify on GPLR reads. This normally
	297	* shouldn't be needed but it is used for the hack on Spitz machines.
	298	*/
0bb53337	299	void pxa2xx_gpio_read_notifier(DeviceState *dev, qemu_irq handler)
38641a52	300	{
1356b98d	301	PXA2xxGPIOInfo *s = FROM_SYSBUS(PXA2xxGPIOInfo, SYS_BUS_DEVICE(dev));
c1713132	302	s->read_notify = handler;
c1713132	303	}
0bb53337 DES	304
	305	static const VMStateDescription vmstate_pxa2xx_gpio_regs = {
	306	.name = "pxa2xx-gpio",
	307	.version_id = 1,
	308	.minimum_version_id = 1,
	309	.minimum_version_id_old = 1,
	310	.fields = (VMStateField []) {
	311	VMSTATE_INT32(lines, PXA2xxGPIOInfo),
	312	VMSTATE_UINT32_ARRAY(ilevel, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
	313	VMSTATE_UINT32_ARRAY(olevel, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
	314	VMSTATE_UINT32_ARRAY(dir, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
	315	VMSTATE_UINT32_ARRAY(rising, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
	316	VMSTATE_UINT32_ARRAY(falling, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
	317	VMSTATE_UINT32_ARRAY(status, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
	318	VMSTATE_UINT32_ARRAY(gafr, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS * 2),
	319	VMSTATE_END_OF_LIST(),
	320	},
	321	};
	322
999e12bb AL	323	static Property pxa2xx_gpio_properties[] = {
	324	DEFINE_PROP_INT32("lines", PXA2xxGPIOInfo, lines, 0),
	325	DEFINE_PROP_INT32("ncpu", PXA2xxGPIOInfo, ncpu, 0),
	326	DEFINE_PROP_END_OF_LIST(),
	327	};
	328
	329	static void pxa2xx_gpio_class_init(ObjectClass klass, void data)
	330	{
39bffca2	331	DeviceClass *dc = DEVICE_CLASS(klass);
999e12bb AL	332	SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
	333
	334	k->init = pxa2xx_gpio_initfn;
39bffca2 AL	335	dc->desc = "PXA2xx GPIO controller";
39bffca2 AL	336	dc->props = pxa2xx_gpio_properties;
999e12bb AL	337	}
999e12bb AL	338
8c43a6f0	339	static const TypeInfo pxa2xx_gpio_info = {
39bffca2 AL	340	.name = "pxa2xx-gpio",
	341	.parent = TYPE_SYS_BUS_DEVICE,
	342	.instance_size = sizeof(PXA2xxGPIOInfo),
	343	.class_init = pxa2xx_gpio_class_init,
0bb53337 DES	344	};
0bb53337 DES	345
83f7d43a	346	static void pxa2xx_gpio_register_types(void)
0bb53337	347	{
39bffca2	348	type_register_static(&pxa2xx_gpio_info);
0bb53337	349	}
83f7d43a AF	350
83f7d43a AF	351	type_init(pxa2xx_gpio_register_types)