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[qemu.git] / target-s390x / fpu_helper.c
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e72ca652
BS		 1/*
2 * S/390 FPU helper routines
3 *
4 * Copyright (c) 2009 Ulrich Hecht
5 * Copyright (c) 2009 Alexander Graf
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21#include "cpu.h"
e72ca652
BS		 22#include "helper.h"
23
19b0516f 24#if !defined(CONFIG_USER_ONLY)
e72ca652
BS		 25#include "softmmu_exec.h"
26#endif
27
28/* #define DEBUG_HELPER */
29#ifdef DEBUG_HELPER
30#define HELPER_LOG(x...) qemu_log(x)
31#else
32#define HELPER_LOG(x...)
33#endif
34
449c0d70 35static inline int float_comp_to_cc(CPUS390XState *env, int float_compare)
e72ca652
BS		 36{
37 switch (float_compare) {
38 case float_relation_equal:
39 return 0;
40 case float_relation_less:
41 return 1;
42 case float_relation_greater:
43 return 2;
44 case float_relation_unordered:
45 return 3;
46 default:
47 cpu_abort(env, "unknown return value for float compare\n");
48 }
49}
50
51/* condition codes for binary FP ops */
449c0d70 52uint32_t set_cc_f32(CPUS390XState *env, float32 v1, float32 v2)
e72ca652 53{
449c0d70
BS		 54 return float_comp_to_cc(env, float32_compare_quiet(v1, v2,
55 &env->fpu_status));
e72ca652
BS		 56}
57
449c0d70 58uint32_t set_cc_f64(CPUS390XState *env, float64 v1, float64 v2)
e72ca652 59{
449c0d70
BS		 60 return float_comp_to_cc(env, float64_compare_quiet(v1, v2,
61 &env->fpu_status));
e72ca652
BS		 62}
63
64/* condition codes for unary FP ops */
65uint32_t set_cc_nz_f32(float32 v)
66{
67 if (float32_is_any_nan(v)) {
68 return 3;
69 } else if (float32_is_zero(v)) {
70 return 0;
71 } else if (float32_is_neg(v)) {
72 return 1;
73 } else {
74 return 2;
75 }
76}
77
78uint32_t set_cc_nz_f64(float64 v)
79{
80 if (float64_is_any_nan(v)) {
81 return 3;
82 } else if (float64_is_zero(v)) {
83 return 0;
84 } else if (float64_is_neg(v)) {
85 return 1;
86 } else {
87 return 2;
88 }
89}
90
91static uint32_t set_cc_nz_f128(float128 v)
92{
93 if (float128_is_any_nan(v)) {
94 return 3;
95 } else if (float128_is_zero(v)) {
96 return 0;
97 } else if (float128_is_neg(v)) {
98 return 1;
99 } else {
100 return 2;
101 }
102}
103
104/* convert 32-bit int to 64-bit float */
449c0d70 105void HELPER(cdfbr)(CPUS390XState *env, uint32_t f1, int32_t v2)
e72ca652
BS		 106{
107 HELPER_LOG("%s: converting %d to f%d\n", __func__, v2, f1);
108 env->fregs[f1].d = int32_to_float64(v2, &env->fpu_status);
109}
110
111/* convert 32-bit int to 128-bit float */
449c0d70 112void HELPER(cxfbr)(CPUS390XState *env, uint32_t f1, int32_t v2)
e72ca652
BS		 113{
114 CPU_QuadU v1;
115
116 v1.q = int32_to_float128(v2, &env->fpu_status);
117 env->fregs[f1].ll = v1.ll.upper;
118 env->fregs[f1 + 2].ll = v1.ll.lower;
119}
120
121/* convert 64-bit int to 32-bit float */
449c0d70 122void HELPER(cegbr)(CPUS390XState *env, uint32_t f1, int64_t v2)
e72ca652
BS		 123{
124 HELPER_LOG("%s: converting %ld to f%d\n", __func__, v2, f1);
125 env->fregs[f1].l.upper = int64_to_float32(v2, &env->fpu_status);
126}
127
128/* convert 64-bit int to 64-bit float */
449c0d70 129void HELPER(cdgbr)(CPUS390XState *env, uint32_t f1, int64_t v2)
e72ca652
BS		 130{
131 HELPER_LOG("%s: converting %ld to f%d\n", __func__, v2, f1);
132 env->fregs[f1].d = int64_to_float64(v2, &env->fpu_status);
133}
134
135/* convert 64-bit int to 128-bit float */
449c0d70 136void HELPER(cxgbr)(CPUS390XState *env, uint32_t f1, int64_t v2)
e72ca652
BS		 137{
138 CPU_QuadU x1;
139
140 x1.q = int64_to_float128(v2, &env->fpu_status);
141 HELPER_LOG("%s: converted %ld to 0x%lx and 0x%lx\n", __func__, v2,
142 x1.ll.upper, x1.ll.lower);
143 env->fregs[f1].ll = x1.ll.upper;
144 env->fregs[f1 + 2].ll = x1.ll.lower;
145}
146
147/* convert 32-bit int to 32-bit float */
449c0d70 148void HELPER(cefbr)(CPUS390XState *env, uint32_t f1, int32_t v2)
e72ca652
BS		 149{
150 env->fregs[f1].l.upper = int32_to_float32(v2, &env->fpu_status);
151 HELPER_LOG("%s: converting %d to 0x%d in f%d\n", __func__, v2,
152 env->fregs[f1].l.upper, f1);
153}
154
155/* 32-bit FP addition RR */
449c0d70 156uint32_t HELPER(aebr)(CPUS390XState *env, uint32_t f1, uint32_t f2)
e72ca652
BS		 157{
158 env->fregs[f1].l.upper = float32_add(env->fregs[f1].l.upper,
159 env->fregs[f2].l.upper,
160 &env->fpu_status);
161 HELPER_LOG("%s: adding 0x%d resulting in 0x%d in f%d\n", __func__,
162 env->fregs[f2].l.upper, env->fregs[f1].l.upper, f1);
163
164 return set_cc_nz_f32(env->fregs[f1].l.upper);
165}
166
167/* 64-bit FP addition RR */
449c0d70 168uint32_t HELPER(adbr)(CPUS390XState *env, uint32_t f1, uint32_t f2)
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BS		 169{
170 env->fregs[f1].d = float64_add(env->fregs[f1].d, env->fregs[f2].d,
171 &env->fpu_status);
172 HELPER_LOG("%s: adding 0x%ld resulting in 0x%ld in f%d\n", __func__,
173 env->fregs[f2].d, env->fregs[f1].d, f1);
174
175 return set_cc_nz_f64(env->fregs[f1].d);
176}
177
178/* 32-bit FP subtraction RR */
449c0d70 179uint32_t HELPER(sebr)(CPUS390XState *env, uint32_t f1, uint32_t f2)
e72ca652
BS		 180{
181 env->fregs[f1].l.upper = float32_sub(env->fregs[f1].l.upper,
182 env->fregs[f2].l.upper,
183 &env->fpu_status);
184 HELPER_LOG("%s: adding 0x%d resulting in 0x%d in f%d\n", __func__,
185 env->fregs[f2].l.upper, env->fregs[f1].l.upper, f1);
186
187 return set_cc_nz_f32(env->fregs[f1].l.upper);
188}
189
190/* 64-bit FP subtraction RR */
449c0d70 191uint32_t HELPER(sdbr)(CPUS390XState *env, uint32_t f1, uint32_t f2)
e72ca652
BS		 192{
193 env->fregs[f1].d = float64_sub(env->fregs[f1].d, env->fregs[f2].d,
194 &env->fpu_status);
195 HELPER_LOG("%s: subtracting 0x%ld resulting in 0x%ld in f%d\n",
196 __func__, env->fregs[f2].d, env->fregs[f1].d, f1);
197
198 return set_cc_nz_f64(env->fregs[f1].d);
199}
200
201/* 32-bit FP division RR */
449c0d70 202void HELPER(debr)(CPUS390XState *env, uint32_t f1, uint32_t f2)
e72ca652
BS		 203{
204 env->fregs[f1].l.upper = float32_div(env->fregs[f1].l.upper,
205 env->fregs[f2].l.upper,
206 &env->fpu_status);
207}
208
209/* 128-bit FP division RR */
449c0d70 210void HELPER(dxbr)(CPUS390XState *env, uint32_t f1, uint32_t f2)
e72ca652
BS		 211{
212 CPU_QuadU v1;
213 CPU_QuadU v2;
214 CPU_QuadU res;
215
216 v1.ll.upper = env->fregs[f1].ll;
217 v1.ll.lower = env->fregs[f1 + 2].ll;
218 v2.ll.upper = env->fregs[f2].ll;
219 v2.ll.lower = env->fregs[f2 + 2].ll;
220 res.q = float128_div(v1.q, v2.q, &env->fpu_status);
221 env->fregs[f1].ll = res.ll.upper;
222 env->fregs[f1 + 2].ll = res.ll.lower;
223}
224
225/* 64-bit FP multiplication RR */
449c0d70 226void HELPER(mdbr)(CPUS390XState *env, uint32_t f1, uint32_t f2)
e72ca652
BS		 227{
228 env->fregs[f1].d = float64_mul(env->fregs[f1].d, env->fregs[f2].d,
229 &env->fpu_status);
230}
231
232/* 128-bit FP multiplication RR */
449c0d70 233void HELPER(mxbr)(CPUS390XState *env, uint32_t f1, uint32_t f2)
e72ca652
BS		 234{
235 CPU_QuadU v1;
236 CPU_QuadU v2;
237 CPU_QuadU res;
238
239 v1.ll.upper = env->fregs[f1].ll;
240 v1.ll.lower = env->fregs[f1 + 2].ll;
241 v2.ll.upper = env->fregs[f2].ll;
242 v2.ll.lower = env->fregs[f2 + 2].ll;
243 res.q = float128_mul(v1.q, v2.q, &env->fpu_status);
244 env->fregs[f1].ll = res.ll.upper;
245 env->fregs[f1 + 2].ll = res.ll.lower;
246}
247
248/* convert 32-bit float to 64-bit float */
449c0d70 249void HELPER(ldebr)(CPUS390XState *env, uint32_t r1, uint32_t r2)
e72ca652
BS		 250{
251 env->fregs[r1].d = float32_to_float64(env->fregs[r2].l.upper,
252 &env->fpu_status);
253}
254
255/* convert 128-bit float to 64-bit float */
449c0d70 256void HELPER(ldxbr)(CPUS390XState *env, uint32_t f1, uint32_t f2)
e72ca652
BS		 257{
258 CPU_QuadU x2;
259
260 x2.ll.upper = env->fregs[f2].ll;
261 x2.ll.lower = env->fregs[f2 + 2].ll;
262 env->fregs[f1].d = float128_to_float64(x2.q, &env->fpu_status);
263 HELPER_LOG("%s: to 0x%ld\n", __func__, env->fregs[f1].d);
264}
265
266/* convert 64-bit float to 128-bit float */
449c0d70 267void HELPER(lxdbr)(CPUS390XState *env, uint32_t f1, uint32_t f2)
e72ca652
BS		 268{
269 CPU_QuadU res;
270
271 res.q = float64_to_float128(env->fregs[f2].d, &env->fpu_status);
272 env->fregs[f1].ll = res.ll.upper;
273 env->fregs[f1 + 2].ll = res.ll.lower;
274}
275
276/* convert 64-bit float to 32-bit float */
449c0d70 277void HELPER(ledbr)(CPUS390XState *env, uint32_t f1, uint32_t f2)
e72ca652
BS		 278{
279 float64 d2 = env->fregs[f2].d;
280
281 env->fregs[f1].l.upper = float64_to_float32(d2, &env->fpu_status);
282}
283
284/* convert 128-bit float to 32-bit float */
449c0d70 285void HELPER(lexbr)(CPUS390XState *env, uint32_t f1, uint32_t f2)
e72ca652
BS		 286{
287 CPU_QuadU x2;
288
289 x2.ll.upper = env->fregs[f2].ll;
290 x2.ll.lower = env->fregs[f2 + 2].ll;
291 env->fregs[f1].l.upper = float128_to_float32(x2.q, &env->fpu_status);
292 HELPER_LOG("%s: to 0x%d\n", __func__, env->fregs[f1].l.upper);
293}
294
295/* absolute value of 32-bit float */
449c0d70 296uint32_t HELPER(lpebr)(CPUS390XState *env, uint32_t f1, uint32_t f2)
e72ca652
BS		 297{
298 float32 v1;
299 float32 v2 = env->fregs[f2].d;
300
301 v1 = float32_abs(v2);
302 env->fregs[f1].d = v1;
303 return set_cc_nz_f32(v1);
304}
305
306/* absolute value of 64-bit float */
449c0d70 307uint32_t HELPER(lpdbr)(CPUS390XState *env, uint32_t f1, uint32_t f2)
e72ca652
BS		 308{
309 float64 v1;
310 float64 v2 = env->fregs[f2].d;
311
312 v1 = float64_abs(v2);
313 env->fregs[f1].d = v1;
314 return set_cc_nz_f64(v1);
315}
316
317/* absolute value of 128-bit float */
449c0d70 318uint32_t HELPER(lpxbr)(CPUS390XState *env, uint32_t f1, uint32_t f2)
e72ca652
BS		 319{
320 CPU_QuadU v1;
321 CPU_QuadU v2;
322
323 v2.ll.upper = env->fregs[f2].ll;
324 v2.ll.lower = env->fregs[f2 + 2].ll;
325 v1.q = float128_abs(v2.q);
326 env->fregs[f1].ll = v1.ll.upper;
327 env->fregs[f1 + 2].ll = v1.ll.lower;
328 return set_cc_nz_f128(v1.q);
329}
330
331/* load and test 64-bit float */
449c0d70 332uint32_t HELPER(ltdbr)(CPUS390XState *env, uint32_t f1, uint32_t f2)
e72ca652
BS		 333{
334 env->fregs[f1].d = env->fregs[f2].d;
335 return set_cc_nz_f64(env->fregs[f1].d);
336}
337
338/* load and test 32-bit float */
449c0d70 339uint32_t HELPER(ltebr)(CPUS390XState *env, uint32_t f1, uint32_t f2)
e72ca652
BS		 340{
341 env->fregs[f1].l.upper = env->fregs[f2].l.upper;
342 return set_cc_nz_f32(env->fregs[f1].l.upper);
343}
344
345/* load and test 128-bit float */
449c0d70 346uint32_t HELPER(ltxbr)(CPUS390XState *env, uint32_t f1, uint32_t f2)
e72ca652
BS		 347{
348 CPU_QuadU x;
349
350 x.ll.upper = env->fregs[f2].ll;
351 x.ll.lower = env->fregs[f2 + 2].ll;
352 env->fregs[f1].ll = x.ll.upper;
353 env->fregs[f1 + 2].ll = x.ll.lower;
354 return set_cc_nz_f128(x.q);
355}
356
357/* load complement of 32-bit float */
449c0d70 358uint32_t HELPER(lcebr)(CPUS390XState *env, uint32_t f1, uint32_t f2)
e72ca652
BS		 359{
360 env->fregs[f1].l.upper = float32_chs(env->fregs[f2].l.upper);
361
362 return set_cc_nz_f32(env->fregs[f1].l.upper);
363}
364
365/* load complement of 64-bit float */
449c0d70 366uint32_t HELPER(lcdbr)(CPUS390XState *env, uint32_t f1, uint32_t f2)
e72ca652
BS		 367{
368 env->fregs[f1].d = float64_chs(env->fregs[f2].d);
369
370 return set_cc_nz_f64(env->fregs[f1].d);
371}
372
373/* load complement of 128-bit float */
449c0d70 374uint32_t HELPER(lcxbr)(CPUS390XState *env, uint32_t f1, uint32_t f2)
e72ca652
BS		 375{
376 CPU_QuadU x1, x2;
377
378 x2.ll.upper = env->fregs[f2].ll;
379 x2.ll.lower = env->fregs[f2 + 2].ll;
380 x1.q = float128_chs(x2.q);
381 env->fregs[f1].ll = x1.ll.upper;
382 env->fregs[f1 + 2].ll = x1.ll.lower;
383 return set_cc_nz_f128(x1.q);
384}
385
386/* 32-bit FP addition RM */
449c0d70 387void HELPER(aeb)(CPUS390XState *env, uint32_t f1, uint32_t val)
e72ca652
BS		 388{
389 float32 v1 = env->fregs[f1].l.upper;
390 CPU_FloatU v2;
391
392 v2.l = val;
393 HELPER_LOG("%s: adding 0x%d from f%d and 0x%d\n", __func__,
394 v1, f1, v2.f);
395 env->fregs[f1].l.upper = float32_add(v1, v2.f, &env->fpu_status);
396}
397
398/* 32-bit FP division RM */
449c0d70 399void HELPER(deb)(CPUS390XState *env, uint32_t f1, uint32_t val)
e72ca652
BS		 400{
401 float32 v1 = env->fregs[f1].l.upper;
402 CPU_FloatU v2;
403
404 v2.l = val;
405 HELPER_LOG("%s: dividing 0x%d from f%d by 0x%d\n", __func__,
406 v1, f1, v2.f);
407 env->fregs[f1].l.upper = float32_div(v1, v2.f, &env->fpu_status);
408}
409
410/* 32-bit FP multiplication RM */
449c0d70 411void HELPER(meeb)(CPUS390XState *env, uint32_t f1, uint32_t val)
e72ca652
BS		 412{
413 float32 v1 = env->fregs[f1].l.upper;
414 CPU_FloatU v2;
415
416 v2.l = val;
417 HELPER_LOG("%s: multiplying 0x%d from f%d and 0x%d\n", __func__,
418 v1, f1, v2.f);
419 env->fregs[f1].l.upper = float32_mul(v1, v2.f, &env->fpu_status);
420}
421
422/* 32-bit FP compare RR */
449c0d70 423uint32_t HELPER(cebr)(CPUS390XState *env, uint32_t f1, uint32_t f2)
e72ca652
BS		 424{
425 float32 v1 = env->fregs[f1].l.upper;
426 float32 v2 = env->fregs[f2].l.upper;
427
428 HELPER_LOG("%s: comparing 0x%d from f%d and 0x%d\n", __func__,
429 v1, f1, v2);
449c0d70 430 return set_cc_f32(env, v1, v2);
e72ca652
BS		 431}
432
433/* 64-bit FP compare RR */
449c0d70 434uint32_t HELPER(cdbr)(CPUS390XState *env, uint32_t f1, uint32_t f2)
e72ca652
BS		 435{
436 float64 v1 = env->fregs[f1].d;
437 float64 v2 = env->fregs[f2].d;
438
439 HELPER_LOG("%s: comparing 0x%ld from f%d and 0x%ld\n", __func__,
440 v1, f1, v2);
449c0d70 441 return set_cc_f64(env, v1, v2);
e72ca652
BS		 442}
443
444/* 128-bit FP compare RR */
449c0d70 445uint32_t HELPER(cxbr)(CPUS390XState *env, uint32_t f1, uint32_t f2)
e72ca652
BS		 446{
447 CPU_QuadU v1;
448 CPU_QuadU v2;
449
450 v1.ll.upper = env->fregs[f1].ll;
451 v1.ll.lower = env->fregs[f1 + 2].ll;
452 v2.ll.upper = env->fregs[f2].ll;
453 v2.ll.lower = env->fregs[f2 + 2].ll;
454
449c0d70 455 return float_comp_to_cc(env, float128_compare_quiet(v1.q, v2.q,
e72ca652
BS		 456 &env->fpu_status));
457}
458
459/* 64-bit FP compare RM */
449c0d70 460uint32_t HELPER(cdb)(CPUS390XState *env, uint32_t f1, uint64_t a2)
e72ca652
BS		 461{
462 float64 v1 = env->fregs[f1].d;
463 CPU_DoubleU v2;
464
449c0d70 465 v2.ll = cpu_ldq_data(env, a2);
e72ca652
BS		 466 HELPER_LOG("%s: comparing 0x%ld from f%d and 0x%lx\n", __func__, v1,
467 f1, v2.d);
449c0d70 468 return set_cc_f64(env, v1, v2.d);
e72ca652
BS		 469}
470
471/* 64-bit FP addition RM */
449c0d70 472uint32_t HELPER(adb)(CPUS390XState *env, uint32_t f1, uint64_t a2)
e72ca652
BS		 473{
474 float64 v1 = env->fregs[f1].d;
475 CPU_DoubleU v2;
476
449c0d70 477 v2.ll = cpu_ldq_data(env, a2);
e72ca652
BS		 478 HELPER_LOG("%s: adding 0x%lx from f%d and 0x%lx\n", __func__,
479 v1, f1, v2.d);
480 env->fregs[f1].d = v1 = float64_add(v1, v2.d, &env->fpu_status);
481 return set_cc_nz_f64(v1);
482}
483
484/* 32-bit FP subtraction RM */
449c0d70 485void HELPER(seb)(CPUS390XState *env, uint32_t f1, uint32_t val)
e72ca652
BS		 486{
487 float32 v1 = env->fregs[f1].l.upper;
488 CPU_FloatU v2;
489
490 v2.l = val;
491 env->fregs[f1].l.upper = float32_sub(v1, v2.f, &env->fpu_status);
492}
493
494/* 64-bit FP subtraction RM */
449c0d70 495uint32_t HELPER(sdb)(CPUS390XState *env, uint32_t f1, uint64_t a2)
e72ca652
BS		 496{
497 float64 v1 = env->fregs[f1].d;
498 CPU_DoubleU v2;
499
449c0d70 500 v2.ll = cpu_ldq_data(env, a2);
e72ca652
BS		 501 env->fregs[f1].d = v1 = float64_sub(v1, v2.d, &env->fpu_status);
502 return set_cc_nz_f64(v1);
503}
504
505/* 64-bit FP multiplication RM */
449c0d70 506void HELPER(mdb)(CPUS390XState *env, uint32_t f1, uint64_t a2)
e72ca652
BS		 507{
508 float64 v1 = env->fregs[f1].d;
509 CPU_DoubleU v2;
510
449c0d70 511 v2.ll = cpu_ldq_data(env, a2);
e72ca652
BS		 512 HELPER_LOG("%s: multiplying 0x%lx from f%d and 0x%ld\n", __func__,
513 v1, f1, v2.d);
514 env->fregs[f1].d = float64_mul(v1, v2.d, &env->fpu_status);
515}
516
517/* 64-bit FP division RM */
449c0d70 518void HELPER(ddb)(CPUS390XState *env, uint32_t f1, uint64_t a2)
e72ca652
BS		 519{
520 float64 v1 = env->fregs[f1].d;
521 CPU_DoubleU v2;
522
449c0d70 523 v2.ll = cpu_ldq_data(env, a2);
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BS		 524 HELPER_LOG("%s: dividing 0x%lx from f%d by 0x%ld\n", __func__,
525 v1, f1, v2.d);
526 env->fregs[f1].d = float64_div(v1, v2.d, &env->fpu_status);
527}
528
449c0d70 529static void set_round_mode(CPUS390XState *env, int m3)
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BS		 530{
531 switch (m3) {
532 case 0:
533 /* current mode */
534 break;
535 case 1:
536 /* biased round no nearest */
537 case 4:
538 /* round to nearest */
539 set_float_rounding_mode(float_round_nearest_even, &env->fpu_status);
540 break;
541 case 5:
542 /* round to zero */
543 set_float_rounding_mode(float_round_to_zero, &env->fpu_status);
544 break;
545 case 6:
546 /* round to +inf */
547 set_float_rounding_mode(float_round_up, &env->fpu_status);
548 break;
549 case 7:
550 /* round to -inf */
551 set_float_rounding_mode(float_round_down, &env->fpu_status);
552 break;
553 }
554}
555
556/* convert 32-bit float to 64-bit int */
449c0d70
BS		 557uint32_t HELPER(cgebr)(CPUS390XState *env, uint32_t r1, uint32_t f2,
558 uint32_t m3)
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BS		 559{
560 float32 v2 = env->fregs[f2].l.upper;
561
449c0d70 562 set_round_mode(env, m3);
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BS		 563 env->regs[r1] = float32_to_int64(v2, &env->fpu_status);
564 return set_cc_nz_f32(v2);
565}
566
567/* convert 64-bit float to 64-bit int */
449c0d70
BS		 568uint32_t HELPER(cgdbr)(CPUS390XState *env, uint32_t r1, uint32_t f2,
569 uint32_t m3)
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BS		 570{
571 float64 v2 = env->fregs[f2].d;
572
449c0d70 573 set_round_mode(env, m3);
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BS		 574 env->regs[r1] = float64_to_int64(v2, &env->fpu_status);
575 return set_cc_nz_f64(v2);
576}
577
578/* convert 128-bit float to 64-bit int */
449c0d70
BS		 579uint32_t HELPER(cgxbr)(CPUS390XState *env, uint32_t r1, uint32_t f2,
580 uint32_t m3)
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BS		 581{
582 CPU_QuadU v2;
583
584 v2.ll.upper = env->fregs[f2].ll;
585 v2.ll.lower = env->fregs[f2 + 2].ll;
449c0d70 586 set_round_mode(env, m3);
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BS		 587 env->regs[r1] = float128_to_int64(v2.q, &env->fpu_status);
588 if (float128_is_any_nan(v2.q)) {
589 return 3;
590 } else if (float128_is_zero(v2.q)) {
591 return 0;
592 } else if (float128_is_neg(v2.q)) {
593 return 1;
594 } else {
595 return 2;
596 }
597}
598
599/* convert 32-bit float to 32-bit int */
449c0d70
BS		 600uint32_t HELPER(cfebr)(CPUS390XState *env, uint32_t r1, uint32_t f2,
601 uint32_t m3)
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BS		 602{
603 float32 v2 = env->fregs[f2].l.upper;
604
449c0d70 605 set_round_mode(env, m3);
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BS		 606 env->regs[r1] = (env->regs[r1] & 0xffffffff00000000ULL) |
607 float32_to_int32(v2, &env->fpu_status);
608 return set_cc_nz_f32(v2);
609}
610
611/* convert 64-bit float to 32-bit int */
449c0d70
BS		 612uint32_t HELPER(cfdbr)(CPUS390XState *env, uint32_t r1, uint32_t f2,
613 uint32_t m3)
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BS		 614{
615 float64 v2 = env->fregs[f2].d;
616
449c0d70 617 set_round_mode(env, m3);
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BS		 618 env->regs[r1] = (env->regs[r1] & 0xffffffff00000000ULL) |
619 float64_to_int32(v2, &env->fpu_status);
620 return set_cc_nz_f64(v2);
621}
622
623/* convert 128-bit float to 32-bit int */
449c0d70
BS		 624uint32_t HELPER(cfxbr)(CPUS390XState *env, uint32_t r1, uint32_t f2,
625 uint32_t m3)
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BS		 626{
627 CPU_QuadU v2;
628
629 v2.ll.upper = env->fregs[f2].ll;
630 v2.ll.lower = env->fregs[f2 + 2].ll;
631 env->regs[r1] = (env->regs[r1] & 0xffffffff00000000ULL) |
632 float128_to_int32(v2.q, &env->fpu_status);
633 return set_cc_nz_f128(v2.q);
634}
635
636/* load 32-bit FP zero */
449c0d70 637void HELPER(lzer)(CPUS390XState *env, uint32_t f1)
e72ca652
BS		 638{
639 env->fregs[f1].l.upper = float32_zero;
640}
641
642/* load 64-bit FP zero */
449c0d70 643void HELPER(lzdr)(CPUS390XState *env, uint32_t f1)
e72ca652
BS		 644{
645 env->fregs[f1].d = float64_zero;
646}
647
648/* load 128-bit FP zero */
449c0d70 649void HELPER(lzxr)(CPUS390XState *env, uint32_t f1)
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BS		 650{
651 CPU_QuadU x;
652
653 x.q = float64_to_float128(float64_zero, &env->fpu_status);
654 env->fregs[f1].ll = x.ll.upper;
655 env->fregs[f1 + 1].ll = x.ll.lower;
656}
657
658/* 128-bit FP subtraction RR */
449c0d70 659uint32_t HELPER(sxbr)(CPUS390XState *env, uint32_t f1, uint32_t f2)
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BS		 660{
661 CPU_QuadU v1;
662 CPU_QuadU v2;
663 CPU_QuadU res;
664
665 v1.ll.upper = env->fregs[f1].ll;
666 v1.ll.lower = env->fregs[f1 + 2].ll;
667 v2.ll.upper = env->fregs[f2].ll;
668 v2.ll.lower = env->fregs[f2 + 2].ll;
669 res.q = float128_sub(v1.q, v2.q, &env->fpu_status);
670 env->fregs[f1].ll = res.ll.upper;
671 env->fregs[f1 + 2].ll = res.ll.lower;
672 return set_cc_nz_f128(res.q);
673}
674
675/* 128-bit FP addition RR */
449c0d70 676uint32_t HELPER(axbr)(CPUS390XState *env, uint32_t f1, uint32_t f2)
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BS		 677{
678 CPU_QuadU v1;
679 CPU_QuadU v2;
680 CPU_QuadU res;
681
682 v1.ll.upper = env->fregs[f1].ll;
683 v1.ll.lower = env->fregs[f1 + 2].ll;
684 v2.ll.upper = env->fregs[f2].ll;
685 v2.ll.lower = env->fregs[f2 + 2].ll;
686 res.q = float128_add(v1.q, v2.q, &env->fpu_status);
687 env->fregs[f1].ll = res.ll.upper;
688 env->fregs[f1 + 2].ll = res.ll.lower;
689 return set_cc_nz_f128(res.q);
690}
691
692/* 32-bit FP multiplication RR */
449c0d70 693void HELPER(meebr)(CPUS390XState *env, uint32_t f1, uint32_t f2)
e72ca652
BS		 694{
695 env->fregs[f1].l.upper = float32_mul(env->fregs[f1].l.upper,
696 env->fregs[f2].l.upper,
697 &env->fpu_status);
698}
699
700/* 64-bit FP division RR */
449c0d70 701void HELPER(ddbr)(CPUS390XState *env, uint32_t f1, uint32_t f2)
e72ca652
BS		 702{
703 env->fregs[f1].d = float64_div(env->fregs[f1].d, env->fregs[f2].d,
704 &env->fpu_status);
705}
706
707/* 64-bit FP multiply and add RM */
449c0d70 708void HELPER(madb)(CPUS390XState *env, uint32_t f1, uint64_t a2, uint32_t f3)
e72ca652
BS		 709{
710 CPU_DoubleU v2;
711
712 HELPER_LOG("%s: f1 %d a2 0x%lx f3 %d\n", __func__, f1, a2, f3);
449c0d70 713 v2.ll = cpu_ldq_data(env, a2);
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BS		 714 env->fregs[f1].d = float64_add(env->fregs[f1].d,
715 float64_mul(v2.d, env->fregs[f3].d,
716 &env->fpu_status),
717 &env->fpu_status);
718}
719
720/* 64-bit FP multiply and add RR */
449c0d70 721void HELPER(madbr)(CPUS390XState *env, uint32_t f1, uint32_t f3, uint32_t f2)
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BS		 722{
723 HELPER_LOG("%s: f1 %d f2 %d f3 %d\n", __func__, f1, f2, f3);
724 env->fregs[f1].d = float64_add(float64_mul(env->fregs[f2].d,
725 env->fregs[f3].d,
726 &env->fpu_status),
727 env->fregs[f1].d, &env->fpu_status);
728}
729
730/* 64-bit FP multiply and subtract RR */
449c0d70 731void HELPER(msdbr)(CPUS390XState *env, uint32_t f1, uint32_t f3, uint32_t f2)
e72ca652
BS		 732{
733 HELPER_LOG("%s: f1 %d f2 %d f3 %d\n", __func__, f1, f2, f3);
734 env->fregs[f1].d = float64_sub(float64_mul(env->fregs[f2].d,
735 env->fregs[f3].d,
736 &env->fpu_status),
737 env->fregs[f1].d, &env->fpu_status);
738}
739
740/* 32-bit FP multiply and add RR */
449c0d70 741void HELPER(maebr)(CPUS390XState *env, uint32_t f1, uint32_t f3, uint32_t f2)
e72ca652
BS		 742{
743 env->fregs[f1].l.upper = float32_add(env->fregs[f1].l.upper,
744 float32_mul(env->fregs[f2].l.upper,
745 env->fregs[f3].l.upper,
746 &env->fpu_status),
747 &env->fpu_status);
748}
749
750/* convert 32-bit float to 64-bit float */
449c0d70 751void HELPER(ldeb)(CPUS390XState *env, uint32_t f1, uint64_t a2)
e72ca652
BS		 752{
753 uint32_t v2;
754
449c0d70 755 v2 = cpu_ldl_data(env, a2);
e72ca652
BS		 756 env->fregs[f1].d = float32_to_float64(v2,
757 &env->fpu_status);
758}
759
760/* convert 64-bit float to 128-bit float */
449c0d70 761void HELPER(lxdb)(CPUS390XState *env, uint32_t f1, uint64_t a2)
e72ca652
BS		 762{
763 CPU_DoubleU v2;
764 CPU_QuadU v1;
765
449c0d70 766 v2.ll = cpu_ldq_data(env, a2);
e72ca652
BS		 767 v1.q = float64_to_float128(v2.d, &env->fpu_status);
768 env->fregs[f1].ll = v1.ll.upper;
769 env->fregs[f1 + 2].ll = v1.ll.lower;
770}
771
772/* test data class 32-bit */
449c0d70 773uint32_t HELPER(tceb)(CPUS390XState *env, uint32_t f1, uint64_t m2)
e72ca652
BS		 774{
775 float32 v1 = env->fregs[f1].l.upper;
776 int neg = float32_is_neg(v1);
777 uint32_t cc = 0;
778
779 HELPER_LOG("%s: v1 0x%lx m2 0x%lx neg %d\n", __func__, (long)v1, m2, neg);
780 if ((float32_is_zero(v1) && (m2 & (1 << (11-neg)))) ||
781 (float32_is_infinity(v1) && (m2 & (1 << (5-neg)))) ||
782 (float32_is_any_nan(v1) && (m2 & (1 << (3-neg)))) ||
783 (float32_is_signaling_nan(v1) && (m2 & (1 << (1-neg))))) {
784 cc = 1;
785 } else if (m2 & (1 << (9-neg))) {
786 /* assume normalized number */
787 cc = 1;
788 }
789
790 /* FIXME: denormalized? */
791 return cc;
792}
793
794/* test data class 64-bit */
449c0d70 795uint32_t HELPER(tcdb)(CPUS390XState *env, uint32_t f1, uint64_t m2)
e72ca652
BS		 796{
797 float64 v1 = env->fregs[f1].d;
798 int neg = float64_is_neg(v1);
799 uint32_t cc = 0;
800
801 HELPER_LOG("%s: v1 0x%lx m2 0x%lx neg %d\n", __func__, v1, m2, neg);
802 if ((float64_is_zero(v1) && (m2 & (1 << (11-neg)))) ||
803 (float64_is_infinity(v1) && (m2 & (1 << (5-neg)))) ||
804 (float64_is_any_nan(v1) && (m2 & (1 << (3-neg)))) ||
805 (float64_is_signaling_nan(v1) && (m2 & (1 << (1-neg))))) {
806 cc = 1;
807 } else if (m2 & (1 << (9-neg))) {
808 /* assume normalized number */
809 cc = 1;
810 }
811 /* FIXME: denormalized? */
812 return cc;
813}
814
815/* test data class 128-bit */
449c0d70 816uint32_t HELPER(tcxb)(CPUS390XState *env, uint32_t f1, uint64_t m2)
e72ca652
BS		 817{
818 CPU_QuadU v1;
819 uint32_t cc = 0;
820 int neg;
821
822 v1.ll.upper = env->fregs[f1].ll;
823 v1.ll.lower = env->fregs[f1 + 2].ll;
824
825 neg = float128_is_neg(v1.q);
826 if ((float128_is_zero(v1.q) && (m2 & (1 << (11-neg)))) ||
827 (float128_is_infinity(v1.q) && (m2 & (1 << (5-neg)))) ||
828 (float128_is_any_nan(v1.q) && (m2 & (1 << (3-neg)))) ||
829 (float128_is_signaling_nan(v1.q) && (m2 & (1 << (1-neg))))) {
830 cc = 1;
831 } else if (m2 & (1 << (9-neg))) {
832 /* assume normalized number */
833 cc = 1;
834 }
835 /* FIXME: denormalized? */
836 return cc;
837}
838
839/* square root 64-bit RR */
449c0d70 840void HELPER(sqdbr)(CPUS390XState *env, uint32_t f1, uint32_t f2)
e72ca652
BS		 841{
842 env->fregs[f1].d = float64_sqrt(env->fregs[f2].d, &env->fpu_status);
843}
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