[qemu.git] / hw / slavio_misc.c

/*
 * QEMU Sparc SLAVIO aux io port emulation
 *
 * Copyright (c) 2005 Fabrice Bellard
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */

#include "sun4m.h"
#include "sysemu.h"
#include "sysbus.h"

/* debug misc */
//#define DEBUG_MISC

/*
 * This is the auxio port, chip control and system control part of
 * chip STP2001 (Slave I/O), also produced as NCR89C105. See
 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt
 *
 * This also includes the PMC CPU idle controller.
 */

#ifdef DEBUG_MISC
#define MISC_DPRINTF(fmt, ...)                                  \
    do { printf("MISC: " fmt , ## __VA_ARGS__); } while (0)
#else
#define MISC_DPRINTF(fmt, ...)
#endif

typedef struct MiscState {
    SysBusDevice busdev;
    qemu_irq irq;
    uint8_t config;
    uint8_t aux1, aux2;
    uint8_t diag, mctrl;
    uint32_t sysctrl;
    uint16_t leds;
    qemu_irq fdc_tc;
} MiscState;

typedef struct APCState {
    SysBusDevice busdev;
    qemu_irq cpu_halt;
} APCState;

#define MISC_SIZE 1
#define SYSCTRL_SIZE 4

#define AUX1_TC        0x02

#define AUX2_PWROFF    0x01
#define AUX2_PWRINTCLR 0x02
#define AUX2_PWRFAIL   0x20

#define CFG_PWRINTEN   0x08

#define SYS_RESET      0x01
#define SYS_RESETSTAT  0x02

static void slavio_misc_update_irq(void *opaque)
{
    MiscState *s = opaque;

    if ((s->aux2 & AUX2_PWRFAIL) && (s->config & CFG_PWRINTEN)) {
        MISC_DPRINTF("Raise IRQ\n");
        qemu_irq_raise(s->irq);
    } else {
        MISC_DPRINTF("Lower IRQ\n");
        qemu_irq_lower(s->irq);
    }
}

static void slavio_misc_reset(void *opaque)
{
    MiscState *s = opaque;

    // Diagnostic and system control registers not cleared in reset
    s->config = s->aux1 = s->aux2 = s->mctrl = 0;
}

static void slavio_set_power_fail(void *opaque, int irq, int power_failing)
{
    MiscState *s = opaque;

    MISC_DPRINTF("Power fail: %d, config: %d\n", power_failing, s->config);
    if (power_failing && (s->config & CFG_PWRINTEN)) {
        s->aux2 |= AUX2_PWRFAIL;
    } else {
        s->aux2 &= ~AUX2_PWRFAIL;
    }
    slavio_misc_update_irq(s);
}

static void slavio_cfg_mem_writeb(void *opaque, target_phys_addr_t addr,
                                  uint32_t val)
{
    MiscState *s = opaque;

    MISC_DPRINTF("Write config %2.2x\n", val & 0xff);
    s->config = val & 0xff;
    slavio_misc_update_irq(s);
}

static uint32_t slavio_cfg_mem_readb(void *opaque, target_phys_addr_t addr)
{
    MiscState *s = opaque;
    uint32_t ret = 0;

    ret = s->config;
    MISC_DPRINTF("Read config %2.2x\n", ret);
    return ret;
}

static CPUReadMemoryFunc * const slavio_cfg_mem_read[3] = {
    slavio_cfg_mem_readb,
    NULL,
    NULL,
};

static CPUWriteMemoryFunc * const slavio_cfg_mem_write[3] = {
    slavio_cfg_mem_writeb,
    NULL,
    NULL,
};

static void slavio_diag_mem_writeb(void *opaque, target_phys_addr_t addr,
                                   uint32_t val)
{
    MiscState *s = opaque;

    MISC_DPRINTF("Write diag %2.2x\n", val & 0xff);
    s->diag = val & 0xff;
}

static uint32_t slavio_diag_mem_readb(void *opaque, target_phys_addr_t addr)
{
    MiscState *s = opaque;
    uint32_t ret = 0;

    ret = s->diag;
    MISC_DPRINTF("Read diag %2.2x\n", ret);
    return ret;
}

static CPUReadMemoryFunc * const slavio_diag_mem_read[3] = {
    slavio_diag_mem_readb,
    NULL,
    NULL,
};

static CPUWriteMemoryFunc * const slavio_diag_mem_write[3] = {
    slavio_diag_mem_writeb,
    NULL,
    NULL,
};

static void slavio_mdm_mem_writeb(void *opaque, target_phys_addr_t addr,
                                  uint32_t val)
{
    MiscState *s = opaque;

    MISC_DPRINTF("Write modem control %2.2x\n", val & 0xff);
    s->mctrl = val & 0xff;
}

static uint32_t slavio_mdm_mem_readb(void *opaque, target_phys_addr_t addr)
{
    MiscState *s = opaque;
    uint32_t ret = 0;

    ret = s->mctrl;
    MISC_DPRINTF("Read modem control %2.2x\n", ret);
    return ret;
}

static CPUReadMemoryFunc * const slavio_mdm_mem_read[3] = {
    slavio_mdm_mem_readb,
    NULL,
    NULL,
};

static CPUWriteMemoryFunc * const slavio_mdm_mem_write[3] = {
    slavio_mdm_mem_writeb,
    NULL,
    NULL,
};

static void slavio_aux1_mem_writeb(void *opaque, target_phys_addr_t addr,
                                   uint32_t val)
{
    MiscState *s = opaque;

    MISC_DPRINTF("Write aux1 %2.2x\n", val & 0xff);
    if (val & AUX1_TC) {
        // Send a pulse to floppy terminal count line
        if (s->fdc_tc) {
            qemu_irq_raise(s->fdc_tc);
            qemu_irq_lower(s->fdc_tc);
        }
        val &= ~AUX1_TC;
    }
    s->aux1 = val & 0xff;
}

static uint32_t slavio_aux1_mem_readb(void *opaque, target_phys_addr_t addr)
{
    MiscState *s = opaque;
    uint32_t ret = 0;

    ret = s->aux1;
    MISC_DPRINTF("Read aux1 %2.2x\n", ret);

    return ret;
}

static CPUReadMemoryFunc * const slavio_aux1_mem_read[3] = {
    slavio_aux1_mem_readb,
    NULL,
    NULL,
};

static CPUWriteMemoryFunc * const slavio_aux1_mem_write[3] = {
    slavio_aux1_mem_writeb,
    NULL,
    NULL,
};

static void slavio_aux2_mem_writeb(void *opaque, target_phys_addr_t addr,
                                   uint32_t val)
{
    MiscState *s = opaque;

    val &= AUX2_PWRINTCLR | AUX2_PWROFF;
    MISC_DPRINTF("Write aux2 %2.2x\n", val);
    val |= s->aux2 & AUX2_PWRFAIL;
    if (val & AUX2_PWRINTCLR) // Clear Power Fail int
        val &= AUX2_PWROFF;
    s->aux2 = val;
    if (val & AUX2_PWROFF)
        qemu_system_shutdown_request();
    slavio_misc_update_irq(s);
}

static uint32_t slavio_aux2_mem_readb(void *opaque, target_phys_addr_t addr)
{
    MiscState *s = opaque;
    uint32_t ret = 0;

    ret = s->aux2;
    MISC_DPRINTF("Read aux2 %2.2x\n", ret);

    return ret;
}

static CPUReadMemoryFunc * const slavio_aux2_mem_read[3] = {
    slavio_aux2_mem_readb,
    NULL,
    NULL,
};

static CPUWriteMemoryFunc * const slavio_aux2_mem_write[3] = {
    slavio_aux2_mem_writeb,
    NULL,
    NULL,
};

static void apc_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
{
    APCState *s = opaque;

    MISC_DPRINTF("Write power management %2.2x\n", val & 0xff);
    qemu_irq_raise(s->cpu_halt);
}

static uint32_t apc_mem_readb(void *opaque, target_phys_addr_t addr)
{
    uint32_t ret = 0;

    MISC_DPRINTF("Read power management %2.2x\n", ret);
    return ret;
}

static CPUReadMemoryFunc * const apc_mem_read[3] = {
    apc_mem_readb,
    NULL,
    NULL,
};

static CPUWriteMemoryFunc * const apc_mem_write[3] = {
    apc_mem_writeb,
    NULL,
    NULL,
};

static uint32_t slavio_sysctrl_mem_readl(void *opaque, target_phys_addr_t addr)
{
    MiscState *s = opaque;
    uint32_t ret = 0;

    switch (addr) {
    case 0:
        ret = s->sysctrl;
        break;
    default:
        break;
    }
    MISC_DPRINTF("Read system control %08x\n", ret);
    return ret;
}

static void slavio_sysctrl_mem_writel(void *opaque, target_phys_addr_t addr,
                                      uint32_t val)
{
    MiscState *s = opaque;

    MISC_DPRINTF("Write system control %08x\n", val);
    switch (addr) {
    case 0:
        if (val & SYS_RESET) {
            s->sysctrl = SYS_RESETSTAT;
            qemu_system_reset_request();
        }
        break;
    default:
        break;
    }
}

static CPUReadMemoryFunc * const slavio_sysctrl_mem_read[3] = {
    NULL,
    NULL,
    slavio_sysctrl_mem_readl,
};

static CPUWriteMemoryFunc * const slavio_sysctrl_mem_write[3] = {
    NULL,
    NULL,
    slavio_sysctrl_mem_writel,
};

static uint32_t slavio_led_mem_readw(void *opaque, target_phys_addr_t addr)
{
    MiscState *s = opaque;
    uint32_t ret = 0;

    switch (addr) {
    case 0:
        ret = s->leds;
        break;
    default:
        break;
    }
    MISC_DPRINTF("Read diagnostic LED %04x\n", ret);
    return ret;
}

static void slavio_led_mem_writew(void *opaque, target_phys_addr_t addr,
                                  uint32_t val)
{
    MiscState *s = opaque;

    MISC_DPRINTF("Write diagnostic LED %04x\n", val & 0xffff);
    switch (addr) {
    case 0:
        s->leds = val;
        break;
    default:
        break;
    }
}

static CPUReadMemoryFunc * const slavio_led_mem_read[3] = {
    NULL,
    slavio_led_mem_readw,
    NULL,
};

static CPUWriteMemoryFunc * const slavio_led_mem_write[3] = {
    NULL,
    slavio_led_mem_writew,
    NULL,
};

static void slavio_misc_save(QEMUFile *f, void *opaque)
{
    MiscState *s = opaque;
    uint32_t tmp = 0;
    uint8_t tmp8;

    qemu_put_be32s(f, &tmp); /* ignored, was IRQ.  */
    qemu_put_8s(f, &s->config);
    qemu_put_8s(f, &s->aux1);
    qemu_put_8s(f, &s->aux2);
    qemu_put_8s(f, &s->diag);
    qemu_put_8s(f, &s->mctrl);
    tmp8 = s->sysctrl & 0xff;
    qemu_put_8s(f, &tmp8);
}

static int slavio_misc_load(QEMUFile *f, void *opaque, int version_id)
{
    MiscState *s = opaque;
    uint32_t tmp;
    uint8_t tmp8;

    if (version_id != 1)
        return -EINVAL;

    qemu_get_be32s(f, &tmp);
    qemu_get_8s(f, &s->config);
    qemu_get_8s(f, &s->aux1);
    qemu_get_8s(f, &s->aux2);
    qemu_get_8s(f, &s->diag);
    qemu_get_8s(f, &s->mctrl);
    qemu_get_8s(f, &tmp8);
    s->sysctrl = (uint32_t)tmp8;
    return 0;
}

static int apc_init1(SysBusDevice *dev)
{
    APCState *s = FROM_SYSBUS(APCState, dev);
    int io;

    sysbus_init_irq(dev, &s->cpu_halt);

    /* Power management (APC) XXX: not a Slavio device */
    io = cpu_register_io_memory(apc_mem_read, apc_mem_write, s);
    sysbus_init_mmio(dev, MISC_SIZE, io);
    return 0;
}

static int slavio_misc_init1(SysBusDevice *dev)
{
    MiscState *s = FROM_SYSBUS(MiscState, dev);
    int io;

    sysbus_init_irq(dev, &s->irq);
    sysbus_init_irq(dev, &s->fdc_tc);

    /* 8 bit registers */
    /* Slavio control */
    io = cpu_register_io_memory(slavio_cfg_mem_read,
                                slavio_cfg_mem_write, s);
    sysbus_init_mmio(dev, MISC_SIZE, io);

    /* Diagnostics */
    io = cpu_register_io_memory(slavio_diag_mem_read,
                                slavio_diag_mem_write, s);
    sysbus_init_mmio(dev, MISC_SIZE, io);

    /* Modem control */
    io = cpu_register_io_memory(slavio_mdm_mem_read,
                                slavio_mdm_mem_write, s);
    sysbus_init_mmio(dev, MISC_SIZE, io);

    /* 16 bit registers */
    /* ss600mp diag LEDs */
    io = cpu_register_io_memory(slavio_led_mem_read,
                                slavio_led_mem_write, s);
    sysbus_init_mmio(dev, MISC_SIZE, io);

    /* 32 bit registers */
    /* System control */
    io = cpu_register_io_memory(slavio_sysctrl_mem_read,
                                slavio_sysctrl_mem_write, s);
    sysbus_init_mmio(dev, SYSCTRL_SIZE, io);

    /* AUX 1 (Misc System Functions) */
    io = cpu_register_io_memory(slavio_aux1_mem_read,
                                slavio_aux1_mem_write, s);
    sysbus_init_mmio(dev, MISC_SIZE, io);

    /* AUX 2 (Software Powerdown Control) */
    io = cpu_register_io_memory(slavio_aux2_mem_read,
                                slavio_aux2_mem_write, s);
    sysbus_init_mmio(dev, MISC_SIZE, io);

    qdev_init_gpio_in(&dev->qdev, slavio_set_power_fail, 1);

    register_savevm("slavio_misc", -1, 1, slavio_misc_save, slavio_misc_load,
                    s);
    qemu_register_reset(slavio_misc_reset, s);
    slavio_misc_reset(s);
    return 0;
}

static SysBusDeviceInfo slavio_misc_info = {
    .init = slavio_misc_init1,
    .qdev.name  = "slavio_misc",
    .qdev.size  = sizeof(MiscState),
};

static SysBusDeviceInfo apc_info = {
    .init = apc_init1,
    .qdev.name  = "apc",
    .qdev.size  = sizeof(MiscState),
};

static void slavio_misc_register_devices(void)
{
    sysbus_register_withprop(&slavio_misc_info);
    sysbus_register_withprop(&apc_info);
}

device_init(slavio_misc_register_devices)
Commit	Line	Data
3475187d FB	1	/*
3475187d FB	2	* QEMU Sparc SLAVIO aux io port emulation
5fafdf24	3	*
3475187d	4	* Copyright (c) 2005 Fabrice Bellard
5fafdf24	5	*
3475187d FB	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
2582cfa0	24
87ecb68b PB	25	#include "sun4m.h"
87ecb68b PB	26	#include "sysemu.h"
2582cfa0	27	#include "sysbus.h"
87ecb68b	28
3475187d FB	29	/* debug misc */
	30	//#define DEBUG_MISC
	31
	32	/*
	33	* This is the auxio port, chip control and system control part of
	34	* chip STP2001 (Slave I/O), also produced as NCR89C105. See
	35	* http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt
	36	*
	37	* This also includes the PMC CPU idle controller.
	38	*/
	39
	40	#ifdef DEBUG_MISC
001faf32 BS	41	#define MISC_DPRINTF(fmt, ...) \
001faf32 BS	42	do { printf("MISC: " fmt , ## __VA_ARGS__); } while (0)
3475187d	43	#else
001faf32	44	#define MISC_DPRINTF(fmt, ...)
3475187d FB	45	#endif
	46
	47	typedef struct MiscState {
2582cfa0	48	SysBusDevice busdev;
d537cf6c	49	qemu_irq irq;
3475187d FB	50	uint8_t config;
3475187d FB	51	uint8_t aux1, aux2;
bfa30a38 BS	52	uint8_t diag, mctrl;
bfa30a38 BS	53	uint32_t sysctrl;
6a3b9cc9	54	uint16_t leds;
2be17ebd	55	qemu_irq fdc_tc;
3475187d FB	56	} MiscState;
3475187d FB	57
2582cfa0 BS	58	typedef struct APCState {
	59	SysBusDevice busdev;
	60	qemu_irq cpu_halt;
	61	} APCState;
	62
5aca8c3b	63	#define MISC_SIZE 1
a8f48dcc	64	#define SYSCTRL_SIZE 4
3475187d	65
2be17ebd BS	66	#define AUX1_TC 0x02
2be17ebd BS	67
7debeb82 BS	68	#define AUX2_PWROFF 0x01
	69	#define AUX2_PWRINTCLR 0x02
	70	#define AUX2_PWRFAIL 0x20
	71
	72	#define CFG_PWRINTEN 0x08
	73
	74	#define SYS_RESET 0x01
	75	#define SYS_RESETSTAT 0x02
	76
3475187d FB	77	static void slavio_misc_update_irq(void *opaque)
	78	{
	79	MiscState *s = opaque;
	80
7debeb82	81	if ((s->aux2 & AUX2_PWRFAIL) && (s->config & CFG_PWRINTEN)) {
d537cf6c PB	82	MISC_DPRINTF("Raise IRQ\n");
d537cf6c PB	83	qemu_irq_raise(s->irq);
3475187d	84	} else {
d537cf6c PB	85	MISC_DPRINTF("Lower IRQ\n");
d537cf6c PB	86	qemu_irq_lower(s->irq);
3475187d FB	87	}
	88	}
	89
	90	static void slavio_misc_reset(void *opaque)
	91	{
	92	MiscState *s = opaque;
	93
4e3b1ea1	94	// Diagnostic and system control registers not cleared in reset
3475187d FB	95	s->config = s->aux1 = s->aux2 = s->mctrl = 0;
	96	}
	97
b2b6f6ec	98	static void slavio_set_power_fail(void *opaque, int irq, int power_failing)
3475187d FB	99	{
	100	MiscState *s = opaque;
	101
	102	MISC_DPRINTF("Power fail: %d, config: %d\n", power_failing, s->config);
7debeb82 BS	103	if (power_failing && (s->config & CFG_PWRINTEN)) {
7debeb82 BS	104	s->aux2 \|= AUX2_PWRFAIL;
3475187d	105	} else {
7debeb82	106	s->aux2 &= ~AUX2_PWRFAIL;
3475187d FB	107	}
	108	slavio_misc_update_irq(s);
	109	}
	110
a8f48dcc BS	111	static void slavio_cfg_mem_writeb(void *opaque, target_phys_addr_t addr,
	112	uint32_t val)
	113	{
	114	MiscState *s = opaque;
	115
	116	MISC_DPRINTF("Write config %2.2x\n", val & 0xff);
	117	s->config = val & 0xff;
	118	slavio_misc_update_irq(s);
	119	}
	120
	121	static uint32_t slavio_cfg_mem_readb(void *opaque, target_phys_addr_t addr)
	122	{
	123	MiscState *s = opaque;
	124	uint32_t ret = 0;
	125
	126	ret = s->config;
	127	MISC_DPRINTF("Read config %2.2x\n", ret);
	128	return ret;
	129	}
	130
d60efc6b	131	static CPUReadMemoryFunc * const slavio_cfg_mem_read[3] = {
a8f48dcc BS	132	slavio_cfg_mem_readb,
	133	NULL,
	134	NULL,
	135	};
	136
d60efc6b	137	static CPUWriteMemoryFunc * const slavio_cfg_mem_write[3] = {
a8f48dcc BS	138	slavio_cfg_mem_writeb,
	139	NULL,
	140	NULL,
	141	};
	142
	143	static void slavio_diag_mem_writeb(void *opaque, target_phys_addr_t addr,
bfa30a38	144	uint32_t val)
3475187d FB	145	{
	146	MiscState *s = opaque;
	147
a8f48dcc BS	148	MISC_DPRINTF("Write diag %2.2x\n", val & 0xff);
a8f48dcc BS	149	s->diag = val & 0xff;
3475187d FB	150	}
3475187d FB	151
a8f48dcc	152	static uint32_t slavio_diag_mem_readb(void *opaque, target_phys_addr_t addr)
3475187d FB	153	{
	154	MiscState *s = opaque;
	155	uint32_t ret = 0;
	156
a8f48dcc BS	157	ret = s->diag;
	158	MISC_DPRINTF("Read diag %2.2x\n", ret);
	159	return ret;
	160	}
	161
d60efc6b	162	static CPUReadMemoryFunc * const slavio_diag_mem_read[3] = {
a8f48dcc BS	163	slavio_diag_mem_readb,
	164	NULL,
	165	NULL,
	166	};
	167
d60efc6b	168	static CPUWriteMemoryFunc * const slavio_diag_mem_write[3] = {
a8f48dcc BS	169	slavio_diag_mem_writeb,
	170	NULL,
	171	NULL,
	172	};
	173
	174	static void slavio_mdm_mem_writeb(void *opaque, target_phys_addr_t addr,
	175	uint32_t val)
	176	{
	177	MiscState *s = opaque;
	178
	179	MISC_DPRINTF("Write modem control %2.2x\n", val & 0xff);
	180	s->mctrl = val & 0xff;
	181	}
	182
	183	static uint32_t slavio_mdm_mem_readb(void *opaque, target_phys_addr_t addr)
	184	{
	185	MiscState *s = opaque;
	186	uint32_t ret = 0;
	187
	188	ret = s->mctrl;
	189	MISC_DPRINTF("Read modem control %2.2x\n", ret);
3475187d FB	190	return ret;
	191	}
	192
d60efc6b	193	static CPUReadMemoryFunc * const slavio_mdm_mem_read[3] = {
a8f48dcc	194	slavio_mdm_mem_readb,
7c560456 BS	195	NULL,
7c560456 BS	196	NULL,
3475187d FB	197	};
3475187d FB	198
d60efc6b	199	static CPUWriteMemoryFunc * const slavio_mdm_mem_write[3] = {
a8f48dcc	200	slavio_mdm_mem_writeb,
7c560456 BS	201	NULL,
7c560456 BS	202	NULL,
3475187d FB	203	};
3475187d FB	204
0019ad53 BS	205	static void slavio_aux1_mem_writeb(void *opaque, target_phys_addr_t addr,
	206	uint32_t val)
	207	{
	208	MiscState *s = opaque;
	209
	210	MISC_DPRINTF("Write aux1 %2.2x\n", val & 0xff);
2be17ebd BS	211	if (val & AUX1_TC) {
	212	// Send a pulse to floppy terminal count line
	213	if (s->fdc_tc) {
	214	qemu_irq_raise(s->fdc_tc);
	215	qemu_irq_lower(s->fdc_tc);
	216	}
	217	val &= ~AUX1_TC;
	218	}
0019ad53 BS	219	s->aux1 = val & 0xff;
	220	}
	221
	222	static uint32_t slavio_aux1_mem_readb(void *opaque, target_phys_addr_t addr)
	223	{
	224	MiscState *s = opaque;
	225	uint32_t ret = 0;
	226
	227	ret = s->aux1;
	228	MISC_DPRINTF("Read aux1 %2.2x\n", ret);
	229
	230	return ret;
	231	}
	232
d60efc6b	233	static CPUReadMemoryFunc * const slavio_aux1_mem_read[3] = {
0019ad53 BS	234	slavio_aux1_mem_readb,
	235	NULL,
	236	NULL,
	237	};
	238
d60efc6b	239	static CPUWriteMemoryFunc * const slavio_aux1_mem_write[3] = {
0019ad53 BS	240	slavio_aux1_mem_writeb,
	241	NULL,
	242	NULL,
	243	};
	244
	245	static void slavio_aux2_mem_writeb(void *opaque, target_phys_addr_t addr,
	246	uint32_t val)
	247	{
	248	MiscState *s = opaque;
	249
	250	val &= AUX2_PWRINTCLR \| AUX2_PWROFF;
	251	MISC_DPRINTF("Write aux2 %2.2x\n", val);
	252	val \|= s->aux2 & AUX2_PWRFAIL;
	253	if (val & AUX2_PWRINTCLR) // Clear Power Fail int
	254	val &= AUX2_PWROFF;
	255	s->aux2 = val;
	256	if (val & AUX2_PWROFF)
	257	qemu_system_shutdown_request();
	258	slavio_misc_update_irq(s);
	259	}
	260
	261	static uint32_t slavio_aux2_mem_readb(void *opaque, target_phys_addr_t addr)
	262	{
	263	MiscState *s = opaque;
	264	uint32_t ret = 0;
	265
	266	ret = s->aux2;
	267	MISC_DPRINTF("Read aux2 %2.2x\n", ret);
	268
	269	return ret;
	270	}
	271
d60efc6b	272	static CPUReadMemoryFunc * const slavio_aux2_mem_read[3] = {
0019ad53 BS	273	slavio_aux2_mem_readb,
	274	NULL,
	275	NULL,
	276	};
	277
d60efc6b	278	static CPUWriteMemoryFunc * const slavio_aux2_mem_write[3] = {
0019ad53 BS	279	slavio_aux2_mem_writeb,
	280	NULL,
	281	NULL,
	282	};
	283
	284	static void apc_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
	285	{
2582cfa0	286	APCState *s = opaque;
0019ad53 BS	287
0019ad53 BS	288	MISC_DPRINTF("Write power management %2.2x\n", val & 0xff);
6d0c293d	289	qemu_irq_raise(s->cpu_halt);
0019ad53 BS	290	}
	291
	292	static uint32_t apc_mem_readb(void *opaque, target_phys_addr_t addr)
	293	{
	294	uint32_t ret = 0;
	295
	296	MISC_DPRINTF("Read power management %2.2x\n", ret);
	297	return ret;
	298	}
	299
d60efc6b	300	static CPUReadMemoryFunc * const apc_mem_read[3] = {
0019ad53 BS	301	apc_mem_readb,
	302	NULL,
	303	NULL,
	304	};
	305
d60efc6b	306	static CPUWriteMemoryFunc * const apc_mem_write[3] = {
0019ad53 BS	307	apc_mem_writeb,
	308	NULL,
	309	NULL,
	310	};
	311
bfa30a38 BS	312	static uint32_t slavio_sysctrl_mem_readl(void *opaque, target_phys_addr_t addr)
	313	{
	314	MiscState *s = opaque;
a8f48dcc	315	uint32_t ret = 0;
bfa30a38	316
a8f48dcc	317	switch (addr) {
bfa30a38 BS	318	case 0:
	319	ret = s->sysctrl;
	320	break;
	321	default:
	322	break;
	323	}
5626b017	324	MISC_DPRINTF("Read system control %08x\n", ret);
bfa30a38 BS	325	return ret;
	326	}
	327
	328	static void slavio_sysctrl_mem_writel(void *opaque, target_phys_addr_t addr,
	329	uint32_t val)
	330	{
	331	MiscState *s = opaque;
bfa30a38	332
5626b017	333	MISC_DPRINTF("Write system control %08x\n", val);
a8f48dcc	334	switch (addr) {
bfa30a38	335	case 0:
7debeb82 BS	336	if (val & SYS_RESET) {
7debeb82 BS	337	s->sysctrl = SYS_RESETSTAT;
bfa30a38 BS	338	qemu_system_reset_request();
	339	}
	340	break;
	341	default:
	342	break;
	343	}
	344	}
	345
d60efc6b	346	static CPUReadMemoryFunc * const slavio_sysctrl_mem_read[3] = {
7c560456 BS	347	NULL,
7c560456 BS	348	NULL,
bfa30a38 BS	349	slavio_sysctrl_mem_readl,
	350	};
	351
d60efc6b	352	static CPUWriteMemoryFunc * const slavio_sysctrl_mem_write[3] = {
7c560456 BS	353	NULL,
7c560456 BS	354	NULL,
bfa30a38 BS	355	slavio_sysctrl_mem_writel,
	356	};
	357
7c560456	358	static uint32_t slavio_led_mem_readw(void *opaque, target_phys_addr_t addr)
6a3b9cc9 BS	359	{
6a3b9cc9 BS	360	MiscState *s = opaque;
a8f48dcc	361	uint32_t ret = 0;
6a3b9cc9	362
a8f48dcc	363	switch (addr) {
6a3b9cc9 BS	364	case 0:
	365	ret = s->leds;
	366	break;
	367	default:
	368	break;
	369	}
5626b017	370	MISC_DPRINTF("Read diagnostic LED %04x\n", ret);
6a3b9cc9 BS	371	return ret;
	372	}
	373
7c560456	374	static void slavio_led_mem_writew(void *opaque, target_phys_addr_t addr,
6a3b9cc9 BS	375	uint32_t val)
	376	{
	377	MiscState *s = opaque;
6a3b9cc9	378
5626b017	379	MISC_DPRINTF("Write diagnostic LED %04x\n", val & 0xffff);
a8f48dcc	380	switch (addr) {
6a3b9cc9	381	case 0:
d5296cb5	382	s->leds = val;
6a3b9cc9 BS	383	break;
	384	default:
	385	break;
	386	}
	387	}
	388
d60efc6b	389	static CPUReadMemoryFunc * const slavio_led_mem_read[3] = {
7c560456 BS	390	NULL,
	391	slavio_led_mem_readw,
	392	NULL,
6a3b9cc9 BS	393	};
6a3b9cc9 BS	394
d60efc6b	395	static CPUWriteMemoryFunc * const slavio_led_mem_write[3] = {
7c560456 BS	396	NULL,
	397	slavio_led_mem_writew,
	398	NULL,
6a3b9cc9 BS	399	};
6a3b9cc9 BS	400
3475187d FB	401	static void slavio_misc_save(QEMUFile f, void opaque)
	402	{
	403	MiscState *s = opaque;
22548760	404	uint32_t tmp = 0;
bfa30a38	405	uint8_t tmp8;
3475187d	406
d537cf6c	407	qemu_put_be32s(f, &tmp); /* ignored, was IRQ. */
3475187d FB	408	qemu_put_8s(f, &s->config);
	409	qemu_put_8s(f, &s->aux1);
	410	qemu_put_8s(f, &s->aux2);
	411	qemu_put_8s(f, &s->diag);
	412	qemu_put_8s(f, &s->mctrl);
bfa30a38 BS	413	tmp8 = s->sysctrl & 0xff;
bfa30a38 BS	414	qemu_put_8s(f, &tmp8);
3475187d FB	415	}
	416
	417	static int slavio_misc_load(QEMUFile f, void opaque, int version_id)
	418	{
	419	MiscState *s = opaque;
22548760	420	uint32_t tmp;
bfa30a38	421	uint8_t tmp8;
3475187d FB	422
	423	if (version_id != 1)
	424	return -EINVAL;
	425
d537cf6c	426	qemu_get_be32s(f, &tmp);
3475187d FB	427	qemu_get_8s(f, &s->config);
	428	qemu_get_8s(f, &s->aux1);
	429	qemu_get_8s(f, &s->aux2);
	430	qemu_get_8s(f, &s->diag);
	431	qemu_get_8s(f, &s->mctrl);
bfa30a38 BS	432	qemu_get_8s(f, &tmp8);
bfa30a38 BS	433	s->sysctrl = (uint32_t)tmp8;
3475187d FB	434	return 0;
	435	}
	436
81a322d4	437	static int apc_init1(SysBusDevice *dev)
2582cfa0 BS	438	{
	439	APCState *s = FROM_SYSBUS(APCState, dev);
	440	int io;
3475187d	441
2582cfa0 BS	442	sysbus_init_irq(dev, &s->cpu_halt);
	443
	444	/* Power management (APC) XXX: not a Slavio device */
	445	io = cpu_register_io_memory(apc_mem_read, apc_mem_write, s);
	446	sysbus_init_mmio(dev, MISC_SIZE, io);
81a322d4	447	return 0;
2582cfa0 BS	448	}
2582cfa0 BS	449
81a322d4	450	static int slavio_misc_init1(SysBusDevice *dev)
2582cfa0 BS	451	{
	452	MiscState *s = FROM_SYSBUS(MiscState, dev);
	453	int io;
	454
	455	sysbus_init_irq(dev, &s->irq);
	456	sysbus_init_irq(dev, &s->fdc_tc);
	457
	458	/* 8 bit registers */
	459	/* Slavio control */
	460	io = cpu_register_io_memory(slavio_cfg_mem_read,
	461	slavio_cfg_mem_write, s);
	462	sysbus_init_mmio(dev, MISC_SIZE, io);
	463
	464	/* Diagnostics */
	465	io = cpu_register_io_memory(slavio_diag_mem_read,
	466	slavio_diag_mem_write, s);
	467	sysbus_init_mmio(dev, MISC_SIZE, io);
	468
	469	/* Modem control */
	470	io = cpu_register_io_memory(slavio_mdm_mem_read,
	471	slavio_mdm_mem_write, s);
	472	sysbus_init_mmio(dev, MISC_SIZE, io);
	473
	474	/* 16 bit registers */
	475	/* ss600mp diag LEDs */
	476	io = cpu_register_io_memory(slavio_led_mem_read,
	477	slavio_led_mem_write, s);
	478	sysbus_init_mmio(dev, MISC_SIZE, io);
	479
	480	/* 32 bit registers */
	481	/* System control */
	482	io = cpu_register_io_memory(slavio_sysctrl_mem_read,
	483	slavio_sysctrl_mem_write, s);
	484	sysbus_init_mmio(dev, SYSCTRL_SIZE, io);
	485
	486	/* AUX 1 (Misc System Functions) */
	487	io = cpu_register_io_memory(slavio_aux1_mem_read,
	488	slavio_aux1_mem_write, s);
	489	sysbus_init_mmio(dev, MISC_SIZE, io);
	490
	491	/* AUX 2 (Software Powerdown Control) */
	492	io = cpu_register_io_memory(slavio_aux2_mem_read,
	493	slavio_aux2_mem_write, s);
	494	sysbus_init_mmio(dev, MISC_SIZE, io);
	495
b2b6f6ec BS	496	qdev_init_gpio_in(&dev->qdev, slavio_set_power_fail, 1);
b2b6f6ec BS	497
2582cfa0	498	register_savevm("slavio_misc", -1, 1, slavio_misc_save, slavio_misc_load,
bfa30a38	499	s);
a08d4367	500	qemu_register_reset(slavio_misc_reset, s);
3475187d	501	slavio_misc_reset(s);
81a322d4	502	return 0;
2582cfa0	503	}
0019ad53	504
2582cfa0 BS	505	static SysBusDeviceInfo slavio_misc_info = {
	506	.init = slavio_misc_init1,
	507	.qdev.name = "slavio_misc",
	508	.qdev.size = sizeof(MiscState),
2582cfa0 BS	509	};
	510
	511	static SysBusDeviceInfo apc_info = {
	512	.init = apc_init1,
	513	.qdev.name = "apc",
	514	.qdev.size = sizeof(MiscState),
2582cfa0 BS	515	};
	516
	517	static void slavio_misc_register_devices(void)
	518	{
	519	sysbus_register_withprop(&slavio_misc_info);
	520	sysbus_register_withprop(&apc_info);
3475187d	521	}
2582cfa0 BS	522
2582cfa0 BS	523	device_init(slavio_misc_register_devices)