[qemu.git] / hw / ppc_chrp.c

/*
 * QEMU PPC CHRP/PMAC hardware System Emulator
 * 
 * Copyright (c) 2004 Fabrice Bellard
 * 
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#include "vl.h"

#define BIOS_FILENAME "ppc_rom.bin"
#define NVRAM_SIZE        0x2000

#define KERNEL_LOAD_ADDR 0x01000000
#define INITRD_LOAD_ADDR 0x01800000

/* MacIO devices (mapped inside the MacIO address space): CUDA, DBDMA,
   NVRAM (not implemented).  */

static int dbdma_mem_index;
static int cuda_mem_index;
static int ide0_mem_index = -1;
static int ide1_mem_index = -1;
static int openpic_mem_index = -1;
static int heathrow_pic_mem_index = -1;

/* DBDMA: currently no op - should suffice right now */

static void dbdma_writeb (void *opaque, target_phys_addr_t addr, uint32_t value)
{
    printf("%s: 0x%08x <= 0x%08x\n", __func__, addr, value);
}

static void dbdma_writew (void *opaque, target_phys_addr_t addr, uint32_t value)
{
}

static void dbdma_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
{
}

static uint32_t dbdma_readb (void *opaque, target_phys_addr_t addr)
{
    printf("%s: 0x%08x => 0x00000000\n", __func__, addr);
    return 0;
}

static uint32_t dbdma_readw (void *opaque, target_phys_addr_t addr)
{
    return 0;
}

static uint32_t dbdma_readl (void *opaque, target_phys_addr_t addr)
{
    return 0;
}

static CPUWriteMemoryFunc *dbdma_write[] = {
    &dbdma_writeb,
    &dbdma_writew,
    &dbdma_writel,
};

static CPUReadMemoryFunc *dbdma_read[] = {
    &dbdma_readb,
    &dbdma_readw,
    &dbdma_readl,
};

static void macio_map(PCIDevice *pci_dev, int region_num, 
                      uint32_t addr, uint32_t size, int type)
{
    if (heathrow_pic_mem_index >= 0) {
        cpu_register_physical_memory(addr + 0x00000, 0x1000, 
                                     heathrow_pic_mem_index);
    }
    cpu_register_physical_memory(addr + 0x08000, 0x1000, dbdma_mem_index);
    cpu_register_physical_memory(addr + 0x16000, 0x2000, cuda_mem_index);
    if (ide0_mem_index >= 0)
        cpu_register_physical_memory(addr + 0x1f000, 0x1000, ide0_mem_index);
    if (ide1_mem_index >= 0)
        cpu_register_physical_memory(addr + 0x20000, 0x1000, ide1_mem_index);
    if (openpic_mem_index >= 0) {
        cpu_register_physical_memory(addr + 0x40000, 0x40000, 
                                     openpic_mem_index);
    }
}

static void macio_init(PCIBus *bus)
{
    PCIDevice *d;

    d = pci_register_device(bus, "macio", sizeof(PCIDevice),
                            -1, NULL, NULL);
    /* Note: this code is strongly inspirated from the corresponding code
       in PearPC */
    d->config[0x00] = 0x6b; // vendor_id
    d->config[0x01] = 0x10;
    d->config[0x02] = 0x22;
    d->config[0x03] = 0x00;

    d->config[0x0a] = 0x00; // class_sub = pci2pci
    d->config[0x0b] = 0xff; // class_base = bridge
    d->config[0x0e] = 0x00; // header_type

    d->config[0x3d] = 0x01; // interrupt on pin 1
    
    dbdma_mem_index = cpu_register_io_memory(0, dbdma_read, dbdma_write, NULL);

    pci_register_io_region(d, 0, 0x80000, 
                           PCI_ADDRESS_SPACE_MEM, macio_map);
}

/* UniN device */
static void unin_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
{
}

static uint32_t unin_readl (void *opaque, target_phys_addr_t addr)
{
    return 0;
}

static CPUWriteMemoryFunc *unin_write[] = {
    &unin_writel,
    &unin_writel,
    &unin_writel,
};

static CPUReadMemoryFunc *unin_read[] = {
    &unin_readl,
    &unin_readl,
    &unin_readl,
};

/* temporary frame buffer OSI calls for the video.x driver. The right
   solution is to modify the driver to use VGA PCI I/Os */
static int vga_osi_call(CPUState *env)
{
    static int vga_vbl_enabled;
    int linesize;
    
    //    printf("osi_call R5=%d\n", env->gpr[5]);

    /* same handler as PearPC, coming from the original MOL video
       driver. */
    switch(env->gpr[5]) {
    case 4:
        break;
    case 28: /* set_vmode */
        if (env->gpr[6] != 1 || env->gpr[7] != 0)
            env->gpr[3] = 1;
        else
            env->gpr[3] = 0;
        break;
    case 29: /* get_vmode_info */
        if (env->gpr[6] != 0) {
            if (env->gpr[6] != 1 || env->gpr[7] != 0) {
                env->gpr[3] = 1;
                break;
            }
        }
        env->gpr[3] = 0; 
        env->gpr[4] = (1 << 16) | 1; /* num_vmodes, cur_vmode */
        env->gpr[5] = (1 << 16) | 0; /* num_depths, cur_depth_mode */
        env->gpr[6] = (graphic_width << 16) | graphic_height; /* w, h */
        env->gpr[7] = 85 << 16; /* refresh rate */
        env->gpr[8] = (graphic_depth + 7) & ~7; /* depth (round to byte) */
        linesize = ((graphic_depth + 7) >> 3) * graphic_width;
        linesize = (linesize + 3) & ~3;
        env->gpr[9] = (linesize << 16) | 0; /* row_bytes, offset */
        break;
    case 31: /* set_video power */
        env->gpr[3] = 0;
        break;
    case 39: /* video_ctrl */
        if (env->gpr[6] == 0 || env->gpr[6] == 1)
            vga_vbl_enabled = env->gpr[6];
        env->gpr[3] = 0;
        break;
    case 47:
        break;
    case 59: /* set_color */
        /* R6 = index, R7 = RGB */
        env->gpr[3] = 0;
        break;
    case 64: /* get color */
        /* R6 = index */
        env->gpr[3] = 0; 
        break;
    case 116: /* set hwcursor */
        /* R6 = x, R7 = y, R8 = visible, R9 = data */
        break;
    default:
        fprintf(stderr, "unsupported OSI call R5=%08x\n", env->gpr[5]);
        break;
    }
    return 1; /* osi_call handled */
}

/* PowerPC CHRP hardware initialisation */
static void ppc_chrp_init(int ram_size, int vga_ram_size, int boot_device,
                          DisplayState *ds, const char **fd_filename, 
                          int snapshot,
                          const char *kernel_filename, 
                          const char *kernel_cmdline,
                          const char *initrd_filename,
                          int is_heathrow)
{
    char buf[1024];
    SetIRQFunc *set_irq;
    void *pic;
    m48t59_t *nvram;
    int PPC_io_memory, unin_memory;
    int ret, linux_boot, i;
    unsigned long bios_offset;
    uint32_t kernel_base, kernel_size, initrd_base, initrd_size;
    PCIBus *pci_bus;
    const char *arch_name;

    linux_boot = (kernel_filename != NULL);

    /* allocate RAM */
    cpu_register_physical_memory(0, ram_size, IO_MEM_RAM);

    /* allocate and load BIOS */
    bios_offset = ram_size + vga_ram_size;
    snprintf(buf, sizeof(buf), "%s/%s", bios_dir, BIOS_FILENAME);
    ret = load_image(buf, phys_ram_base + bios_offset);
    if (ret != BIOS_SIZE) {
        fprintf(stderr, "qemu: could not load PPC PREP bios '%s'\n", buf);
        exit(1);
    }
    cpu_register_physical_memory((uint32_t)(-BIOS_SIZE), 
                                 BIOS_SIZE, bios_offset | IO_MEM_ROM);
    cpu_single_env->nip = 0xfffffffc;

    if (linux_boot) {
        kernel_base = KERNEL_LOAD_ADDR;
        /* now we can load the kernel */
        kernel_size = load_image(kernel_filename, phys_ram_base + kernel_base);
        if (kernel_size < 0) {
            fprintf(stderr, "qemu: could not load kernel '%s'\n", 
                    kernel_filename);
            exit(1);
        }
        /* load initrd */
        if (initrd_filename) {
            initrd_base = INITRD_LOAD_ADDR;
            initrd_size = load_image(initrd_filename,
                                     phys_ram_base + initrd_base);
            if (initrd_size < 0) {
                fprintf(stderr, "qemu: could not load initial ram disk '%s'\n", 
                        initrd_filename);
                exit(1);
            }
        } else {
            initrd_base = 0;
            initrd_size = 0;
        }
        boot_device = 'm';
    } else {
        kernel_base = 0;
        kernel_size = 0;
        initrd_base = 0;
        initrd_size = 0;
    }
    /* Register CPU as a 74x/75x */
    cpu_ppc_register(cpu_single_env, 0x00080000);
    /* Set time-base frequency to 10 Mhz */
    cpu_ppc_tb_init(cpu_single_env, 10UL * 1000UL * 1000UL);

    cpu_single_env->osi_call = vga_osi_call;

    if (is_heathrow) {
        isa_mem_base = 0x80000000;
        pci_bus = pci_grackle_init(0xfec00000);
        
        /* Register 2 MB of ISA IO space */
        PPC_io_memory = cpu_register_io_memory(0, PPC_io_read, PPC_io_write, NULL);
        cpu_register_physical_memory(0xfe000000, 0x00200000, PPC_io_memory);
        
        /* init basic PC hardware */
        vga_initialize(pci_bus, ds, phys_ram_base + ram_size, ram_size, 
                       vga_ram_size);
        pic = heathrow_pic_init(&heathrow_pic_mem_index);
        set_irq = heathrow_pic_set_irq;
        pci_set_pic(pci_bus, set_irq, pic);

        /* XXX: suppress that */
        pic_init();
        
        /* XXX: use Mac Serial port */
        serial_init(0x3f8, 4, serial_hds[0]);
        
        for(i = 0; i < nb_nics; i++) {
            pci_ne2000_init(pci_bus, &nd_table[i]);
        }
        
        pci_cmd646_ide_init(pci_bus, &bs_table[0], 0);

        /* cuda also initialize ADB */
        cuda_mem_index = cuda_init(set_irq, pic, 0x12);
        
        adb_kbd_init(&adb_bus);
        adb_mouse_init(&adb_bus);
        
        macio_init(pci_bus);
        
        nvram = m48t59_init(8, 0xFFF04000, 0x0074, NVRAM_SIZE);
        
        arch_name = "HEATHROW";
    } else {
        isa_mem_base = 0x80000000;
        pci_bus = pci_pmac_init();
        
        /* Register 8 MB of ISA IO space */
        PPC_io_memory = cpu_register_io_memory(0, PPC_io_read, PPC_io_write, NULL);
        cpu_register_physical_memory(0xF2000000, 0x00800000, PPC_io_memory);
        
        /* UniN init */
        unin_memory = cpu_register_io_memory(0, unin_read, unin_write, NULL);
        cpu_register_physical_memory(0xf8000000, 0x00001000, unin_memory);

        /* init basic PC hardware */
        vga_initialize(pci_bus, ds, phys_ram_base + ram_size, ram_size, 
                       vga_ram_size);
        pic = openpic_init(NULL, &openpic_mem_index, 1);
        set_irq = openpic_set_irq;
        pci_set_pic(pci_bus, set_irq, pic);

        /* XXX: suppress that */
        pic_init();
        
        /* XXX: use Mac Serial port */
        serial_init(0x3f8, 4, serial_hds[0]);
        
        for(i = 0; i < nb_nics; i++) {
            pci_ne2000_init(pci_bus, &nd_table[i]);
        }
        
#if 1
        ide0_mem_index = pmac_ide_init(&bs_table[0], set_irq, pic, 0x13);
        ide1_mem_index = pmac_ide_init(&bs_table[2], set_irq, pic, 0x14);
#else
        pci_cmd646_ide_init(pci_bus, &bs_table[0], 0);
#endif
        /* cuda also initialize ADB */
        cuda_mem_index = cuda_init(set_irq, pic, 0x19);
        
        adb_kbd_init(&adb_bus);
        adb_mouse_init(&adb_bus);
        
        macio_init(pci_bus);
        
        nvram = m48t59_init(8, 0xFFF04000, 0x0074, NVRAM_SIZE);
        
        arch_name = "MAC99";
    }
    
    if (graphic_depth != 15 && graphic_depth != 32 && graphic_depth != 8)
        graphic_depth = 15;

    PPC_NVRAM_set_params(nvram, NVRAM_SIZE, arch_name, ram_size, boot_device,
                         kernel_base, kernel_size,
                         kernel_cmdline,
                         initrd_base, initrd_size,
                         /* XXX: need an option to load a NVRAM image */
                         0,
                         graphic_width, graphic_height, graphic_depth);
    /* No PCI init: the BIOS will do it */

    /* Special port to get debug messages from Open-Firmware */
    register_ioport_write(0x0F00, 4, 1, &PPC_debug_write, NULL);
}

static void ppc_core99_init(int ram_size, int vga_ram_size, int boot_device,
                            DisplayState *ds, const char **fd_filename, 
                            int snapshot,
                            const char *kernel_filename, 
                            const char *kernel_cmdline,
                            const char *initrd_filename)
{
    ppc_chrp_init(ram_size, vga_ram_size, boot_device,
                  ds, fd_filename, snapshot,
                  kernel_filename, kernel_cmdline,
                  initrd_filename, 0);
}
    
static void ppc_heathrow_init(int ram_size, int vga_ram_size, int boot_device,
                              DisplayState *ds, const char **fd_filename, 
                              int snapshot,
                              const char *kernel_filename, 
                              const char *kernel_cmdline,
                              const char *initrd_filename)
{
    ppc_chrp_init(ram_size, vga_ram_size, boot_device,
                  ds, fd_filename, snapshot,
                  kernel_filename, kernel_cmdline,
                  initrd_filename, 1);
}

QEMUMachine core99_machine = {
    "core99",
    "Core99 based PowerMAC",
    ppc_core99_init,
};

QEMUMachine heathrow_machine = {
    "heathrow",
    "Heathrow based PowerMAC",
    ppc_heathrow_init,
};
Commit	Line	Data
64201201 FB	1	/*
	2	* QEMU PPC CHRP/PMAC hardware System Emulator
	3	*
	4	* Copyright (c) 2004 Fabrice Bellard
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
	24	#include "vl.h"
	25
	26	#define BIOS_FILENAME "ppc_rom.bin"
	27	#define NVRAM_SIZE 0x2000
	28
b6b8bd18 FB	29	#define KERNEL_LOAD_ADDR 0x01000000
	30	#define INITRD_LOAD_ADDR 0x01800000
	31
267002cd FB	32	/* MacIO devices (mapped inside the MacIO address space): CUDA, DBDMA,
	33	NVRAM (not implemented). */
	34
	35	static int dbdma_mem_index;
	36	static int cuda_mem_index;
0aa6a4a2 FB	37	static int ide0_mem_index = -1;
	38	static int ide1_mem_index = -1;
	39	static int openpic_mem_index = -1;
	40	static int heathrow_pic_mem_index = -1;
267002cd FB	41
	42	/* DBDMA: currently no op - should suffice right now */
	43
	44	static void dbdma_writeb (void *opaque, target_phys_addr_t addr, uint32_t value)
	45	{
b6b8bd18	46	printf("%s: 0x%08x <= 0x%08x\n", __func__, addr, value);
267002cd FB	47	}
	48
	49	static void dbdma_writew (void *opaque, target_phys_addr_t addr, uint32_t value)
	50	{
	51	}
	52
	53	static void dbdma_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
	54	{
	55	}
	56
	57	static uint32_t dbdma_readb (void *opaque, target_phys_addr_t addr)
	58	{
b6b8bd18	59	printf("%s: 0x%08x => 0x00000000\n", __func__, addr);
267002cd FB	60	return 0;
	61	}
	62
	63	static uint32_t dbdma_readw (void *opaque, target_phys_addr_t addr)
	64	{
	65	return 0;
	66	}
	67
	68	static uint32_t dbdma_readl (void *opaque, target_phys_addr_t addr)
	69	{
	70	return 0;
	71	}
	72
	73	static CPUWriteMemoryFunc *dbdma_write[] = {
	74	&dbdma_writeb,
	75	&dbdma_writew,
	76	&dbdma_writel,
	77	};
	78
	79	static CPUReadMemoryFunc *dbdma_read[] = {
	80	&dbdma_readb,
	81	&dbdma_readw,
	82	&dbdma_readl,
	83	};
	84
	85	static void macio_map(PCIDevice *pci_dev, int region_num,
	86	uint32_t addr, uint32_t size, int type)
	87	{
0aa6a4a2 FB	88	if (heathrow_pic_mem_index >= 0) {
	89	cpu_register_physical_memory(addr + 0x00000, 0x1000,
	90	heathrow_pic_mem_index);
	91	}
267002cd FB	92	cpu_register_physical_memory(addr + 0x08000, 0x1000, dbdma_mem_index);
267002cd FB	93	cpu_register_physical_memory(addr + 0x16000, 0x2000, cuda_mem_index);
0aa6a4a2 FB	94	if (ide0_mem_index >= 0)
	95	cpu_register_physical_memory(addr + 0x1f000, 0x1000, ide0_mem_index);
	96	if (ide1_mem_index >= 0)
	97	cpu_register_physical_memory(addr + 0x20000, 0x1000, ide1_mem_index);
	98	if (openpic_mem_index >= 0) {
	99	cpu_register_physical_memory(addr + 0x40000, 0x40000,
	100	openpic_mem_index);
	101	}
267002cd FB	102	}
267002cd FB	103
46e50e9d	104	static void macio_init(PCIBus *bus)
267002cd FB	105	{
	106	PCIDevice *d;
	107
46e50e9d FB	108	d = pci_register_device(bus, "macio", sizeof(PCIDevice),
46e50e9d FB	109	-1, NULL, NULL);
267002cd FB	110	/* Note: this code is strongly inspirated from the corresponding code
	111	in PearPC */
	112	d->config[0x00] = 0x6b; // vendor_id
	113	d->config[0x01] = 0x10;
b6b8bd18	114	d->config[0x02] = 0x22;
267002cd FB	115	d->config[0x03] = 0x00;
	116
	117	d->config[0x0a] = 0x00; // class_sub = pci2pci
	118	d->config[0x0b] = 0xff; // class_base = bridge
	119	d->config[0x0e] = 0x00; // header_type
	120
	121	d->config[0x3d] = 0x01; // interrupt on pin 1
	122
	123	dbdma_mem_index = cpu_register_io_memory(0, dbdma_read, dbdma_write, NULL);
	124
	125	pci_register_io_region(d, 0, 0x80000,
	126	PCI_ADDRESS_SPACE_MEM, macio_map);
	127	}
	128
0aa6a4a2 FB	129	/* UniN device */
	130	static void unin_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
	131	{
	132	}
	133
	134	static uint32_t unin_readl (void *opaque, target_phys_addr_t addr)
	135	{
	136	return 0;
	137	}
	138
	139	static CPUWriteMemoryFunc *unin_write[] = {
	140	&unin_writel,
	141	&unin_writel,
	142	&unin_writel,
	143	};
	144
	145	static CPUReadMemoryFunc *unin_read[] = {
	146	&unin_readl,
	147	&unin_readl,
	148	&unin_readl,
	149	};
	150
	151	/* temporary frame buffer OSI calls for the video.x driver. The right
	152	solution is to modify the driver to use VGA PCI I/Os */
	153	static int vga_osi_call(CPUState *env)
	154	{
	155	static int vga_vbl_enabled;
	156	int linesize;
	157
	158	// printf("osi_call R5=%d\n", env->gpr[5]);
	159
	160	/* same handler as PearPC, coming from the original MOL video
	161	driver. */
	162	switch(env->gpr[5]) {
	163	case 4:
	164	break;
	165	case 28: /* set_vmode */
	166	if (env->gpr[6] != 1 \|\| env->gpr[7] != 0)
	167	env->gpr[3] = 1;
	168	else
	169	env->gpr[3] = 0;
	170	break;
	171	case 29: /* get_vmode_info */
	172	if (env->gpr[6] != 0) {
	173	if (env->gpr[6] != 1 \|\| env->gpr[7] != 0) {
	174	env->gpr[3] = 1;
	175	break;
	176	}
	177	}
	178	env->gpr[3] = 0;
	179	env->gpr[4] = (1 << 16) \| 1; /* num_vmodes, cur_vmode */
	180	env->gpr[5] = (1 << 16) \| 0; /* num_depths, cur_depth_mode */
	181	env->gpr[6] = (graphic_width << 16) \| graphic_height; /* w, h */
	182	env->gpr[7] = 85 << 16; /* refresh rate */
	183	env->gpr[8] = (graphic_depth + 7) & ~7; /* depth (round to byte) */
	184	linesize = ((graphic_depth + 7) >> 3) * graphic_width;
	185	linesize = (linesize + 3) & ~3;
	186	env->gpr[9] = (linesize << 16) \| 0; /* row_bytes, offset */
	187	break;
	188	case 31: /* set_video power */
	189	env->gpr[3] = 0;
	190	break;
	191	case 39: /* video_ctrl */
	192	if (env->gpr[6] == 0 \|\| env->gpr[6] == 1)
193	vga_vbl_enabled = env->gpr[6];
194	env->gpr[3] = 0;
195	break;
196	case 47:
197	break;
198	case 59: /* set_color */
199	/* R6 = index, R7 = RGB */
200	env->gpr[3] = 0;
201	break;
202	case 64: /* get color */
203	/* R6 = index */
204	env->gpr[3] = 0;
205	break;
206	case 116: /* set hwcursor */
207	/* R6 = x, R7 = y, R8 = visible, R9 = data */
208	break;
209	default:
210	fprintf(stderr, "unsupported OSI call R5=%08x\n", env->gpr[5]);
211	break;
212	}
213	return 1; /* osi_call handled */
214	}
215
216	/* PowerPC CHRP hardware initialisation */
217	static void ppc_chrp_init(int ram_size, int vga_ram_size, int boot_device,
218	DisplayState ds, const char *fd_filename,
219	int snapshot,
220	const char *kernel_filename,
221	const char *kernel_cmdline,
222	const char *initrd_filename,
223	int is_heathrow)
64201201 FB	224	{
64201201 FB	225	char buf[1024];
0aa6a4a2 FB	226	SetIRQFunc *set_irq;
0aa6a4a2 FB	227	void *pic;
64201201	228	m48t59_t *nvram;
0aa6a4a2	229	int PPC_io_memory, unin_memory;
82c643ff	230	int ret, linux_boot, i;
64201201	231	unsigned long bios_offset;
b6b8bd18	232	uint32_t kernel_base, kernel_size, initrd_base, initrd_size;
46e50e9d	233	PCIBus *pci_bus;
0aa6a4a2	234	const char *arch_name;
46e50e9d	235
64201201 FB	236	linux_boot = (kernel_filename != NULL);
	237
	238	/* allocate RAM */
	239	cpu_register_physical_memory(0, ram_size, IO_MEM_RAM);
	240
	241	/* allocate and load BIOS */
	242	bios_offset = ram_size + vga_ram_size;
	243	snprintf(buf, sizeof(buf), "%s/%s", bios_dir, BIOS_FILENAME);
	244	ret = load_image(buf, phys_ram_base + bios_offset);
	245	if (ret != BIOS_SIZE) {
	246	fprintf(stderr, "qemu: could not load PPC PREP bios '%s'\n", buf);
	247	exit(1);
	248	}
	249	cpu_register_physical_memory((uint32_t)(-BIOS_SIZE),
	250	BIOS_SIZE, bios_offset \| IO_MEM_ROM);
	251	cpu_single_env->nip = 0xfffffffc;
	252
b6b8bd18 FB	253	if (linux_boot) {
	254	kernel_base = KERNEL_LOAD_ADDR;
	255	/* now we can load the kernel */
	256	kernel_size = load_image(kernel_filename, phys_ram_base + kernel_base);
	257	if (kernel_size < 0) {
	258	fprintf(stderr, "qemu: could not load kernel '%s'\n",
	259	kernel_filename);
	260	exit(1);
	261	}
	262	/* load initrd */
	263	if (initrd_filename) {
	264	initrd_base = INITRD_LOAD_ADDR;
	265	initrd_size = load_image(initrd_filename,
	266	phys_ram_base + initrd_base);
	267	if (initrd_size < 0) {
	268	fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
	269	initrd_filename);
	270	exit(1);
	271	}
	272	} else {
	273	initrd_base = 0;
	274	initrd_size = 0;
	275	}
	276	boot_device = 'm';
	277	} else {
	278	kernel_base = 0;
	279	kernel_size = 0;
	280	initrd_base = 0;
	281	initrd_size = 0;
	282	}
64201201 FB	283	/* Register CPU as a 74x/75x */
64201201 FB	284	cpu_ppc_register(cpu_single_env, 0x00080000);
0aa6a4a2 FB	285	/* Set time-base frequency to 10 Mhz */
	286	cpu_ppc_tb_init(cpu_single_env, 10UL * 1000UL * 1000UL);
	287
	288	cpu_single_env->osi_call = vga_osi_call;
	289
	290	if (is_heathrow) {
	291	isa_mem_base = 0x80000000;
	292	pci_bus = pci_grackle_init(0xfec00000);
	293
	294	/* Register 2 MB of ISA IO space */
	295	PPC_io_memory = cpu_register_io_memory(0, PPC_io_read, PPC_io_write, NULL);
	296	cpu_register_physical_memory(0xfe000000, 0x00200000, PPC_io_memory);
	297
	298	/* init basic PC hardware */
	299	vga_initialize(pci_bus, ds, phys_ram_base + ram_size, ram_size,
	300	vga_ram_size);
	301	pic = heathrow_pic_init(&heathrow_pic_mem_index);
	302	set_irq = heathrow_pic_set_irq;
	303	pci_set_pic(pci_bus, set_irq, pic);
	304
	305	/* XXX: suppress that */
	306	pic_init();
	307
	308	/* XXX: use Mac Serial port */
	309	serial_init(0x3f8, 4, serial_hds[0]);
	310
	311	for(i = 0; i < nb_nics; i++) {
	312	pci_ne2000_init(pci_bus, &nd_table[i]);
	313	}
	314
	315	pci_cmd646_ide_init(pci_bus, &bs_table[0], 0);
	316
	317	/* cuda also initialize ADB */
	318	cuda_mem_index = cuda_init(set_irq, pic, 0x12);
	319
	320	adb_kbd_init(&adb_bus);
	321	adb_mouse_init(&adb_bus);
	322
	323	macio_init(pci_bus);
	324
	325	nvram = m48t59_init(8, 0xFFF04000, 0x0074, NVRAM_SIZE);
	326
	327	arch_name = "HEATHROW";
	328	} else {
	329	isa_mem_base = 0x80000000;
	330	pci_bus = pci_pmac_init();
	331
	332	/* Register 8 MB of ISA IO space */
	333	PPC_io_memory = cpu_register_io_memory(0, PPC_io_read, PPC_io_write, NULL);
	334	cpu_register_physical_memory(0xF2000000, 0x00800000, PPC_io_memory);
	335
	336	/* UniN init */
	337	unin_memory = cpu_register_io_memory(0, unin_read, unin_write, NULL);
	338	cpu_register_physical_memory(0xf8000000, 0x00001000, unin_memory);
	339
	340	/* init basic PC hardware */
	341	vga_initialize(pci_bus, ds, phys_ram_base + ram_size, ram_size,
	342	vga_ram_size);
	343	pic = openpic_init(NULL, &openpic_mem_index, 1);
	344	set_irq = openpic_set_irq;
	345	pci_set_pic(pci_bus, set_irq, pic);
	346
	347	/* XXX: suppress that */
	348	pic_init();
349
350	/* XXX: use Mac Serial port */
351	serial_init(0x3f8, 4, serial_hds[0]);
352
353	for(i = 0; i < nb_nics; i++) {
354	pci_ne2000_init(pci_bus, &nd_table[i]);
355	}
356
357	#if 1
358	ide0_mem_index = pmac_ide_init(&bs_table[0], set_irq, pic, 0x13);
359	ide1_mem_index = pmac_ide_init(&bs_table[2], set_irq, pic, 0x14);
360	#else
361	pci_cmd646_ide_init(pci_bus, &bs_table[0], 0);
362	#endif
363	/* cuda also initialize ADB */
364	cuda_mem_index = cuda_init(set_irq, pic, 0x19);
365
366	adb_kbd_init(&adb_bus);
367	adb_mouse_init(&adb_bus);
368
369	macio_init(pci_bus);
370
371	nvram = m48t59_init(8, 0xFFF04000, 0x0074, NVRAM_SIZE);
372
373	arch_name = "MAC99";
64201201	374	}
b6b8bd18 FB	375
	376	if (graphic_depth != 15 && graphic_depth != 32 && graphic_depth != 8)
	377	graphic_depth = 15;
64201201	378
0aa6a4a2	379	PPC_NVRAM_set_params(nvram, NVRAM_SIZE, arch_name, ram_size, boot_device,
b6b8bd18 FB	380	kernel_base, kernel_size,
	381	kernel_cmdline,
	382	initrd_base, initrd_size,
64201201	383	/* XXX: need an option to load a NVRAM image */
b6b8bd18 FB	384	0,
	385	graphic_width, graphic_height, graphic_depth);
	386	/* No PCI init: the BIOS will do it */
0aa6a4a2 FB	387
	388	/* Special port to get debug messages from Open-Firmware */
	389	register_ioport_write(0x0F00, 4, 1, &PPC_debug_write, NULL);
	390	}
	391
	392	static void ppc_core99_init(int ram_size, int vga_ram_size, int boot_device,
	393	DisplayState ds, const char *fd_filename,
	394	int snapshot,
	395	const char *kernel_filename,
	396	const char *kernel_cmdline,
	397	const char *initrd_filename)
	398	{
	399	ppc_chrp_init(ram_size, vga_ram_size, boot_device,
	400	ds, fd_filename, snapshot,
	401	kernel_filename, kernel_cmdline,
	402	initrd_filename, 0);
64201201	403	}
0aa6a4a2 FB	404
	405	static void ppc_heathrow_init(int ram_size, int vga_ram_size, int boot_device,
	406	DisplayState ds, const char *fd_filename,
	407	int snapshot,
	408	const char *kernel_filename,
	409	const char *kernel_cmdline,
	410	const char *initrd_filename)
	411	{
	412	ppc_chrp_init(ram_size, vga_ram_size, boot_device,
	413	ds, fd_filename, snapshot,
	414	kernel_filename, kernel_cmdline,
	415	initrd_filename, 1);
	416	}
	417
	418	QEMUMachine core99_machine = {
	419	"core99",
	420	"Core99 based PowerMAC",
	421	ppc_core99_init,
	422	};
	423
	424	QEMUMachine heathrow_machine = {
	425	"heathrow",
	426	"Heathrow based PowerMAC",
	427	ppc_heathrow_init,
	428	};