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Commit | Line | Data |
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29e4bcb2 AF |
1 | /* |
2 | * QEMU S/390 CPU | |
3 | * | |
1ac1a749 AF |
4 | * Copyright (c) 2009 Ulrich Hecht |
5 | * Copyright (c) 2011 Alexander Graf | |
29e4bcb2 | 6 | * Copyright (c) 2012 SUSE LINUX Products GmbH |
70bada03 | 7 | * Copyright (c) 2012 IBM Corp. |
29e4bcb2 AF |
8 | * |
9 | * This library is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU Lesser General Public | |
11 | * License as published by the Free Software Foundation; either | |
12 | * version 2.1 of the License, or (at your option) any later version. | |
13 | * | |
14 | * This library is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
17 | * Lesser General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU Lesser General Public | |
20 | * License along with this library; if not, see | |
21 | * <http://www.gnu.org/licenses/lgpl-2.1.html> | |
70bada03 JF |
22 | * Contributions after 2012-12-11 are licensed under the terms of the |
23 | * GNU GPL, version 2 or (at your option) any later version. | |
29e4bcb2 AF |
24 | */ |
25 | ||
9615495a | 26 | #include "qemu/osdep.h" |
da34e65c | 27 | #include "qapi/error.h" |
564b863d | 28 | #include "cpu.h" |
29e4bcb2 | 29 | #include "qemu-common.h" |
f348b6d1 | 30 | #include "qemu/cutils.h" |
1de7afc9 | 31 | #include "qemu/timer.h" |
eb24f7c6 | 32 | #include "qemu/error-report.h" |
eb24f7c6 | 33 | #include "trace.h" |
96b1a8bb | 34 | #include "qapi/visitor.h" |
741da0d3 | 35 | #include "migration/vmstate.h" |
63c91552 | 36 | #include "exec/exec-all.h" |
c7396bbb | 37 | #ifndef CONFIG_USER_ONLY |
741da0d3 | 38 | #include "hw/hw.h" |
904e5fd5 | 39 | #include "sysemu/arch_init.h" |
96b1a8bb | 40 | #include "sysemu/sysemu.h" |
a006b67f | 41 | #include "hw/s390x/sclp.h" |
904e5fd5 VM |
42 | #endif |
43 | ||
70bada03 JF |
44 | #define CR0_RESET 0xE0UL |
45 | #define CR14_RESET 0xC2000000UL; | |
46 | ||
f45748f1 AF |
47 | static void s390_cpu_set_pc(CPUState *cs, vaddr value) |
48 | { | |
49 | S390CPU *cpu = S390_CPU(cs); | |
50 | ||
51 | cpu->env.psw.addr = value; | |
52 | } | |
53 | ||
8c2e1b00 AF |
54 | static bool s390_cpu_has_work(CPUState *cs) |
55 | { | |
56 | S390CPU *cpu = S390_CPU(cs); | |
57 | CPUS390XState *env = &cpu->env; | |
58 | ||
59 | return (cs->interrupt_request & CPU_INTERRUPT_HARD) && | |
60 | (env->psw.mask & PSW_MASK_EXT); | |
61 | } | |
62 | ||
29c6157c CB |
63 | #if !defined(CONFIG_USER_ONLY) |
64 | /* S390CPUClass::load_normal() */ | |
65 | static void s390_cpu_load_normal(CPUState *s) | |
66 | { | |
67 | S390CPU *cpu = S390_CPU(s); | |
fdfba1a2 | 68 | cpu->env.psw.addr = ldl_phys(s->as, 4) & PSW_MASK_ESA_ADDR; |
29c6157c | 69 | cpu->env.psw.mask = PSW_MASK_32 | PSW_MASK_64; |
eb24f7c6 | 70 | s390_cpu_set_state(CPU_STATE_OPERATING, cpu); |
29c6157c CB |
71 | } |
72 | #endif | |
73 | ||
f5ae2a4f | 74 | /* S390CPUClass::cpu_reset() */ |
29e4bcb2 AF |
75 | static void s390_cpu_reset(CPUState *s) |
76 | { | |
77 | S390CPU *cpu = S390_CPU(s); | |
78 | S390CPUClass *scc = S390_CPU_GET_CLASS(cpu); | |
79 | CPUS390XState *env = &cpu->env; | |
80 | ||
819bd309 | 81 | env->pfault_token = -1UL; |
f5ae2a4f | 82 | scc->parent_reset(s); |
18ff9494 | 83 | cpu->env.sigp_order = 0; |
eb24f7c6 | 84 | s390_cpu_set_state(CPU_STATE_STOPPED, cpu); |
f5ae2a4f CB |
85 | } |
86 | ||
87 | /* S390CPUClass::initial_reset() */ | |
88 | static void s390_cpu_initial_reset(CPUState *s) | |
89 | { | |
90 | S390CPU *cpu = S390_CPU(s); | |
91 | CPUS390XState *env = &cpu->env; | |
cc0d079d | 92 | int i; |
f5ae2a4f CB |
93 | |
94 | s390_cpu_reset(s); | |
95 | /* initial reset does not touch regs,fregs and aregs */ | |
1f5c00cf | 96 | memset(&env->fpc, 0, offsetof(CPUS390XState, end_reset_fields) - |
f5ae2a4f CB |
97 | offsetof(CPUS390XState, fpc)); |
98 | ||
99 | /* architectured initial values for CR 0 and 14 */ | |
100 | env->cregs[0] = CR0_RESET; | |
101 | env->cregs[14] = CR14_RESET; | |
819bd309 | 102 | |
3da0ab35 AJ |
103 | /* architectured initial value for Breaking-Event-Address register */ |
104 | env->gbea = 1; | |
105 | ||
819bd309 | 106 | env->pfault_token = -1UL; |
7107e5a7 | 107 | env->ext_index = -1; |
cc0d079d AJ |
108 | for (i = 0; i < ARRAY_SIZE(env->io_index); i++) { |
109 | env->io_index[i] = -1; | |
110 | } | |
49f5c9e9 | 111 | |
4a33565f AJ |
112 | /* tininess for underflow is detected before rounding */ |
113 | set_float_detect_tininess(float_tininess_before_rounding, | |
114 | &env->fpu_status); | |
115 | ||
49f5c9e9 TH |
116 | /* Reset state inside the kernel that we cannot access yet from QEMU. */ |
117 | if (kvm_enabled()) { | |
99607144 | 118 | kvm_s390_reset_vcpu(cpu); |
49f5c9e9 | 119 | } |
f5ae2a4f CB |
120 | } |
121 | ||
122 | /* CPUClass:reset() */ | |
123 | static void s390_cpu_full_reset(CPUState *s) | |
124 | { | |
125 | S390CPU *cpu = S390_CPU(s); | |
126 | S390CPUClass *scc = S390_CPU_GET_CLASS(cpu); | |
127 | CPUS390XState *env = &cpu->env; | |
cc0d079d | 128 | int i; |
f5ae2a4f | 129 | |
29e4bcb2 | 130 | scc->parent_reset(s); |
18ff9494 | 131 | cpu->env.sigp_order = 0; |
eb24f7c6 | 132 | s390_cpu_set_state(CPU_STATE_STOPPED, cpu); |
29e4bcb2 | 133 | |
1f5c00cf | 134 | memset(env, 0, offsetof(CPUS390XState, end_reset_fields)); |
70bada03 JF |
135 | |
136 | /* architectured initial values for CR 0 and 14 */ | |
137 | env->cregs[0] = CR0_RESET; | |
138 | env->cregs[14] = CR14_RESET; | |
819bd309 | 139 | |
3da0ab35 AJ |
140 | /* architectured initial value for Breaking-Event-Address register */ |
141 | env->gbea = 1; | |
142 | ||
819bd309 | 143 | env->pfault_token = -1UL; |
7107e5a7 | 144 | env->ext_index = -1; |
cc0d079d AJ |
145 | for (i = 0; i < ARRAY_SIZE(env->io_index); i++) { |
146 | env->io_index[i] = -1; | |
147 | } | |
819bd309 | 148 | |
4a33565f AJ |
149 | /* tininess for underflow is detected before rounding */ |
150 | set_float_detect_tininess(float_tininess_before_rounding, | |
151 | &env->fpu_status); | |
152 | ||
99607144 | 153 | /* Reset state inside the kernel that we cannot access yet from QEMU. */ |
50a2c6e5 PB |
154 | if (kvm_enabled()) { |
155 | kvm_s390_reset_vcpu(cpu); | |
156 | } | |
29e4bcb2 AF |
157 | } |
158 | ||
70bada03 JF |
159 | #if !defined(CONFIG_USER_ONLY) |
160 | static void s390_cpu_machine_reset_cb(void *opaque) | |
161 | { | |
162 | S390CPU *cpu = opaque; | |
163 | ||
14e6fe12 | 164 | run_on_cpu(CPU(cpu), s390_do_cpu_full_reset, RUN_ON_CPU_NULL); |
70bada03 JF |
165 | } |
166 | #endif | |
167 | ||
dbad6b74 PC |
168 | static void s390_cpu_disas_set_info(CPUState *cpu, disassemble_info *info) |
169 | { | |
170 | info->mach = bfd_mach_s390_64; | |
171 | info->print_insn = print_insn_s390; | |
172 | } | |
173 | ||
1f136632 AF |
174 | static void s390_cpu_realizefn(DeviceState *dev, Error **errp) |
175 | { | |
14a10fc3 | 176 | CPUState *cs = CPU(dev); |
1f136632 | 177 | S390CPUClass *scc = S390_CPU_GET_CLASS(dev); |
c6644fc8 MR |
178 | S390CPU *cpu = S390_CPU(dev); |
179 | CPUS390XState *env = &cpu->env; | |
180 | Error *err = NULL; | |
181 | ||
41868f84 DH |
182 | /* the model has to be realized before qemu_init_vcpu() due to kvm */ |
183 | s390_realize_cpu_model(cs, &err); | |
184 | if (err) { | |
185 | goto out; | |
186 | } | |
187 | ||
96b1a8bb MR |
188 | #if !defined(CONFIG_USER_ONLY) |
189 | if (cpu->id >= max_cpus) { | |
190 | error_setg(&err, "Unable to add CPU: %" PRIi64 | |
191 | ", max allowed: %d", cpu->id, max_cpus - 1); | |
192 | goto out; | |
193 | } | |
194 | #endif | |
195 | if (cpu_exists(cpu->id)) { | |
196 | error_setg(&err, "Unable to add CPU: %" PRIi64 | |
197 | ", it already exists", cpu->id); | |
198 | goto out; | |
199 | } | |
200 | if (cpu->id != scc->next_cpu_id) { | |
201 | error_setg(&err, "Unable to add CPU: %" PRIi64 | |
202 | ", The next available id is %" PRIi64, cpu->id, | |
203 | scc->next_cpu_id); | |
204 | goto out; | |
205 | } | |
206 | ||
ce5b1bbf | 207 | cpu_exec_realizefn(cs, &err); |
c6644fc8 | 208 | if (err != NULL) { |
96b1a8bb | 209 | goto out; |
c6644fc8 | 210 | } |
96b1a8bb | 211 | scc->next_cpu_id++; |
1f136632 | 212 | |
c6644fc8 MR |
213 | #if !defined(CONFIG_USER_ONLY) |
214 | qemu_register_reset(s390_cpu_machine_reset_cb, cpu); | |
215 | #endif | |
96b1a8bb | 216 | env->cpu_num = cpu->id; |
73d510c9 | 217 | s390_cpu_gdb_init(cs); |
14a10fc3 | 218 | qemu_init_vcpu(cs); |
159855f0 | 219 | #if !defined(CONFIG_USER_ONLY) |
14e6fe12 | 220 | run_on_cpu(cs, s390_do_cpu_full_reset, RUN_ON_CPU_NULL); |
159855f0 | 221 | #else |
14a10fc3 | 222 | cpu_reset(cs); |
159855f0 | 223 | #endif |
1f136632 | 224 | |
96b1a8bb MR |
225 | scc->parent_realize(dev, &err); |
226 | ||
a006b67f MR |
227 | #if !defined(CONFIG_USER_ONLY) |
228 | if (dev->hotplugged) { | |
229 | raise_irq_cpu_hotplug(); | |
230 | } | |
231 | #endif | |
232 | ||
96b1a8bb MR |
233 | out: |
234 | error_propagate(errp, err); | |
235 | } | |
236 | ||
237 | static void s390x_cpu_get_id(Object *obj, Visitor *v, const char *name, | |
238 | void *opaque, Error **errp) | |
239 | { | |
240 | S390CPU *cpu = S390_CPU(obj); | |
241 | int64_t value = cpu->id; | |
242 | ||
243 | visit_type_int(v, name, &value, errp); | |
244 | } | |
245 | ||
246 | static void s390x_cpu_set_id(Object *obj, Visitor *v, const char *name, | |
247 | void *opaque, Error **errp) | |
248 | { | |
249 | S390CPU *cpu = S390_CPU(obj); | |
250 | DeviceState *dev = DEVICE(obj); | |
251 | const int64_t min = 0; | |
252 | const int64_t max = UINT32_MAX; | |
253 | Error *err = NULL; | |
254 | int64_t value; | |
255 | ||
256 | if (dev->realized) { | |
257 | error_setg(errp, "Attempt to set property '%s' on '%s' after " | |
258 | "it was realized", name, object_get_typename(obj)); | |
259 | return; | |
260 | } | |
261 | ||
262 | visit_type_int(v, name, &value, &err); | |
263 | if (err) { | |
264 | error_propagate(errp, err); | |
265 | return; | |
266 | } | |
267 | if (value < min || value > max) { | |
268 | error_setg(errp, "Property %s.%s doesn't take value %" PRId64 | |
269 | " (minimum: %" PRId64 ", maximum: %" PRId64 ")" , | |
270 | object_get_typename(obj), name, value, min, max); | |
271 | return; | |
272 | } | |
273 | cpu->id = value; | |
1f136632 AF |
274 | } |
275 | ||
8f22e0df AF |
276 | static void s390_cpu_initfn(Object *obj) |
277 | { | |
c05efcb1 | 278 | CPUState *cs = CPU(obj); |
8f22e0df AF |
279 | S390CPU *cpu = S390_CPU(obj); |
280 | CPUS390XState *env = &cpu->env; | |
2b7ac767 | 281 | static bool inited; |
8f22e0df AF |
282 | #if !defined(CONFIG_USER_ONLY) |
283 | struct tm tm; | |
284 | #endif | |
285 | ||
c05efcb1 | 286 | cs->env_ptr = env; |
ef3027af MR |
287 | cs->halted = 1; |
288 | cs->exception_index = EXCP_HLT; | |
96b1a8bb MR |
289 | object_property_add(OBJECT(cpu), "id", "int64_t", s390x_cpu_get_id, |
290 | s390x_cpu_set_id, NULL, NULL, NULL); | |
0754f604 | 291 | s390_cpu_model_register_props(obj); |
8f22e0df AF |
292 | #if !defined(CONFIG_USER_ONLY) |
293 | qemu_get_timedate(&tm, 0); | |
294 | env->tod_offset = TOD_UNIX_EPOCH + | |
295 | (time2tod(mktimegm(&tm)) * 1000000000ULL); | |
296 | env->tod_basetime = 0; | |
bc72ad67 AB |
297 | env->tod_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, s390x_tod_timer, cpu); |
298 | env->cpu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, s390x_cpu_timer, cpu); | |
eb24f7c6 | 299 | s390_cpu_set_state(CPU_STATE_STOPPED, cpu); |
8f22e0df | 300 | #endif |
2b7ac767 AF |
301 | |
302 | if (tcg_enabled() && !inited) { | |
303 | inited = true; | |
304 | s390x_translate_init(); | |
305 | } | |
8f22e0df AF |
306 | } |
307 | ||
d5627ce8 AF |
308 | static void s390_cpu_finalize(Object *obj) |
309 | { | |
310 | #if !defined(CONFIG_USER_ONLY) | |
311 | S390CPU *cpu = S390_CPU(obj); | |
312 | ||
313 | qemu_unregister_reset(s390_cpu_machine_reset_cb, cpu); | |
3cda44f7 | 314 | g_free(cpu->irqstate); |
d5627ce8 AF |
315 | #endif |
316 | } | |
317 | ||
75973bfe | 318 | #if !defined(CONFIG_USER_ONLY) |
eb24f7c6 DH |
319 | static bool disabled_wait(CPUState *cpu) |
320 | { | |
321 | return cpu->halted && !(S390_CPU(cpu)->env.psw.mask & | |
322 | (PSW_MASK_IO | PSW_MASK_EXT | PSW_MASK_MCHECK)); | |
323 | } | |
324 | ||
75973bfe DH |
325 | static unsigned s390_count_running_cpus(void) |
326 | { | |
327 | CPUState *cpu; | |
328 | int nr_running = 0; | |
329 | ||
330 | CPU_FOREACH(cpu) { | |
331 | uint8_t state = S390_CPU(cpu)->env.cpu_state; | |
332 | if (state == CPU_STATE_OPERATING || | |
333 | state == CPU_STATE_LOAD) { | |
eb24f7c6 DH |
334 | if (!disabled_wait(cpu)) { |
335 | nr_running++; | |
336 | } | |
75973bfe DH |
337 | } |
338 | } | |
339 | ||
340 | return nr_running; | |
341 | } | |
342 | ||
eb24f7c6 | 343 | unsigned int s390_cpu_halt(S390CPU *cpu) |
75973bfe DH |
344 | { |
345 | CPUState *cs = CPU(cpu); | |
eb24f7c6 | 346 | trace_cpu_halt(cs->cpu_index); |
75973bfe | 347 | |
eb24f7c6 DH |
348 | if (!cs->halted) { |
349 | cs->halted = 1; | |
350 | cs->exception_index = EXCP_HLT; | |
75973bfe | 351 | } |
eb24f7c6 DH |
352 | |
353 | return s390_count_running_cpus(); | |
75973bfe DH |
354 | } |
355 | ||
eb24f7c6 | 356 | void s390_cpu_unhalt(S390CPU *cpu) |
75973bfe DH |
357 | { |
358 | CPUState *cs = CPU(cpu); | |
eb24f7c6 | 359 | trace_cpu_unhalt(cs->cpu_index); |
75973bfe | 360 | |
eb24f7c6 DH |
361 | if (cs->halted) { |
362 | cs->halted = 0; | |
363 | cs->exception_index = -1; | |
364 | } | |
365 | } | |
366 | ||
367 | unsigned int s390_cpu_set_state(uint8_t cpu_state, S390CPU *cpu) | |
368 | { | |
369 | trace_cpu_set_state(CPU(cpu)->cpu_index, cpu_state); | |
370 | ||
371 | switch (cpu_state) { | |
372 | case CPU_STATE_STOPPED: | |
373 | case CPU_STATE_CHECK_STOP: | |
374 | /* halt the cpu for common infrastructure */ | |
375 | s390_cpu_halt(cpu); | |
376 | break; | |
377 | case CPU_STATE_OPERATING: | |
378 | case CPU_STATE_LOAD: | |
379 | /* unhalt the cpu for common infrastructure */ | |
380 | s390_cpu_unhalt(cpu); | |
381 | break; | |
382 | default: | |
383 | error_report("Requested CPU state is not a valid S390 CPU state: %u", | |
384 | cpu_state); | |
385 | exit(1); | |
75973bfe | 386 | } |
c9e659c9 DH |
387 | if (kvm_enabled() && cpu->env.cpu_state != cpu_state) { |
388 | kvm_s390_set_cpu_state(cpu, cpu_state); | |
389 | } | |
eb24f7c6 | 390 | cpu->env.cpu_state = cpu_state; |
75973bfe DH |
391 | |
392 | return s390_count_running_cpus(); | |
393 | } | |
394 | #endif | |
395 | ||
b3820e6c DH |
396 | static gchar *s390_gdb_arch_name(CPUState *cs) |
397 | { | |
398 | return g_strdup("s390:64-bit"); | |
399 | } | |
400 | ||
29e4bcb2 AF |
401 | static void s390_cpu_class_init(ObjectClass *oc, void *data) |
402 | { | |
403 | S390CPUClass *scc = S390_CPU_CLASS(oc); | |
404 | CPUClass *cc = CPU_CLASS(scc); | |
c7396bbb | 405 | DeviceClass *dc = DEVICE_CLASS(oc); |
29e4bcb2 | 406 | |
c6644fc8 | 407 | scc->next_cpu_id = 0; |
1f136632 AF |
408 | scc->parent_realize = dc->realize; |
409 | dc->realize = s390_cpu_realizefn; | |
410 | ||
29e4bcb2 | 411 | scc->parent_reset = cc->reset; |
29c6157c CB |
412 | #if !defined(CONFIG_USER_ONLY) |
413 | scc->load_normal = s390_cpu_load_normal; | |
414 | #endif | |
f5ae2a4f CB |
415 | scc->cpu_reset = s390_cpu_reset; |
416 | scc->initial_cpu_reset = s390_cpu_initial_reset; | |
417 | cc->reset = s390_cpu_full_reset; | |
41868f84 | 418 | cc->class_by_name = s390_cpu_class_by_name, |
8c2e1b00 | 419 | cc->has_work = s390_cpu_has_work; |
97a8ea5a | 420 | cc->do_interrupt = s390_cpu_do_interrupt; |
878096ee | 421 | cc->dump_state = s390_cpu_dump_state; |
f45748f1 | 422 | cc->set_pc = s390_cpu_set_pc; |
5b50e790 AF |
423 | cc->gdb_read_register = s390_cpu_gdb_read_register; |
424 | cc->gdb_write_register = s390_cpu_gdb_write_register; | |
7510454e AF |
425 | #ifdef CONFIG_USER_ONLY |
426 | cc->handle_mmu_fault = s390_cpu_handle_mmu_fault; | |
427 | #else | |
00b941e5 | 428 | cc->get_phys_page_debug = s390_cpu_get_phys_page_debug; |
ef1df130 | 429 | cc->vmsd = &vmstate_s390_cpu; |
9b4f38e1 | 430 | cc->write_elf64_note = s390_cpu_write_elf64_note; |
02bb9bbf | 431 | cc->cpu_exec_interrupt = s390_cpu_exec_interrupt; |
311918b9 | 432 | cc->debug_excp_handler = s390x_cpu_debug_excp_handler; |
00b941e5 | 433 | #endif |
dbad6b74 PC |
434 | cc->disas_set_info = s390_cpu_disas_set_info; |
435 | ||
73d510c9 DH |
436 | cc->gdb_num_core_regs = S390_NUM_CORE_REGS; |
437 | cc->gdb_core_xml_file = "s390x-core64.xml"; | |
b3820e6c | 438 | cc->gdb_arch_name = s390_gdb_arch_name; |
4c315c27 | 439 | |
6efadc90 | 440 | s390_cpu_model_class_register_props(oc); |
29e4bcb2 AF |
441 | } |
442 | ||
443 | static const TypeInfo s390_cpu_type_info = { | |
444 | .name = TYPE_S390_CPU, | |
445 | .parent = TYPE_CPU, | |
446 | .instance_size = sizeof(S390CPU), | |
8f22e0df | 447 | .instance_init = s390_cpu_initfn, |
d5627ce8 | 448 | .instance_finalize = s390_cpu_finalize, |
41868f84 | 449 | .abstract = true, |
29e4bcb2 AF |
450 | .class_size = sizeof(S390CPUClass), |
451 | .class_init = s390_cpu_class_init, | |
452 | }; | |
453 | ||
454 | static void s390_cpu_register_types(void) | |
455 | { | |
456 | type_register_static(&s390_cpu_type_info); | |
457 | } | |
458 | ||
459 | type_init(s390_cpu_register_types) |