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Commit | Line | Data |
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7b9cbadb AJ |
1 | /* |
2 | * QEMU MIPS interrupt support | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
5 | * of this software and associated documentation files (the "Software"), to deal | |
6 | * in the Software without restriction, including without limitation the rights | |
7 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
8 | * copies of the Software, and to permit persons to whom the Software is | |
9 | * furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
19 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
20 | * THE SOFTWARE. | |
21 | */ | |
22 | ||
87ecb68b | 23 | #include "hw.h" |
b970ea8f | 24 | #include "mips_cpudevs.h" |
4de9b249 TS |
25 | #include "cpu.h" |
26 | ||
d537cf6c | 27 | static void cpu_mips_irq_request(void *opaque, int irq, int level) |
4de9b249 | 28 | { |
61c56c8c | 29 | CPUMIPSState *env = (CPUMIPSState *)opaque; |
4de9b249 | 30 | |
39d51eb8 | 31 | if (irq < 0 || irq > 7) |
4de9b249 TS |
32 | return; |
33 | ||
4de9b249 | 34 | if (level) { |
39d51eb8 | 35 | env->CP0_Cause |= 1 << (irq + CP0Ca_IP); |
4de9b249 | 36 | } else { |
a4bc3afc | 37 | env->CP0_Cause &= ~(1 << (irq + CP0Ca_IP)); |
4de9b249 | 38 | } |
36388314 EI |
39 | |
40 | if (env->CP0_Cause & CP0Ca_IP_mask) { | |
41 | cpu_interrupt(env, CPU_INTERRUPT_HARD); | |
42 | } else { | |
43 | cpu_reset_interrupt(env, CPU_INTERRUPT_HARD); | |
44 | } | |
4de9b249 | 45 | } |
d537cf6c | 46 | |
61c56c8c | 47 | void cpu_mips_irq_init_cpu(CPUMIPSState *env) |
d537cf6c PB |
48 | { |
49 | qemu_irq *qi; | |
50 | int i; | |
51 | ||
52 | qi = qemu_allocate_irqs(cpu_mips_irq_request, env, 8); | |
53 | for (i = 0; i < 8; i++) { | |
54 | env->irq[i] = qi[i]; | |
55 | } | |
56 | } | |
5dc5d9f0 | 57 | |
61c56c8c | 58 | void cpu_mips_soft_irq(CPUMIPSState *env, int irq, int level) |
5dc5d9f0 AJ |
59 | { |
60 | if (irq < 0 || irq > 2) { | |
61 | return; | |
62 | } | |
63 | ||
64 | qemu_set_irq(env->irq[irq], level); | |
65 | } |