[qemu.git] / target / openrisc / cpu.h

/*
 * OpenRISC virtual CPU header.
 *
 * Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com>
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */

#ifndef OPENRISC_CPU_H
#define OPENRISC_CPU_H

#define TARGET_LONG_BITS 32

#define CPUArchState struct CPUOpenRISCState

/* cpu_openrisc_map_address_* in CPUOpenRISCTLBContext need this decl.  */
struct OpenRISCCPU;

#include "qemu-common.h"
#include "exec/cpu-defs.h"
#include "fpu/softfloat.h"
#include "qom/cpu.h"

#define TYPE_OPENRISC_CPU "or1k-cpu"

#define OPENRISC_CPU_CLASS(klass) \
    OBJECT_CLASS_CHECK(OpenRISCCPUClass, (klass), TYPE_OPENRISC_CPU)
#define OPENRISC_CPU(obj) \
    OBJECT_CHECK(OpenRISCCPU, (obj), TYPE_OPENRISC_CPU)
#define OPENRISC_CPU_GET_CLASS(obj) \
    OBJECT_GET_CLASS(OpenRISCCPUClass, (obj), TYPE_OPENRISC_CPU)

/**
 * OpenRISCCPUClass:
 * @parent_realize: The parent class' realize handler.
 * @parent_reset: The parent class' reset handler.
 *
 * A OpenRISC CPU model.
 */
typedef struct OpenRISCCPUClass {
    /*< private >*/
    CPUClass parent_class;
    /*< public >*/

    DeviceRealize parent_realize;
    void (*parent_reset)(CPUState *cpu);
} OpenRISCCPUClass;

#define NB_MMU_MODES    3

enum {
    MMU_NOMMU_IDX = 0,
    MMU_SUPERVISOR_IDX = 1,
    MMU_USER_IDX = 2,
};

#define TARGET_PAGE_BITS 13

#define TARGET_PHYS_ADDR_SPACE_BITS 32
#define TARGET_VIRT_ADDR_SPACE_BITS 32

#define SET_FP_CAUSE(reg, v)    do {\
                                    (reg) = ((reg) & ~(0x3f << 12)) | \
                                            ((v & 0x3f) << 12);\
                                } while (0)
#define GET_FP_ENABLE(reg)       (((reg) >>  7) & 0x1f)
#define UPDATE_FP_FLAGS(reg, v)   do {\
                                      (reg) |= ((v & 0x1f) << 2);\
                                  } while (0)

/* Version Register */
#define SPR_VR 0xFFFF003F

/* Internal flags, delay slot flag */
#define D_FLAG    1

/* Interrupt */
#define NR_IRQS  32

/* Unit presece register */
enum {
    UPR_UP = (1 << 0),
    UPR_DCP = (1 << 1),
    UPR_ICP = (1 << 2),
    UPR_DMP = (1 << 3),
    UPR_IMP = (1 << 4),
    UPR_MP = (1 << 5),
    UPR_DUP = (1 << 6),
    UPR_PCUR = (1 << 7),
    UPR_PMP = (1 << 8),
    UPR_PICP = (1 << 9),
    UPR_TTP = (1 << 10),
    UPR_CUP = (255 << 24),
};

/* CPU configure register */
enum {
    CPUCFGR_NSGF = (15 << 0),
    CPUCFGR_CGF = (1 << 4),
    CPUCFGR_OB32S = (1 << 5),
    CPUCFGR_OB64S = (1 << 6),
    CPUCFGR_OF32S = (1 << 7),
    CPUCFGR_OF64S = (1 << 8),
    CPUCFGR_OV64S = (1 << 9),
};

/* DMMU configure register */
enum {
    DMMUCFGR_NTW = (3 << 0),
    DMMUCFGR_NTS = (7 << 2),
    DMMUCFGR_NAE = (7 << 5),
    DMMUCFGR_CRI = (1 << 8),
    DMMUCFGR_PRI = (1 << 9),
    DMMUCFGR_TEIRI = (1 << 10),
    DMMUCFGR_HTR = (1 << 11),
};

/* IMMU configure register */
enum {
    IMMUCFGR_NTW = (3 << 0),
    IMMUCFGR_NTS = (7 << 2),
    IMMUCFGR_NAE = (7 << 5),
    IMMUCFGR_CRI = (1 << 8),
    IMMUCFGR_PRI = (1 << 9),
    IMMUCFGR_TEIRI = (1 << 10),
    IMMUCFGR_HTR = (1 << 11),
};

/* Float point control status register */
enum {
    FPCSR_FPEE = 1,
    FPCSR_RM = (3 << 1),
    FPCSR_OVF = (1 << 3),
    FPCSR_UNF = (1 << 4),
    FPCSR_SNF = (1 << 5),
    FPCSR_QNF = (1 << 6),
    FPCSR_ZF = (1 << 7),
    FPCSR_IXF = (1 << 8),
    FPCSR_IVF = (1 << 9),
    FPCSR_INF = (1 << 10),
    FPCSR_DZF = (1 << 11),
};

/* Exceptions indices */
enum {
    EXCP_RESET    = 0x1,
    EXCP_BUSERR   = 0x2,
    EXCP_DPF      = 0x3,
    EXCP_IPF      = 0x4,
    EXCP_TICK     = 0x5,
    EXCP_ALIGN    = 0x6,
    EXCP_ILLEGAL  = 0x7,
    EXCP_INT      = 0x8,
    EXCP_DTLBMISS = 0x9,
    EXCP_ITLBMISS = 0xa,
    EXCP_RANGE    = 0xb,
    EXCP_SYSCALL  = 0xc,
    EXCP_FPE      = 0xd,
    EXCP_TRAP     = 0xe,
    EXCP_NR,
};

/* Supervisor register */
enum {
    SR_SM = (1 << 0),
    SR_TEE = (1 << 1),
    SR_IEE = (1 << 2),
    SR_DCE = (1 << 3),
    SR_ICE = (1 << 4),
    SR_DME = (1 << 5),
    SR_IME = (1 << 6),
    SR_LEE = (1 << 7),
    SR_CE  = (1 << 8),
    SR_F   = (1 << 9),
    SR_CY  = (1 << 10),
    SR_OV  = (1 << 11),
    SR_OVE = (1 << 12),
    SR_DSX = (1 << 13),
    SR_EPH = (1 << 14),
    SR_FO  = (1 << 15),
    SR_SUMRA = (1 << 16),
    SR_SCE = (1 << 17),
};

/* OpenRISC Hardware Capabilities */
enum {
    OPENRISC_FEATURE_NSGF = (15 << 0),
    OPENRISC_FEATURE_CGF = (1 << 4),
    OPENRISC_FEATURE_OB32S = (1 << 5),
    OPENRISC_FEATURE_OB64S = (1 << 6),
    OPENRISC_FEATURE_OF32S = (1 << 7),
    OPENRISC_FEATURE_OF64S = (1 << 8),
    OPENRISC_FEATURE_OV64S = (1 << 9),
};

/* Tick Timer Mode Register */
enum {
    TTMR_TP = (0xfffffff),
    TTMR_IP = (1 << 28),
    TTMR_IE = (1 << 29),
    TTMR_M  = (3 << 30),
};

/* Timer Mode */
enum {
    TIMER_NONE = (0 << 30),
    TIMER_INTR = (1 << 30),
    TIMER_SHOT = (2 << 30),
    TIMER_CONT = (3 << 30),
};

/* TLB size */
enum {
    DTLB_WAYS = 1,
    DTLB_SIZE = 64,
    DTLB_MASK = (DTLB_SIZE-1),
    ITLB_WAYS = 1,
    ITLB_SIZE = 64,
    ITLB_MASK = (ITLB_SIZE-1),
};

/* TLB prot */
enum {
    URE = (1 << 6),
    UWE = (1 << 7),
    SRE = (1 << 8),
    SWE = (1 << 9),

    SXE = (1 << 6),
    UXE = (1 << 7),
};

/* check if tlb available */
enum {
    TLBRET_INVALID = -3,
    TLBRET_NOMATCH = -2,
    TLBRET_BADADDR = -1,
    TLBRET_MATCH = 0
};

typedef struct OpenRISCTLBEntry {
    uint32_t mr;
    uint32_t tr;
} OpenRISCTLBEntry;

#ifndef CONFIG_USER_ONLY
typedef struct CPUOpenRISCTLBContext {
    OpenRISCTLBEntry itlb[ITLB_WAYS][ITLB_SIZE];
    OpenRISCTLBEntry dtlb[DTLB_WAYS][DTLB_SIZE];

    int (*cpu_openrisc_map_address_code)(struct OpenRISCCPU *cpu,
                                         hwaddr *physical,
                                         int *prot,
                                         target_ulong address, int rw);
    int (*cpu_openrisc_map_address_data)(struct OpenRISCCPU *cpu,
                                         hwaddr *physical,
                                         int *prot,
                                         target_ulong address, int rw);
} CPUOpenRISCTLBContext;
#endif

typedef struct CPUOpenRISCState {
    target_ulong gpr[32];     /* General registers */
    target_ulong pc;          /* Program counter */
    target_ulong npc;         /* Next PC */
    target_ulong ppc;         /* Prev PC */
    target_ulong jmp_pc;      /* Jump PC */

    uint64_t mac;             /* Multiply registers MACHI:MACLO */

    target_ulong fpmaddhi;    /* Multiply and add float register FPMADDHI */
    target_ulong fpmaddlo;    /* Multiply and add float register FPMADDLO */

    target_ulong epcr;        /* Exception PC register */
    target_ulong eear;        /* Exception EA register */

    target_ulong sr_f;        /* the SR_F bit, values 0, 1.  */
    target_ulong sr_cy;       /* the SR_CY bit, values 0, 1.  */
    target_long  sr_ov;       /* the SR_OV bit (in the sign bit only) */
    uint32_t sr;              /* Supervisor register, without SR_{F,CY,OV} */
    uint32_t vr;              /* Version register */
    uint32_t upr;             /* Unit presence register */
    uint32_t cpucfgr;         /* CPU configure register */
    uint32_t dmmucfgr;        /* DMMU configure register */
    uint32_t immucfgr;        /* IMMU configure register */
    uint32_t esr;             /* Exception supervisor register */
    uint32_t fpcsr;           /* Float register */
    float_status fp_status;

    target_ulong lock_addr;
    target_ulong lock_value;

    uint32_t flags;           /* cpu_flags, we only use it for exception
                                 in solt so far.  */

    /* Fields up to this point are cleared by a CPU reset */
    struct {} end_reset_fields;

    CPU_COMMON

    /* Fields from here on are preserved across CPU reset. */
#ifndef CONFIG_USER_ONLY
    CPUOpenRISCTLBContext * tlb;

    QEMUTimer *timer;
    uint32_t ttmr;          /* Timer tick mode register */
    uint32_t ttcr;          /* Timer tick count register */

    uint32_t picmr;         /* Interrupt mask register */
    uint32_t picsr;         /* Interrupt contrl register*/
#endif
    void *irq[32];          /* Interrupt irq input */
} CPUOpenRISCState;

/**
 * OpenRISCCPU:
 * @env: #CPUOpenRISCState
 *
 * A OpenRISC CPU.
 */
typedef struct OpenRISCCPU {
    /*< private >*/
    CPUState parent_obj;
    /*< public >*/

    CPUOpenRISCState env;

    uint32_t feature;       /* CPU Capabilities */
} OpenRISCCPU;

static inline OpenRISCCPU *openrisc_env_get_cpu(CPUOpenRISCState *env)
{
    return container_of(env, OpenRISCCPU, env);
}

#define ENV_GET_CPU(e) CPU(openrisc_env_get_cpu(e))

#define ENV_OFFSET offsetof(OpenRISCCPU, env)

OpenRISCCPU *cpu_openrisc_init(const char *cpu_model);

void cpu_openrisc_list(FILE *f, fprintf_function cpu_fprintf);
void openrisc_cpu_do_interrupt(CPUState *cpu);
bool openrisc_cpu_exec_interrupt(CPUState *cpu, int int_req);
void openrisc_cpu_dump_state(CPUState *cpu, FILE *f,
                             fprintf_function cpu_fprintf, int flags);
hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
int openrisc_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
int openrisc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
void openrisc_translate_init(void);
int openrisc_cpu_handle_mmu_fault(CPUState *cpu, vaddr address,
                                  int rw, int mmu_idx);
int cpu_openrisc_signal_handler(int host_signum, void *pinfo, void *puc);

#define cpu_list cpu_openrisc_list
#define cpu_signal_handler cpu_openrisc_signal_handler

#ifndef CONFIG_USER_ONLY
extern const struct VMStateDescription vmstate_openrisc_cpu;

/* hw/openrisc_pic.c */
void cpu_openrisc_pic_init(OpenRISCCPU *cpu);

/* hw/openrisc_timer.c */
void cpu_openrisc_clock_init(OpenRISCCPU *cpu);
void cpu_openrisc_count_update(OpenRISCCPU *cpu);
void cpu_openrisc_timer_update(OpenRISCCPU *cpu);
void cpu_openrisc_count_start(OpenRISCCPU *cpu);
void cpu_openrisc_count_stop(OpenRISCCPU *cpu);

void cpu_openrisc_mmu_init(OpenRISCCPU *cpu);
int cpu_openrisc_get_phys_nommu(OpenRISCCPU *cpu,
                                hwaddr *physical,
                                int *prot, target_ulong address, int rw);
int cpu_openrisc_get_phys_code(OpenRISCCPU *cpu,
                               hwaddr *physical,
                               int *prot, target_ulong address, int rw);
int cpu_openrisc_get_phys_data(OpenRISCCPU *cpu,
                               hwaddr *physical,
                               int *prot, target_ulong address, int rw);
#endif

#define cpu_init(cpu_model) CPU(cpu_openrisc_init(cpu_model))

#include "exec/cpu-all.h"

static inline void cpu_get_tb_cpu_state(CPUOpenRISCState *env,
                                        target_ulong *pc,
                                        target_ulong *cs_base, uint32_t *flags)
{
    *pc = env->pc;
    *cs_base = 0;
    /* D_FLAG -- branch instruction exception, OVE overflow trap enable.  */
    *flags = (env->flags & D_FLAG) | (env->sr & SR_OVE);
}

static inline int cpu_mmu_index(CPUOpenRISCState *env, bool ifetch)
{
    if (!(env->sr & SR_IME)) {
        return MMU_NOMMU_IDX;
    }
    return (env->sr & SR_SM) == 0 ? MMU_USER_IDX : MMU_SUPERVISOR_IDX;
}

static inline uint32_t cpu_get_sr(const CPUOpenRISCState *env)
{
    return (env->sr
            + env->sr_f * SR_F
            + env->sr_cy * SR_CY
            + (env->sr_ov < 0) * SR_OV);
}

static inline void cpu_set_sr(CPUOpenRISCState *env, uint32_t val)
{
    env->sr_f = (val & SR_F) != 0;
    env->sr_cy = (val & SR_CY) != 0;
    env->sr_ov = (val & SR_OV ? -1 : 0);
    env->sr = (val & ~(SR_F | SR_CY | SR_OV)) | SR_FO;
}

#define CPU_INTERRUPT_TIMER   CPU_INTERRUPT_TGT_INT_0

#endif /* OPENRISC_CPU_H */
Commit	Line	Data
e67db06e JL	1	/*
	2	* OpenRISC virtual CPU header.
	3	*
	4	* Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com>
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
	9	* version 2 of the License, or (at your option) any later version.
	10	*
	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
	17	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
	18	*/
	19
07f5a258 MA	20	#ifndef OPENRISC_CPU_H
07f5a258 MA	21	#define OPENRISC_CPU_H
e67db06e JL	22
e67db06e JL	23	#define TARGET_LONG_BITS 32
e67db06e JL	24
	25	#define CPUArchState struct CPUOpenRISCState
	26
726fe045 JL	27	/* cpu_openrisc_map_address_* in CPUOpenRISCTLBContext need this decl. */
	28	struct OpenRISCCPU;
	29
e67db06e	30	#include "qemu-common.h"
022c62cb	31	#include "exec/cpu-defs.h"
6b4c305c	32	#include "fpu/softfloat.h"
14cccb61	33	#include "qom/cpu.h"
e67db06e	34
4a09d0bb	35	#define TYPE_OPENRISC_CPU "or1k-cpu"
e67db06e JL	36
	37	#define OPENRISC_CPU_CLASS(klass) \
	38	OBJECT_CLASS_CHECK(OpenRISCCPUClass, (klass), TYPE_OPENRISC_CPU)
	39	#define OPENRISC_CPU(obj) \
	40	OBJECT_CHECK(OpenRISCCPU, (obj), TYPE_OPENRISC_CPU)
	41	#define OPENRISC_CPU_GET_CLASS(obj) \
	42	OBJECT_GET_CLASS(OpenRISCCPUClass, (obj), TYPE_OPENRISC_CPU)
	43
	44	/**
	45	* OpenRISCCPUClass:
c296262b	46	* @parent_realize: The parent class' realize handler.
e67db06e JL	47	* @parent_reset: The parent class' reset handler.
	48	*
	49	* A OpenRISC CPU model.
	50	*/
	51	typedef struct OpenRISCCPUClass {
	52	/< private >/
	53	CPUClass parent_class;
	54	/< public >/
	55
c296262b	56	DeviceRealize parent_realize;
e67db06e JL	57	void (parent_reset)(CPUState cpu);
	58	} OpenRISCCPUClass;
	59
	60	#define NB_MMU_MODES 3
	61
726fe045 JL	62	enum {
	63	MMU_NOMMU_IDX = 0,
	64	MMU_SUPERVISOR_IDX = 1,
	65	MMU_USER_IDX = 2,
	66	};
	67
e67db06e JL	68	#define TARGET_PAGE_BITS 13
	69
	70	#define TARGET_PHYS_ADDR_SPACE_BITS 32
	71	#define TARGET_VIRT_ADDR_SPACE_BITS 32
	72
	73	#define SET_FP_CAUSE(reg, v) do {\
	74	(reg) = ((reg) & ~(0x3f << 12)) \| \
	75	((v & 0x3f) << 12);\
	76	} while (0)
	77	#define GET_FP_ENABLE(reg) (((reg) >> 7) & 0x1f)
	78	#define UPDATE_FP_FLAGS(reg, v) do {\
	79	(reg) \|= ((v & 0x1f) << 2);\
	80	} while (0)
	81
4dd044c6 JL	82	/* Version Register */
	83	#define SPR_VR 0xFFFF003F
	84
e67db06e JL	85	/* Internal flags, delay slot flag */
	86	#define D_FLAG 1
	87
b6a71ef7 JL	88	/* Interrupt */
	89	#define NR_IRQS 32
	90
e67db06e JL	91	/* Unit presece register */
	92	enum {
	93	UPR_UP = (1 << 0),
	94	UPR_DCP = (1 << 1),
	95	UPR_ICP = (1 << 2),
	96	UPR_DMP = (1 << 3),
	97	UPR_IMP = (1 << 4),
	98	UPR_MP = (1 << 5),
	99	UPR_DUP = (1 << 6),
	100	UPR_PCUR = (1 << 7),
	101	UPR_PMP = (1 << 8),
	102	UPR_PICP = (1 << 9),
	103	UPR_TTP = (1 << 10),
	104	UPR_CUP = (255 << 24),
	105	};
	106
	107	/* CPU configure register */
	108	enum {
	109	CPUCFGR_NSGF = (15 << 0),
	110	CPUCFGR_CGF = (1 << 4),
	111	CPUCFGR_OB32S = (1 << 5),
	112	CPUCFGR_OB64S = (1 << 6),
	113	CPUCFGR_OF32S = (1 << 7),
	114	CPUCFGR_OF64S = (1 << 8),
	115	CPUCFGR_OV64S = (1 << 9),
	116	};
	117
	118	/* DMMU configure register */
	119	enum {
	120	DMMUCFGR_NTW = (3 << 0),
	121	DMMUCFGR_NTS = (7 << 2),
	122	DMMUCFGR_NAE = (7 << 5),
	123	DMMUCFGR_CRI = (1 << 8),
	124	DMMUCFGR_PRI = (1 << 9),
	125	DMMUCFGR_TEIRI = (1 << 10),
	126	DMMUCFGR_HTR = (1 << 11),
	127	};
	128
	129	/* IMMU configure register */
	130	enum {
	131	IMMUCFGR_NTW = (3 << 0),
	132	IMMUCFGR_NTS = (7 << 2),
	133	IMMUCFGR_NAE = (7 << 5),
	134	IMMUCFGR_CRI = (1 << 8),
	135	IMMUCFGR_PRI = (1 << 9),
	136	IMMUCFGR_TEIRI = (1 << 10),
	137	IMMUCFGR_HTR = (1 << 11),
	138	};
	139
	140	/* Float point control status register */
	141	enum {
	142	FPCSR_FPEE = 1,
	143	FPCSR_RM = (3 << 1),
	144	FPCSR_OVF = (1 << 3),
	145	FPCSR_UNF = (1 << 4),
	146	FPCSR_SNF = (1 << 5),
	147	FPCSR_QNF = (1 << 6),
	148	FPCSR_ZF = (1 << 7),
	149	FPCSR_IXF = (1 << 8),
	150	FPCSR_IVF = (1 << 9),
	151	FPCSR_INF = (1 << 10),
	152	FPCSR_DZF = (1 << 11),
	153	};
	154
155	/* Exceptions indices */
156	enum {
157	EXCP_RESET = 0x1,
158	EXCP_BUSERR = 0x2,
159	EXCP_DPF = 0x3,
160	EXCP_IPF = 0x4,
161	EXCP_TICK = 0x5,
162	EXCP_ALIGN = 0x6,
163	EXCP_ILLEGAL = 0x7,
164	EXCP_INT = 0x8,
165	EXCP_DTLBMISS = 0x9,
166	EXCP_ITLBMISS = 0xa,
167	EXCP_RANGE = 0xb,
168	EXCP_SYSCALL = 0xc,
169	EXCP_FPE = 0xd,
170	EXCP_TRAP = 0xe,
171	EXCP_NR,
172	};
173
174	/* Supervisor register */
175	enum {
176	SR_SM = (1 << 0),
177	SR_TEE = (1 << 1),
178	SR_IEE = (1 << 2),
179	SR_DCE = (1 << 3),
180	SR_ICE = (1 << 4),
181	SR_DME = (1 << 5),
182	SR_IME = (1 << 6),
183	SR_LEE = (1 << 7),
184	SR_CE = (1 << 8),
185	SR_F = (1 << 9),
186	SR_CY = (1 << 10),
187	SR_OV = (1 << 11),
188	SR_OVE = (1 << 12),
189	SR_DSX = (1 << 13),
190	SR_EPH = (1 << 14),
191	SR_FO = (1 << 15),
192	SR_SUMRA = (1 << 16),
193	SR_SCE = (1 << 17),
194	};
195
196	/* OpenRISC Hardware Capabilities */
197	enum {
198	OPENRISC_FEATURE_NSGF = (15 << 0),
199	OPENRISC_FEATURE_CGF = (1 << 4),
200	OPENRISC_FEATURE_OB32S = (1 << 5),
201	OPENRISC_FEATURE_OB64S = (1 << 6),
202	OPENRISC_FEATURE_OF32S = (1 << 7),
203	OPENRISC_FEATURE_OF64S = (1 << 8),
204	OPENRISC_FEATURE_OV64S = (1 << 9),
205	};
206
99f575ed JL	207	/* Tick Timer Mode Register */
	208	enum {
	209	TTMR_TP = (0xfffffff),
	210	TTMR_IP = (1 << 28),
	211	TTMR_IE = (1 << 29),
	212	TTMR_M = (3 << 30),
	213	};
	214
	215	/* Timer Mode */
	216	enum {
	217	TIMER_NONE = (0 << 30),
	218	TIMER_INTR = (1 << 30),
	219	TIMER_SHOT = (2 << 30),
	220	TIMER_CONT = (3 << 30),
	221	};
	222
726fe045 JL	223	/* TLB size */
	224	enum {
	225	DTLB_WAYS = 1,
	226	DTLB_SIZE = 64,
	227	DTLB_MASK = (DTLB_SIZE-1),
	228	ITLB_WAYS = 1,
	229	ITLB_SIZE = 64,
	230	ITLB_MASK = (ITLB_SIZE-1),
	231	};
	232
	233	/* TLB prot */
	234	enum {
	235	URE = (1 << 6),
	236	UWE = (1 << 7),
	237	SRE = (1 << 8),
	238	SWE = (1 << 9),
	239
	240	SXE = (1 << 6),
	241	UXE = (1 << 7),
	242	};
	243
	244	/* check if tlb available */
	245	enum {
	246	TLBRET_INVALID = -3,
	247	TLBRET_NOMATCH = -2,
	248	TLBRET_BADADDR = -1,
	249	TLBRET_MATCH = 0
	250	};
	251
	252	typedef struct OpenRISCTLBEntry {
	253	uint32_t mr;
	254	uint32_t tr;
	255	} OpenRISCTLBEntry;
	256
	257	#ifndef CONFIG_USER_ONLY
	258	typedef struct CPUOpenRISCTLBContext {
	259	OpenRISCTLBEntry itlb[ITLB_WAYS][ITLB_SIZE];
	260	OpenRISCTLBEntry dtlb[DTLB_WAYS][DTLB_SIZE];
	261
	262	int (cpu_openrisc_map_address_code)(struct OpenRISCCPU cpu,
a8170e5e	263	hwaddr *physical,
726fe045 JL	264	int *prot,
	265	target_ulong address, int rw);
	266	int (cpu_openrisc_map_address_data)(struct OpenRISCCPU cpu,
a8170e5e	267	hwaddr *physical,
726fe045 JL	268	int *prot,
	269	target_ulong address, int rw);
	270	} CPUOpenRISCTLBContext;
	271	#endif
	272
e67db06e JL	273	typedef struct CPUOpenRISCState {
	274	target_ulong gpr[32]; /* General registers */
	275	target_ulong pc; /* Program counter */
	276	target_ulong npc; /* Next PC */
	277	target_ulong ppc; /* Prev PC */
	278	target_ulong jmp_pc; /* Jump PC */
	279
6f7332ba	280	uint64_t mac; /* Multiply registers MACHI:MACLO */
e67db06e JL	281
	282	target_ulong fpmaddhi; /* Multiply and add float register FPMADDHI */
	283	target_ulong fpmaddlo; /* Multiply and add float register FPMADDLO */
	284
	285	target_ulong epcr; /* Exception PC register */
	286	target_ulong eear; /* Exception EA register */
	287
84775c43	288	target_ulong sr_f; /* the SR_F bit, values 0, 1. */
97458071 RH	289	target_ulong sr_cy; /* the SR_CY bit, values 0, 1. */
	290	target_long sr_ov; /* the SR_OV bit (in the sign bit only) */
	291	uint32_t sr; /* Supervisor register, without SR_{F,CY,OV} */
e67db06e JL	292	uint32_t vr; /* Version register */
	293	uint32_t upr; /* Unit presence register */
	294	uint32_t cpucfgr; /* CPU configure register */
	295	uint32_t dmmucfgr; /* DMMU configure register */
	296	uint32_t immucfgr; /* IMMU configure register */
	297	uint32_t esr; /* Exception supervisor register */
	298	uint32_t fpcsr; /* Float register */
	299	float_status fp_status;
	300
930c3d00 RH	301	target_ulong lock_addr;
	302	target_ulong lock_value;
	303
e67db06e JL	304	uint32_t flags; /* cpu_flags, we only use it for exception
e67db06e JL	305	in solt so far. */
e67db06e	306
1f5c00cf AB	307	/* Fields up to this point are cleared by a CPU reset */
	308	struct {} end_reset_fields;
	309
e67db06e JL	310	CPU_COMMON
e67db06e JL	311
f0c3c505	312	/* Fields from here on are preserved across CPU reset. */
e67db06e	313	#ifndef CONFIG_USER_ONLY
726fe045 JL	314	CPUOpenRISCTLBContext * tlb;
726fe045 JL	315
1246b259	316	QEMUTimer *timer;
e67db06e JL	317	uint32_t ttmr; /* Timer tick mode register */
	318	uint32_t ttcr; /* Timer tick count register */
	319
	320	uint32_t picmr; /* Interrupt mask register */
	321	uint32_t picsr; /* Interrupt contrl register*/
	322	#endif
b6a71ef7	323	void irq[32]; / Interrupt irq input */
e67db06e JL	324	} CPUOpenRISCState;
	325
	326	/**
	327	* OpenRISCCPU:
	328	* @env: #CPUOpenRISCState
	329	*
	330	* A OpenRISC CPU.
	331	*/
	332	typedef struct OpenRISCCPU {
	333	/< private >/
	334	CPUState parent_obj;
	335	/< public >/
	336
	337	CPUOpenRISCState env;
	338
	339	uint32_t feature; /* CPU Capabilities */
	340	} OpenRISCCPU;
	341
	342	static inline OpenRISCCPU openrisc_env_get_cpu(CPUOpenRISCState env)
	343	{
6e42be7c	344	return container_of(env, OpenRISCCPU, env);
e67db06e JL	345	}
	346
	347	#define ENV_GET_CPU(e) CPU(openrisc_env_get_cpu(e))
	348
fadf9825 AF	349	#define ENV_OFFSET offsetof(OpenRISCCPU, env)
fadf9825 AF	350
e67db06e	351	OpenRISCCPU cpu_openrisc_init(const char cpu_model);
e67db06e JL	352
e67db06e JL	353	void cpu_openrisc_list(FILE *f, fprintf_function cpu_fprintf);
97a8ea5a	354	void openrisc_cpu_do_interrupt(CPUState *cpu);
fbb96c4b	355	bool openrisc_cpu_exec_interrupt(CPUState *cpu, int int_req);
878096ee AF	356	void openrisc_cpu_dump_state(CPUState cpu, FILE f,
878096ee AF	357	fprintf_function cpu_fprintf, int flags);
00b941e5	358	hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
5b50e790 AF	359	int openrisc_cpu_gdb_read_register(CPUState cpu, uint8_t buf, int reg);
5b50e790 AF	360	int openrisc_cpu_gdb_write_register(CPUState cpu, uint8_t buf, int reg);
e67db06e	361	void openrisc_translate_init(void);
7510454e	362	int openrisc_cpu_handle_mmu_fault(CPUState *cpu, vaddr address,
726fe045	363	int rw, int mmu_idx);
d962783e	364	int cpu_openrisc_signal_handler(int host_signum, void pinfo, void puc);
e67db06e JL	365
e67db06e JL	366	#define cpu_list cpu_openrisc_list
d962783e	367	#define cpu_signal_handler cpu_openrisc_signal_handler
e67db06e JL	368
e67db06e JL	369	#ifndef CONFIG_USER_ONLY
da697214 AF	370	extern const struct VMStateDescription vmstate_openrisc_cpu;
da697214 AF	371
dd29c7fb JL	372	/* hw/openrisc_pic.c */
	373	void cpu_openrisc_pic_init(OpenRISCCPU *cpu);
	374
99f575ed JL	375	/* hw/openrisc_timer.c */
	376	void cpu_openrisc_clock_init(OpenRISCCPU *cpu);
	377	void cpu_openrisc_count_update(OpenRISCCPU *cpu);
d5155217	378	void cpu_openrisc_timer_update(OpenRISCCPU *cpu);
99f575ed JL	379	void cpu_openrisc_count_start(OpenRISCCPU *cpu);
	380	void cpu_openrisc_count_stop(OpenRISCCPU *cpu);
	381
e67db06e	382	void cpu_openrisc_mmu_init(OpenRISCCPU *cpu);
726fe045	383	int cpu_openrisc_get_phys_nommu(OpenRISCCPU *cpu,
a8170e5e	384	hwaddr *physical,
726fe045 JL	385	int *prot, target_ulong address, int rw);
726fe045 JL	386	int cpu_openrisc_get_phys_code(OpenRISCCPU *cpu,
a8170e5e	387	hwaddr *physical,
726fe045 JL	388	int *prot, target_ulong address, int rw);
726fe045 JL	389	int cpu_openrisc_get_phys_data(OpenRISCCPU *cpu,
a8170e5e	390	hwaddr *physical,
726fe045	391	int *prot, target_ulong address, int rw);
e67db06e JL	392	#endif
e67db06e JL	393
2994fd96	394	#define cpu_init(cpu_model) CPU(cpu_openrisc_init(cpu_model))
e67db06e	395
022c62cb	396	#include "exec/cpu-all.h"
e67db06e JL	397
	398	static inline void cpu_get_tb_cpu_state(CPUOpenRISCState *env,
	399	target_ulong *pc,
89fee74a	400	target_ulong cs_base, uint32_t flags)
e67db06e JL	401	{
	402	*pc = env->pc;
	403	*cs_base = 0;
0c53d734 RH	404	/* D_FLAG -- branch instruction exception, OVE overflow trap enable. */
0c53d734 RH	405	*flags = (env->flags & D_FLAG) \| (env->sr & SR_OVE);
e67db06e JL	406	}
e67db06e JL	407
97ed5ccd	408	static inline int cpu_mmu_index(CPUOpenRISCState *env, bool ifetch)
e67db06e	409	{
726fe045 JL	410	if (!(env->sr & SR_IME)) {
	411	return MMU_NOMMU_IDX;
	412	}
	413	return (env->sr & SR_SM) == 0 ? MMU_USER_IDX : MMU_SUPERVISOR_IDX;
e67db06e JL	414	}
e67db06e JL	415
84775c43 RH	416	static inline uint32_t cpu_get_sr(const CPUOpenRISCState *env)
84775c43 RH	417	{
97458071 RH	418	return (env->sr
	419	+ env->sr_f * SR_F
	420	+ env->sr_cy * SR_CY
	421	+ (env->sr_ov < 0) * SR_OV);
84775c43 RH	422	}
	423
	424	static inline void cpu_set_sr(CPUOpenRISCState *env, uint32_t val)
	425	{
	426	env->sr_f = (val & SR_F) != 0;
97458071 RH	427	env->sr_cy = (val & SR_CY) != 0;
	428	env->sr_ov = (val & SR_OV ? -1 : 0);
	429	env->sr = (val & ~(SR_F \| SR_CY \| SR_OV)) \| SR_FO;
84775c43 RH	430	}
84775c43 RH	431
b6a71ef7	432	#define CPU_INTERRUPT_TIMER CPU_INTERRUPT_TGT_INT_0
e67db06e	433
07f5a258	434	#endif /* OPENRISC_CPU_H */