[qemu.git] / hw / timer / milkymist-sysctl.c

/*
 *  QEMU model of the Milkymist System Controller.
 *
 *  Copyright (c) 2010-2012 Michael Walle <[email protected]>
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 *
 *
 * Specification available at:
 *   http://milkymist.walle.cc/socdoc/sysctl.pdf
 */

#include "qemu/osdep.h"
#include "hw/hw.h"
#include "hw/sysbus.h"
#include "sysemu/sysemu.h"
#include "trace.h"
#include "qemu/timer.h"
#include "hw/ptimer.h"
#include "qemu/error-report.h"

enum {
    CTRL_ENABLE      = (1<<0),
    CTRL_AUTORESTART = (1<<1),
};

enum {
    ICAP_READY       = (1<<0),
};

enum {
    R_GPIO_IN         = 0,
    R_GPIO_OUT,
    R_GPIO_INTEN,
    R_TIMER0_CONTROL  = 4,
    R_TIMER0_COMPARE,
    R_TIMER0_COUNTER,
    R_TIMER1_CONTROL  = 8,
    R_TIMER1_COMPARE,
    R_TIMER1_COUNTER,
    R_ICAP = 16,
    R_DBG_SCRATCHPAD  = 20,
    R_DBG_WRITE_LOCK,
    R_CLK_FREQUENCY   = 29,
    R_CAPABILITIES,
    R_SYSTEM_ID,
    R_MAX
};

#define TYPE_MILKYMIST_SYSCTL "milkymist-sysctl"
#define MILKYMIST_SYSCTL(obj) \
    OBJECT_CHECK(MilkymistSysctlState, (obj), TYPE_MILKYMIST_SYSCTL)

struct MilkymistSysctlState {
    SysBusDevice parent_obj;

    MemoryRegion regs_region;

    QEMUBH *bh0;
    QEMUBH *bh1;
    ptimer_state *ptimer0;
    ptimer_state *ptimer1;

    uint32_t freq_hz;
    uint32_t capabilities;
    uint32_t systemid;
    uint32_t strappings;

    uint32_t regs[R_MAX];

    qemu_irq gpio_irq;
    qemu_irq timer0_irq;
    qemu_irq timer1_irq;
};
typedef struct MilkymistSysctlState MilkymistSysctlState;

static void sysctl_icap_write(MilkymistSysctlState *s, uint32_t value)
{
    trace_milkymist_sysctl_icap_write(value);
    switch (value & 0xffff) {
    case 0x000e:
        qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
        break;
    }
}

static uint64_t sysctl_read(void *opaque, hwaddr addr,
                            unsigned size)
{
    MilkymistSysctlState *s = opaque;
    uint32_t r = 0;

    addr >>= 2;
    switch (addr) {
    case R_TIMER0_COUNTER:
        r = (uint32_t)ptimer_get_count(s->ptimer0);
        /* milkymist timer counts up */
        r = s->regs[R_TIMER0_COMPARE] - r;
        break;
    case R_TIMER1_COUNTER:
        r = (uint32_t)ptimer_get_count(s->ptimer1);
        /* milkymist timer counts up */
        r = s->regs[R_TIMER1_COMPARE] - r;
        break;
    case R_GPIO_IN:
    case R_GPIO_OUT:
    case R_GPIO_INTEN:
    case R_TIMER0_CONTROL:
    case R_TIMER0_COMPARE:
    case R_TIMER1_CONTROL:
    case R_TIMER1_COMPARE:
    case R_ICAP:
    case R_DBG_SCRATCHPAD:
    case R_DBG_WRITE_LOCK:
    case R_CLK_FREQUENCY:
    case R_CAPABILITIES:
    case R_SYSTEM_ID:
        r = s->regs[addr];
        break;

    default:
        error_report("milkymist_sysctl: read access to unknown register 0x"
                TARGET_FMT_plx, addr << 2);
        break;
    }

    trace_milkymist_sysctl_memory_read(addr << 2, r);

    return r;
}

static void sysctl_write(void *opaque, hwaddr addr, uint64_t value,
                         unsigned size)
{
    MilkymistSysctlState *s = opaque;

    trace_milkymist_sysctl_memory_write(addr, value);

    addr >>= 2;
    switch (addr) {
    case R_GPIO_OUT:
    case R_GPIO_INTEN:
    case R_TIMER0_COUNTER:
    case R_TIMER1_COUNTER:
    case R_DBG_SCRATCHPAD:
        s->regs[addr] = value;
        break;
    case R_TIMER0_COMPARE:
        ptimer_set_limit(s->ptimer0, value, 0);
        s->regs[addr] = value;
        break;
    case R_TIMER1_COMPARE:
        ptimer_set_limit(s->ptimer1, value, 0);
        s->regs[addr] = value;
        break;
    case R_TIMER0_CONTROL:
        s->regs[addr] = value;
        if (s->regs[R_TIMER0_CONTROL] & CTRL_ENABLE) {
            trace_milkymist_sysctl_start_timer0();
            ptimer_set_count(s->ptimer0,
                    s->regs[R_TIMER0_COMPARE] - s->regs[R_TIMER0_COUNTER]);
            ptimer_run(s->ptimer0, 0);
        } else {
            trace_milkymist_sysctl_stop_timer0();
            ptimer_stop(s->ptimer0);
        }
        break;
    case R_TIMER1_CONTROL:
        s->regs[addr] = value;
        if (s->regs[R_TIMER1_CONTROL] & CTRL_ENABLE) {
            trace_milkymist_sysctl_start_timer1();
            ptimer_set_count(s->ptimer1,
                    s->regs[R_TIMER1_COMPARE] - s->regs[R_TIMER1_COUNTER]);
            ptimer_run(s->ptimer1, 0);
        } else {
            trace_milkymist_sysctl_stop_timer1();
            ptimer_stop(s->ptimer1);
        }
        break;
    case R_ICAP:
        sysctl_icap_write(s, value);
        break;
    case R_DBG_WRITE_LOCK:
        s->regs[addr] = 1;
        break;
    case R_SYSTEM_ID:
        qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
        break;

    case R_GPIO_IN:
    case R_CLK_FREQUENCY:
    case R_CAPABILITIES:
        error_report("milkymist_sysctl: write to read-only register 0x"
                TARGET_FMT_plx, addr << 2);
        break;

    default:
        error_report("milkymist_sysctl: write access to unknown register 0x"
                TARGET_FMT_plx, addr << 2);
        break;
    }
}

static const MemoryRegionOps sysctl_mmio_ops = {
    .read = sysctl_read,
    .write = sysctl_write,
    .valid = {
        .min_access_size = 4,
        .max_access_size = 4,
    },
    .endianness = DEVICE_NATIVE_ENDIAN,
};

static void timer0_hit(void *opaque)
{
    MilkymistSysctlState *s = opaque;

    if (!(s->regs[R_TIMER0_CONTROL] & CTRL_AUTORESTART)) {
        s->regs[R_TIMER0_CONTROL] &= ~CTRL_ENABLE;
        trace_milkymist_sysctl_stop_timer0();
        ptimer_stop(s->ptimer0);
    }

    trace_milkymist_sysctl_pulse_irq_timer0();
    qemu_irq_pulse(s->timer0_irq);
}

static void timer1_hit(void *opaque)
{
    MilkymistSysctlState *s = opaque;

    if (!(s->regs[R_TIMER1_CONTROL] & CTRL_AUTORESTART)) {
        s->regs[R_TIMER1_CONTROL] &= ~CTRL_ENABLE;
        trace_milkymist_sysctl_stop_timer1();
        ptimer_stop(s->ptimer1);
    }

    trace_milkymist_sysctl_pulse_irq_timer1();
    qemu_irq_pulse(s->timer1_irq);
}

static void milkymist_sysctl_reset(DeviceState *d)
{
    MilkymistSysctlState *s = MILKYMIST_SYSCTL(d);
    int i;

    for (i = 0; i < R_MAX; i++) {
        s->regs[i] = 0;
    }

    ptimer_stop(s->ptimer0);
    ptimer_stop(s->ptimer1);

    /* defaults */
    s->regs[R_ICAP] = ICAP_READY;
    s->regs[R_SYSTEM_ID] = s->systemid;
    s->regs[R_CLK_FREQUENCY] = s->freq_hz;
    s->regs[R_CAPABILITIES] = s->capabilities;
    s->regs[R_GPIO_IN] = s->strappings;
}

static void milkymist_sysctl_init(Object *obj)
{
    MilkymistSysctlState *s = MILKYMIST_SYSCTL(obj);
    SysBusDevice *dev = SYS_BUS_DEVICE(obj);

    sysbus_init_irq(dev, &s->gpio_irq);
    sysbus_init_irq(dev, &s->timer0_irq);
    sysbus_init_irq(dev, &s->timer1_irq);

    s->bh0 = qemu_bh_new(timer0_hit, s);
    s->bh1 = qemu_bh_new(timer1_hit, s);
    s->ptimer0 = ptimer_init(s->bh0, PTIMER_POLICY_DEFAULT);
    s->ptimer1 = ptimer_init(s->bh1, PTIMER_POLICY_DEFAULT);

    memory_region_init_io(&s->regs_region, obj, &sysctl_mmio_ops, s,
            "milkymist-sysctl", R_MAX * 4);
    sysbus_init_mmio(dev, &s->regs_region);
}

static void milkymist_sysctl_realize(DeviceState *dev, Error **errp)
{
    MilkymistSysctlState *s = MILKYMIST_SYSCTL(dev);

    ptimer_set_freq(s->ptimer0, s->freq_hz);
    ptimer_set_freq(s->ptimer1, s->freq_hz);
}

static const VMStateDescription vmstate_milkymist_sysctl = {
    .name = "milkymist-sysctl",
    .version_id = 1,
    .minimum_version_id = 1,
    .fields = (VMStateField[]) {
        VMSTATE_UINT32_ARRAY(regs, MilkymistSysctlState, R_MAX),
        VMSTATE_PTIMER(ptimer0, MilkymistSysctlState),
        VMSTATE_PTIMER(ptimer1, MilkymistSysctlState),
        VMSTATE_END_OF_LIST()
    }
};

static Property milkymist_sysctl_properties[] = {
    DEFINE_PROP_UINT32("frequency", MilkymistSysctlState,
    freq_hz, 80000000),
    DEFINE_PROP_UINT32("capabilities", MilkymistSysctlState,
    capabilities, 0x00000000),
    DEFINE_PROP_UINT32("systemid", MilkymistSysctlState,
    systemid, 0x10014d31),
    DEFINE_PROP_UINT32("gpio_strappings", MilkymistSysctlState,
    strappings, 0x00000001),
    DEFINE_PROP_END_OF_LIST(),
};

static void milkymist_sysctl_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);

    dc->realize = milkymist_sysctl_realize;
    dc->reset = milkymist_sysctl_reset;
    dc->vmsd = &vmstate_milkymist_sysctl;
    dc->props = milkymist_sysctl_properties;
}

static const TypeInfo milkymist_sysctl_info = {
    .name          = TYPE_MILKYMIST_SYSCTL,
    .parent        = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(MilkymistSysctlState),
    .instance_init = milkymist_sysctl_init,
    .class_init    = milkymist_sysctl_class_init,
};

static void milkymist_sysctl_register_types(void)
{
    type_register_static(&milkymist_sysctl_info);
}

type_init(milkymist_sysctl_register_types)
Commit	Line	Data
96832424 MW	1	/*
	2	* QEMU model of the Milkymist System Controller.
	3	*
060544d3	4	* Copyright (c) 2010-2012 Michael Walle <[email protected]>
96832424 MW	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
	9	* version 2 of the License, or (at your option) any later version.
	10	*
	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
	17	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
	18	*
	19	*
	20	* Specification available at:
6dbbe243	21	* http://milkymist.walle.cc/socdoc/sysctl.pdf
96832424 MW	22	*/
96832424 MW	23
ea99dde1	24	#include "qemu/osdep.h"
83c9f4ca PB	25	#include "hw/hw.h"
83c9f4ca PB	26	#include "hw/sysbus.h"
9c17d615	27	#include "sysemu/sysemu.h"
96832424	28	#include "trace.h"
1de7afc9	29	#include "qemu/timer.h"
83c9f4ca	30	#include "hw/ptimer.h"
1de7afc9	31	#include "qemu/error-report.h"
96832424 MW	32
	33	enum {
	34	CTRL_ENABLE = (1<<0),
	35	CTRL_AUTORESTART = (1<<1),
	36	};
	37
	38	enum {
	39	ICAP_READY = (1<<0),
	40	};
	41
	42	enum {
060544d3	43	R_GPIO_IN = 0,
96832424 MW	44	R_GPIO_OUT,
96832424 MW	45	R_GPIO_INTEN,
060544d3	46	R_TIMER0_CONTROL = 4,
96832424 MW	47	R_TIMER0_COMPARE,
96832424 MW	48	R_TIMER0_COUNTER,
060544d3	49	R_TIMER1_CONTROL = 8,
96832424 MW	50	R_TIMER1_COMPARE,
96832424 MW	51	R_TIMER1_COUNTER,
060544d3 MW	52	R_ICAP = 16,
	53	R_DBG_SCRATCHPAD = 20,
	54	R_DBG_WRITE_LOCK,
	55	R_CLK_FREQUENCY = 29,
96832424 MW	56	R_CAPABILITIES,
	57	R_SYSTEM_ID,
	58	R_MAX
	59	};
	60
b564b137 AF	61	#define TYPE_MILKYMIST_SYSCTL "milkymist-sysctl"
	62	#define MILKYMIST_SYSCTL(obj) \
	63	OBJECT_CHECK(MilkymistSysctlState, (obj), TYPE_MILKYMIST_SYSCTL)
	64
96832424	65	struct MilkymistSysctlState {
b564b137 AF	66	SysBusDevice parent_obj;
b564b137 AF	67
dfa87ccf	68	MemoryRegion regs_region;
96832424 MW	69
	70	QEMUBH *bh0;
	71	QEMUBH *bh1;
	72	ptimer_state *ptimer0;
	73	ptimer_state *ptimer1;
	74
	75	uint32_t freq_hz;
	76	uint32_t capabilities;
	77	uint32_t systemid;
	78	uint32_t strappings;
	79
	80	uint32_t regs[R_MAX];
	81
	82	qemu_irq gpio_irq;
	83	qemu_irq timer0_irq;
	84	qemu_irq timer1_irq;
	85	};
	86	typedef struct MilkymistSysctlState MilkymistSysctlState;
	87
	88	static void sysctl_icap_write(MilkymistSysctlState *s, uint32_t value)
	89	{
	90	trace_milkymist_sysctl_icap_write(value);
	91	switch (value & 0xffff) {
	92	case 0x000e:
cf83f140	93	qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
96832424 MW	94	break;
	95	}
	96	}
	97
a8170e5e	98	static uint64_t sysctl_read(void *opaque, hwaddr addr,
dfa87ccf	99	unsigned size)
96832424 MW	100	{
	101	MilkymistSysctlState *s = opaque;
	102	uint32_t r = 0;
	103
	104	addr >>= 2;
	105	switch (addr) {
	106	case R_TIMER0_COUNTER:
	107	r = (uint32_t)ptimer_get_count(s->ptimer0);
	108	/* milkymist timer counts up */
	109	r = s->regs[R_TIMER0_COMPARE] - r;
	110	break;
	111	case R_TIMER1_COUNTER:
	112	r = (uint32_t)ptimer_get_count(s->ptimer1);
	113	/* milkymist timer counts up */
	114	r = s->regs[R_TIMER1_COMPARE] - r;
	115	break;
	116	case R_GPIO_IN:
	117	case R_GPIO_OUT:
	118	case R_GPIO_INTEN:
	119	case R_TIMER0_CONTROL:
	120	case R_TIMER0_COMPARE:
	121	case R_TIMER1_CONTROL:
	122	case R_TIMER1_COMPARE:
	123	case R_ICAP:
060544d3 MW	124	case R_DBG_SCRATCHPAD:
	125	case R_DBG_WRITE_LOCK:
	126	case R_CLK_FREQUENCY:
96832424 MW	127	case R_CAPABILITIES:
	128	case R_SYSTEM_ID:
	129	r = s->regs[addr];
	130	break;
	131
	132	default:
dd3d6775	133	error_report("milkymist_sysctl: read access to unknown register 0x"
96832424 MW	134	TARGET_FMT_plx, addr << 2);
	135	break;
	136	}
	137
	138	trace_milkymist_sysctl_memory_read(addr << 2, r);
	139
	140	return r;
	141	}
	142
a8170e5e	143	static void sysctl_write(void *opaque, hwaddr addr, uint64_t value,
dfa87ccf	144	unsigned size)
96832424 MW	145	{
	146	MilkymistSysctlState *s = opaque;
	147
	148	trace_milkymist_sysctl_memory_write(addr, value);
	149
	150	addr >>= 2;
	151	switch (addr) {
	152	case R_GPIO_OUT:
	153	case R_GPIO_INTEN:
	154	case R_TIMER0_COUNTER:
96832424	155	case R_TIMER1_COUNTER:
060544d3	156	case R_DBG_SCRATCHPAD:
f3172a0e	157	s->regs[addr] = value;
96832424 MW	158	break;
	159	case R_TIMER0_COMPARE:
	160	ptimer_set_limit(s->ptimer0, value, 0);
	161	s->regs[addr] = value;
	162	break;
	163	case R_TIMER1_COMPARE:
	164	ptimer_set_limit(s->ptimer1, value, 0);
	165	s->regs[addr] = value;
	166	break;
	167	case R_TIMER0_CONTROL:
	168	s->regs[addr] = value;
	169	if (s->regs[R_TIMER0_CONTROL] & CTRL_ENABLE) {
f3172a0e MW	170	trace_milkymist_sysctl_start_timer0();
	171	ptimer_set_count(s->ptimer0,
	172	s->regs[R_TIMER0_COMPARE] - s->regs[R_TIMER0_COUNTER]);
96832424 MW	173	ptimer_run(s->ptimer0, 0);
96832424 MW	174	} else {
f3172a0e	175	trace_milkymist_sysctl_stop_timer0();
96832424 MW	176	ptimer_stop(s->ptimer0);
	177	}
	178	break;
	179	case R_TIMER1_CONTROL:
	180	s->regs[addr] = value;
	181	if (s->regs[R_TIMER1_CONTROL] & CTRL_ENABLE) {
	182	trace_milkymist_sysctl_start_timer1();
f3172a0e MW	183	ptimer_set_count(s->ptimer1,
f3172a0e MW	184	s->regs[R_TIMER1_COMPARE] - s->regs[R_TIMER1_COUNTER]);
96832424 MW	185	ptimer_run(s->ptimer1, 0);
	186	} else {
	187	trace_milkymist_sysctl_stop_timer1();
	188	ptimer_stop(s->ptimer1);
	189	}
	190	break;
	191	case R_ICAP:
	192	sysctl_icap_write(s, value);
	193	break;
060544d3 MW	194	case R_DBG_WRITE_LOCK:
	195	s->regs[addr] = 1;
	196	break;
96832424	197	case R_SYSTEM_ID:
cf83f140	198	qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
96832424 MW	199	break;
	200
	201	case R_GPIO_IN:
060544d3	202	case R_CLK_FREQUENCY:
96832424 MW	203	case R_CAPABILITIES:
	204	error_report("milkymist_sysctl: write to read-only register 0x"
	205	TARGET_FMT_plx, addr << 2);
	206	break;
	207
	208	default:
dd3d6775	209	error_report("milkymist_sysctl: write access to unknown register 0x"
96832424 MW	210	TARGET_FMT_plx, addr << 2);
	211	break;
	212	}
	213	}
	214
dfa87ccf MW	215	static const MemoryRegionOps sysctl_mmio_ops = {
	216	.read = sysctl_read,
	217	.write = sysctl_write,
	218	.valid = {
	219	.min_access_size = 4,
	220	.max_access_size = 4,
	221	},
	222	.endianness = DEVICE_NATIVE_ENDIAN,
96832424 MW	223	};
	224
	225	static void timer0_hit(void *opaque)
	226	{
	227	MilkymistSysctlState *s = opaque;
	228
	229	if (!(s->regs[R_TIMER0_CONTROL] & CTRL_AUTORESTART)) {
	230	s->regs[R_TIMER0_CONTROL] &= ~CTRL_ENABLE;
	231	trace_milkymist_sysctl_stop_timer0();
	232	ptimer_stop(s->ptimer0);
	233	}
	234
	235	trace_milkymist_sysctl_pulse_irq_timer0();
	236	qemu_irq_pulse(s->timer0_irq);
	237	}
	238
	239	static void timer1_hit(void *opaque)
	240	{
	241	MilkymistSysctlState *s = opaque;
	242
	243	if (!(s->regs[R_TIMER1_CONTROL] & CTRL_AUTORESTART)) {
	244	s->regs[R_TIMER1_CONTROL] &= ~CTRL_ENABLE;
	245	trace_milkymist_sysctl_stop_timer1();
	246	ptimer_stop(s->ptimer1);
	247	}
	248
	249	trace_milkymist_sysctl_pulse_irq_timer1();
	250	qemu_irq_pulse(s->timer1_irq);
	251	}
	252
	253	static void milkymist_sysctl_reset(DeviceState *d)
	254	{
b564b137	255	MilkymistSysctlState *s = MILKYMIST_SYSCTL(d);
96832424 MW	256	int i;
	257
	258	for (i = 0; i < R_MAX; i++) {
	259	s->regs[i] = 0;
	260	}
	261
	262	ptimer_stop(s->ptimer0);
	263	ptimer_stop(s->ptimer1);
	264
	265	/* defaults */
	266	s->regs[R_ICAP] = ICAP_READY;
	267	s->regs[R_SYSTEM_ID] = s->systemid;
060544d3	268	s->regs[R_CLK_FREQUENCY] = s->freq_hz;
96832424 MW	269	s->regs[R_CAPABILITIES] = s->capabilities;
	270	s->regs[R_GPIO_IN] = s->strappings;
	271	}
	272
596ca933	273	static void milkymist_sysctl_init(Object *obj)
96832424	274	{
596ca933 XZ	275	MilkymistSysctlState *s = MILKYMIST_SYSCTL(obj);
596ca933 XZ	276	SysBusDevice *dev = SYS_BUS_DEVICE(obj);
96832424 MW	277
	278	sysbus_init_irq(dev, &s->gpio_irq);
	279	sysbus_init_irq(dev, &s->timer0_irq);
	280	sysbus_init_irq(dev, &s->timer1_irq);
	281
	282	s->bh0 = qemu_bh_new(timer0_hit, s);
	283	s->bh1 = qemu_bh_new(timer1_hit, s);
e7ea81c3 DO	284	s->ptimer0 = ptimer_init(s->bh0, PTIMER_POLICY_DEFAULT);
e7ea81c3 DO	285	s->ptimer1 = ptimer_init(s->bh1, PTIMER_POLICY_DEFAULT);
96832424	286
596ca933	287	memory_region_init_io(&s->regs_region, obj, &sysctl_mmio_ops, s,
dfa87ccf	288	"milkymist-sysctl", R_MAX * 4);
750ecd44	289	sysbus_init_mmio(dev, &s->regs_region);
596ca933	290	}
96832424	291
596ca933 XZ	292	static void milkymist_sysctl_realize(DeviceState dev, Error *errp)
	293	{
	294	MilkymistSysctlState *s = MILKYMIST_SYSCTL(dev);
	295
	296	ptimer_set_freq(s->ptimer0, s->freq_hz);
	297	ptimer_set_freq(s->ptimer1, s->freq_hz);
96832424 MW	298	}
	299
	300	static const VMStateDescription vmstate_milkymist_sysctl = {
	301	.name = "milkymist-sysctl",
	302	.version_id = 1,
	303	.minimum_version_id = 1,
35d08458	304	.fields = (VMStateField[]) {
96832424 MW	305	VMSTATE_UINT32_ARRAY(regs, MilkymistSysctlState, R_MAX),
	306	VMSTATE_PTIMER(ptimer0, MilkymistSysctlState),
	307	VMSTATE_PTIMER(ptimer1, MilkymistSysctlState),
	308	VMSTATE_END_OF_LIST()
	309	}
	310	};
	311
999e12bb AL	312	static Property milkymist_sysctl_properties[] = {
	313	DEFINE_PROP_UINT32("frequency", MilkymistSysctlState,
	314	freq_hz, 80000000),
	315	DEFINE_PROP_UINT32("capabilities", MilkymistSysctlState,
	316	capabilities, 0x00000000),
	317	DEFINE_PROP_UINT32("systemid", MilkymistSysctlState,
	318	systemid, 0x10014d31),
	319	DEFINE_PROP_UINT32("gpio_strappings", MilkymistSysctlState,
	320	strappings, 0x00000001),
	321	DEFINE_PROP_END_OF_LIST(),
	322	};
	323
	324	static void milkymist_sysctl_class_init(ObjectClass klass, void data)
	325	{
39bffca2	326	DeviceClass *dc = DEVICE_CLASS(klass);
999e12bb	327
596ca933	328	dc->realize = milkymist_sysctl_realize;
39bffca2 AL	329	dc->reset = milkymist_sysctl_reset;
	330	dc->vmsd = &vmstate_milkymist_sysctl;
	331	dc->props = milkymist_sysctl_properties;
999e12bb AL	332	}
999e12bb AL	333
8c43a6f0	334	static const TypeInfo milkymist_sysctl_info = {
b564b137	335	.name = TYPE_MILKYMIST_SYSCTL,
39bffca2 AL	336	.parent = TYPE_SYS_BUS_DEVICE,
39bffca2 AL	337	.instance_size = sizeof(MilkymistSysctlState),
596ca933	338	.instance_init = milkymist_sysctl_init,
39bffca2	339	.class_init = milkymist_sysctl_class_init,
96832424 MW	340	};
96832424 MW	341
83f7d43a	342	static void milkymist_sysctl_register_types(void)
96832424	343	{
39bffca2	344	type_register_static(&milkymist_sysctl_info);
96832424 MW	345	}
96832424 MW	346
83f7d43a	347	type_init(milkymist_sysctl_register_types)