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target/arm: Create gen_gvec_{u,s}{rshr,rsra}
[qemu.git] / target / arm / vec_helper.c
CommitLineData
d9061ec3
RH		 1/*
2 * ARM AdvSIMD / SVE Vector Operations
3 *
4 * Copyright (c) 2018 Linaro
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20#include "qemu/osdep.h"
21#include "cpu.h"
d9061ec3
RH		 22#include "exec/helper-proto.h"
23#include "tcg/tcg-gvec-desc.h"
1695cd61 24#include "fpu/softfloat.h"
d9061ec3
RH		 25
26
1695cd61
RH		 27/* Note that vector data is stored in host-endian 64-bit chunks,
28 so addressing units smaller than that needs a host-endian fixup. */
29#ifdef HOST_WORDS_BIGENDIAN
30#define H1(x) ((x) ^ 7)
31#define H2(x) ((x) ^ 3)
32#define H4(x) ((x) ^ 1)
33#else
34#define H1(x) (x)
35#define H2(x) (x)
36#define H4(x) (x)
37#endif
38
a4d58462 39#define SET_QC() env->vfp.qc[0] = 1
d9061ec3 40
e7186d82
RH		 41static void clear_tail(void *vd, uintptr_t opr_sz, uintptr_t max_sz)
42{
43 uint64_t *d = vd + opr_sz;
44 uintptr_t i;
45
46 for (i = opr_sz; i < max_sz; i += 8) {
47 *d++ = 0;
48 }
49}
50
d9061ec3
RH		 51/* Signed saturating rounding doubling multiply-accumulate high half, 16-bit */
52static uint16_t inl_qrdmlah_s16(CPUARMState *env, int16_t src1,
53 int16_t src2, int16_t src3)
54{
55 /* Simplify:
56 * = ((a3 << 16) + ((e1 * e2) << 1) + (1 << 15)) >> 16
57 * = ((a3 << 15) + (e1 * e2) + (1 << 14)) >> 15
58 */
59 int32_t ret = (int32_t)src1 * src2;
60 ret = ((int32_t)src3 << 15) + ret + (1 << 14);
61 ret >>= 15;
62 if (ret != (int16_t)ret) {
63 SET_QC();
64 ret = (ret < 0 ? -0x8000 : 0x7fff);
65 }
66 return ret;
67}
68
69uint32_t HELPER(neon_qrdmlah_s16)(CPUARMState *env, uint32_t src1,
70 uint32_t src2, uint32_t src3)
71{
72 uint16_t e1 = inl_qrdmlah_s16(env, src1, src2, src3);
73 uint16_t e2 = inl_qrdmlah_s16(env, src1 >> 16, src2 >> 16, src3 >> 16);
74 return deposit32(e1, 16, 16, e2);
75}
76
e7186d82
RH		 77void HELPER(gvec_qrdmlah_s16)(void *vd, void *vn, void *vm,
78 void *ve, uint32_t desc)
79{
80 uintptr_t opr_sz = simd_oprsz(desc);
81 int16_t *d = vd;
82 int16_t *n = vn;
83 int16_t *m = vm;
84 CPUARMState *env = ve;
85 uintptr_t i;
86
87 for (i = 0; i < opr_sz / 2; ++i) {
88 d[i] = inl_qrdmlah_s16(env, n[i], m[i], d[i]);
89 }
90 clear_tail(d, opr_sz, simd_maxsz(desc));
91}
92
d9061ec3
RH		 93/* Signed saturating rounding doubling multiply-subtract high half, 16-bit */
94static uint16_t inl_qrdmlsh_s16(CPUARMState *env, int16_t src1,
95 int16_t src2, int16_t src3)
96{
97 /* Similarly, using subtraction:
98 * = ((a3 << 16) - ((e1 * e2) << 1) + (1 << 15)) >> 16
99 * = ((a3 << 15) - (e1 * e2) + (1 << 14)) >> 15
100 */
101 int32_t ret = (int32_t)src1 * src2;
102 ret = ((int32_t)src3 << 15) - ret + (1 << 14);
103 ret >>= 15;
104 if (ret != (int16_t)ret) {
105 SET_QC();
106 ret = (ret < 0 ? -0x8000 : 0x7fff);
107 }
108 return ret;
109}
110
111uint32_t HELPER(neon_qrdmlsh_s16)(CPUARMState *env, uint32_t src1,
112 uint32_t src2, uint32_t src3)
113{
114 uint16_t e1 = inl_qrdmlsh_s16(env, src1, src2, src3);
115 uint16_t e2 = inl_qrdmlsh_s16(env, src1 >> 16, src2 >> 16, src3 >> 16);
116 return deposit32(e1, 16, 16, e2);
117}
118
e7186d82
RH		 119void HELPER(gvec_qrdmlsh_s16)(void *vd, void *vn, void *vm,
120 void *ve, uint32_t desc)
121{
122 uintptr_t opr_sz = simd_oprsz(desc);
123 int16_t *d = vd;
124 int16_t *n = vn;
125 int16_t *m = vm;
126 CPUARMState *env = ve;
127 uintptr_t i;
128
129 for (i = 0; i < opr_sz / 2; ++i) {
130 d[i] = inl_qrdmlsh_s16(env, n[i], m[i], d[i]);
131 }
132 clear_tail(d, opr_sz, simd_maxsz(desc));
133}
134
d9061ec3
RH		 135/* Signed saturating rounding doubling multiply-accumulate high half, 32-bit */
136uint32_t HELPER(neon_qrdmlah_s32)(CPUARMState *env, int32_t src1,
137 int32_t src2, int32_t src3)
138{
139 /* Simplify similarly to int_qrdmlah_s16 above. */
140 int64_t ret = (int64_t)src1 * src2;
141 ret = ((int64_t)src3 << 31) + ret + (1 << 30);
142 ret >>= 31;
143 if (ret != (int32_t)ret) {
144 SET_QC();
145 ret = (ret < 0 ? INT32_MIN : INT32_MAX);
146 }
147 return ret;
148}
149
e7186d82
RH		 150void HELPER(gvec_qrdmlah_s32)(void *vd, void *vn, void *vm,
151 void *ve, uint32_t desc)
152{
153 uintptr_t opr_sz = simd_oprsz(desc);
154 int32_t *d = vd;
155 int32_t *n = vn;
156 int32_t *m = vm;
157 CPUARMState *env = ve;
158 uintptr_t i;
159
160 for (i = 0; i < opr_sz / 4; ++i) {
161 d[i] = helper_neon_qrdmlah_s32(env, n[i], m[i], d[i]);
162 }
163 clear_tail(d, opr_sz, simd_maxsz(desc));
164}
165
d9061ec3
RH		 166/* Signed saturating rounding doubling multiply-subtract high half, 32-bit */
167uint32_t HELPER(neon_qrdmlsh_s32)(CPUARMState *env, int32_t src1,
168 int32_t src2, int32_t src3)
169{
170 /* Simplify similarly to int_qrdmlsh_s16 above. */
171 int64_t ret = (int64_t)src1 * src2;
172 ret = ((int64_t)src3 << 31) - ret + (1 << 30);
173 ret >>= 31;
174 if (ret != (int32_t)ret) {
175 SET_QC();
176 ret = (ret < 0 ? INT32_MIN : INT32_MAX);
177 }
178 return ret;
179}
e7186d82
RH		 180
181void HELPER(gvec_qrdmlsh_s32)(void *vd, void *vn, void *vm,
182 void *ve, uint32_t desc)
183{
184 uintptr_t opr_sz = simd_oprsz(desc);
185 int32_t *d = vd;
186 int32_t *n = vn;
187 int32_t *m = vm;
188 CPUARMState *env = ve;
189 uintptr_t i;
190
191 for (i = 0; i < opr_sz / 4; ++i) {
192 d[i] = helper_neon_qrdmlsh_s32(env, n[i], m[i], d[i]);
193 }
194 clear_tail(d, opr_sz, simd_maxsz(desc));
195}
1695cd61 196
d730ecaa
RH		 197/* Integer 8 and 16-bit dot-product.
198 *
199 * Note that for the loops herein, host endianness does not matter
200 * with respect to the ordering of data within the 64-bit lanes.
201 * All elements are treated equally, no matter where they are.
202 */
203
204void HELPER(gvec_sdot_b)(void *vd, void *vn, void *vm, uint32_t desc)
205{
206 intptr_t i, opr_sz = simd_oprsz(desc);
207 uint32_t *d = vd;
208 int8_t *n = vn, *m = vm;
209
210 for (i = 0; i < opr_sz / 4; ++i) {
211 d[i] += n[i * 4 + 0] * m[i * 4 + 0]
212 + n[i * 4 + 1] * m[i * 4 + 1]
213 + n[i * 4 + 2] * m[i * 4 + 2]
214 + n[i * 4 + 3] * m[i * 4 + 3];
215 }
216 clear_tail(d, opr_sz, simd_maxsz(desc));
217}
218
219void HELPER(gvec_udot_b)(void *vd, void *vn, void *vm, uint32_t desc)
220{
221 intptr_t i, opr_sz = simd_oprsz(desc);
222 uint32_t *d = vd;
223 uint8_t *n = vn, *m = vm;
224
225 for (i = 0; i < opr_sz / 4; ++i) {
226 d[i] += n[i * 4 + 0] * m[i * 4 + 0]
227 + n[i * 4 + 1] * m[i * 4 + 1]
228 + n[i * 4 + 2] * m[i * 4 + 2]
229 + n[i * 4 + 3] * m[i * 4 + 3];
230 }
231 clear_tail(d, opr_sz, simd_maxsz(desc));
232}
233
234void HELPER(gvec_sdot_h)(void *vd, void *vn, void *vm, uint32_t desc)
235{
236 intptr_t i, opr_sz = simd_oprsz(desc);
237 uint64_t *d = vd;
238 int16_t *n = vn, *m = vm;
239
240 for (i = 0; i < opr_sz / 8; ++i) {
241 d[i] += (int64_t)n[i * 4 + 0] * m[i * 4 + 0]
242 + (int64_t)n[i * 4 + 1] * m[i * 4 + 1]
243 + (int64_t)n[i * 4 + 2] * m[i * 4 + 2]
244 + (int64_t)n[i * 4 + 3] * m[i * 4 + 3];
245 }
246 clear_tail(d, opr_sz, simd_maxsz(desc));
247}
248
249void HELPER(gvec_udot_h)(void *vd, void *vn, void *vm, uint32_t desc)
250{
251 intptr_t i, opr_sz = simd_oprsz(desc);
252 uint64_t *d = vd;
253 uint16_t *n = vn, *m = vm;
254
255 for (i = 0; i < opr_sz / 8; ++i) {
256 d[i] += (uint64_t)n[i * 4 + 0] * m[i * 4 + 0]
257 + (uint64_t)n[i * 4 + 1] * m[i * 4 + 1]
258 + (uint64_t)n[i * 4 + 2] * m[i * 4 + 2]
259 + (uint64_t)n[i * 4 + 3] * m[i * 4 + 3];
260 }
261 clear_tail(d, opr_sz, simd_maxsz(desc));
262}
263
16fcfdc7
RH		 264void HELPER(gvec_sdot_idx_b)(void *vd, void *vn, void *vm, uint32_t desc)
265{
266 intptr_t i, segend, opr_sz = simd_oprsz(desc), opr_sz_4 = opr_sz / 4;
267 intptr_t index = simd_data(desc);
268 uint32_t *d = vd;
269 int8_t *n = vn;
270 int8_t *m_indexed = (int8_t *)vm + index * 4;
271
272 /* Notice the special case of opr_sz == 8, from aa64/aa32 advsimd.
273 * Otherwise opr_sz is a multiple of 16.
274 */
275 segend = MIN(4, opr_sz_4);
276 i = 0;
277 do {
278 int8_t m0 = m_indexed[i * 4 + 0];
279 int8_t m1 = m_indexed[i * 4 + 1];
280 int8_t m2 = m_indexed[i * 4 + 2];
281 int8_t m3 = m_indexed[i * 4 + 3];
282
283 do {
284 d[i] += n[i * 4 + 0] * m0
285 + n[i * 4 + 1] * m1
286 + n[i * 4 + 2] * m2
287 + n[i * 4 + 3] * m3;
288 } while (++i < segend);
289 segend = i + 4;
290 } while (i < opr_sz_4);
291
292 clear_tail(d, opr_sz, simd_maxsz(desc));
293}
294
295void HELPER(gvec_udot_idx_b)(void *vd, void *vn, void *vm, uint32_t desc)
296{
297 intptr_t i, segend, opr_sz = simd_oprsz(desc), opr_sz_4 = opr_sz / 4;
298 intptr_t index = simd_data(desc);
299 uint32_t *d = vd;
300 uint8_t *n = vn;
301 uint8_t *m_indexed = (uint8_t *)vm + index * 4;
302
303 /* Notice the special case of opr_sz == 8, from aa64/aa32 advsimd.
304 * Otherwise opr_sz is a multiple of 16.
305 */
306 segend = MIN(4, opr_sz_4);
307 i = 0;
308 do {
309 uint8_t m0 = m_indexed[i * 4 + 0];
310 uint8_t m1 = m_indexed[i * 4 + 1];
311 uint8_t m2 = m_indexed[i * 4 + 2];
312 uint8_t m3 = m_indexed[i * 4 + 3];
313
314 do {
315 d[i] += n[i * 4 + 0] * m0
316 + n[i * 4 + 1] * m1
317 + n[i * 4 + 2] * m2
318 + n[i * 4 + 3] * m3;
319 } while (++i < segend);
320 segend = i + 4;
321 } while (i < opr_sz_4);
322
323 clear_tail(d, opr_sz, simd_maxsz(desc));
324}
325
326void HELPER(gvec_sdot_idx_h)(void *vd, void *vn, void *vm, uint32_t desc)
327{
328 intptr_t i, opr_sz = simd_oprsz(desc), opr_sz_8 = opr_sz / 8;
329 intptr_t index = simd_data(desc);
330 uint64_t *d = vd;
331 int16_t *n = vn;
332 int16_t *m_indexed = (int16_t *)vm + index * 4;
333
334 /* This is supported by SVE only, so opr_sz is always a multiple of 16.
335 * Process the entire segment all at once, writing back the results
336 * only after we've consumed all of the inputs.
337 */
338 for (i = 0; i < opr_sz_8 ; i += 2) {
339 uint64_t d0, d1;
340
341 d0 = n[i * 4 + 0] * (int64_t)m_indexed[i * 4 + 0];
342 d0 += n[i * 4 + 1] * (int64_t)m_indexed[i * 4 + 1];
343 d0 += n[i * 4 + 2] * (int64_t)m_indexed[i * 4 + 2];
344 d0 += n[i * 4 + 3] * (int64_t)m_indexed[i * 4 + 3];
345 d1 = n[i * 4 + 4] * (int64_t)m_indexed[i * 4 + 0];
346 d1 += n[i * 4 + 5] * (int64_t)m_indexed[i * 4 + 1];
347 d1 += n[i * 4 + 6] * (int64_t)m_indexed[i * 4 + 2];
348 d1 += n[i * 4 + 7] * (int64_t)m_indexed[i * 4 + 3];
349
350 d[i + 0] += d0;
351 d[i + 1] += d1;
352 }
353
354 clear_tail(d, opr_sz, simd_maxsz(desc));
355}
356
357void HELPER(gvec_udot_idx_h)(void *vd, void *vn, void *vm, uint32_t desc)
358{
359 intptr_t i, opr_sz = simd_oprsz(desc), opr_sz_8 = opr_sz / 8;
360 intptr_t index = simd_data(desc);
361 uint64_t *d = vd;
362 uint16_t *n = vn;
363 uint16_t *m_indexed = (uint16_t *)vm + index * 4;
364
365 /* This is supported by SVE only, so opr_sz is always a multiple of 16.
366 * Process the entire segment all at once, writing back the results
367 * only after we've consumed all of the inputs.
368 */
369 for (i = 0; i < opr_sz_8 ; i += 2) {
370 uint64_t d0, d1;
371
372 d0 = n[i * 4 + 0] * (uint64_t)m_indexed[i * 4 + 0];
373 d0 += n[i * 4 + 1] * (uint64_t)m_indexed[i * 4 + 1];
374 d0 += n[i * 4 + 2] * (uint64_t)m_indexed[i * 4 + 2];
375 d0 += n[i * 4 + 3] * (uint64_t)m_indexed[i * 4 + 3];
376 d1 = n[i * 4 + 4] * (uint64_t)m_indexed[i * 4 + 0];
377 d1 += n[i * 4 + 5] * (uint64_t)m_indexed[i * 4 + 1];
378 d1 += n[i * 4 + 6] * (uint64_t)m_indexed[i * 4 + 2];
379 d1 += n[i * 4 + 7] * (uint64_t)m_indexed[i * 4 + 3];
380
381 d[i + 0] += d0;
382 d[i + 1] += d1;
383 }
384
385 clear_tail(d, opr_sz, simd_maxsz(desc));
386}
387
1695cd61
RH		 388void HELPER(gvec_fcaddh)(void *vd, void *vn, void *vm,
389 void *vfpst, uint32_t desc)
390{
391 uintptr_t opr_sz = simd_oprsz(desc);
392 float16 *d = vd;
393 float16 *n = vn;
394 float16 *m = vm;
395 float_status *fpst = vfpst;
396 uint32_t neg_real = extract32(desc, SIMD_DATA_SHIFT, 1);
397 uint32_t neg_imag = neg_real ^ 1;
398 uintptr_t i;
399
400 /* Shift boolean to the sign bit so we can xor to negate. */
401 neg_real <<= 15;
402 neg_imag <<= 15;
403
404 for (i = 0; i < opr_sz / 2; i += 2) {
405 float16 e0 = n[H2(i)];
406 float16 e1 = m[H2(i + 1)] ^ neg_imag;
407 float16 e2 = n[H2(i + 1)];
408 float16 e3 = m[H2(i)] ^ neg_real;
409
410 d[H2(i)] = float16_add(e0, e1, fpst);
411 d[H2(i + 1)] = float16_add(e2, e3, fpst);
412 }
413 clear_tail(d, opr_sz, simd_maxsz(desc));
414}
415
416void HELPER(gvec_fcadds)(void *vd, void *vn, void *vm,
417 void *vfpst, uint32_t desc)
418{
419 uintptr_t opr_sz = simd_oprsz(desc);
420 float32 *d = vd;
421 float32 *n = vn;
422 float32 *m = vm;
423 float_status *fpst = vfpst;
424 uint32_t neg_real = extract32(desc, SIMD_DATA_SHIFT, 1);
425 uint32_t neg_imag = neg_real ^ 1;
426 uintptr_t i;
427
428 /* Shift boolean to the sign bit so we can xor to negate. */
429 neg_real <<= 31;
430 neg_imag <<= 31;
431
432 for (i = 0; i < opr_sz / 4; i += 2) {
433 float32 e0 = n[H4(i)];
434 float32 e1 = m[H4(i + 1)] ^ neg_imag;
435 float32 e2 = n[H4(i + 1)];
436 float32 e3 = m[H4(i)] ^ neg_real;
437
438 d[H4(i)] = float32_add(e0, e1, fpst);
439 d[H4(i + 1)] = float32_add(e2, e3, fpst);
440 }
441 clear_tail(d, opr_sz, simd_maxsz(desc));
442}
443
444void HELPER(gvec_fcaddd)(void *vd, void *vn, void *vm,
445 void *vfpst, uint32_t desc)
446{
447 uintptr_t opr_sz = simd_oprsz(desc);
448 float64 *d = vd;
449 float64 *n = vn;
450 float64 *m = vm;
451 float_status *fpst = vfpst;
452 uint64_t neg_real = extract64(desc, SIMD_DATA_SHIFT, 1);
453 uint64_t neg_imag = neg_real ^ 1;
454 uintptr_t i;
455
456 /* Shift boolean to the sign bit so we can xor to negate. */
457 neg_real <<= 63;
458 neg_imag <<= 63;
459
460 for (i = 0; i < opr_sz / 8; i += 2) {
461 float64 e0 = n[i];
462 float64 e1 = m[i + 1] ^ neg_imag;
463 float64 e2 = n[i + 1];
464 float64 e3 = m[i] ^ neg_real;
465
466 d[i] = float64_add(e0, e1, fpst);
467 d[i + 1] = float64_add(e2, e3, fpst);
468 }
469 clear_tail(d, opr_sz, simd_maxsz(desc));
470}
d17b7cdc
RH		 471
472void HELPER(gvec_fcmlah)(void *vd, void *vn, void *vm,
473 void *vfpst, uint32_t desc)
474{
475 uintptr_t opr_sz = simd_oprsz(desc);
476 float16 *d = vd;
477 float16 *n = vn;
478 float16 *m = vm;
479 float_status *fpst = vfpst;
480 intptr_t flip = extract32(desc, SIMD_DATA_SHIFT, 1);
481 uint32_t neg_imag = extract32(desc, SIMD_DATA_SHIFT + 1, 1);
482 uint32_t neg_real = flip ^ neg_imag;
483 uintptr_t i;
484
485 /* Shift boolean to the sign bit so we can xor to negate. */
486 neg_real <<= 15;
487 neg_imag <<= 15;
488
489 for (i = 0; i < opr_sz / 2; i += 2) {
490 float16 e2 = n[H2(i + flip)];
491 float16 e1 = m[H2(i + flip)] ^ neg_real;
492 float16 e4 = e2;
493 float16 e3 = m[H2(i + 1 - flip)] ^ neg_imag;
494
495 d[H2(i)] = float16_muladd(e2, e1, d[H2(i)], 0, fpst);
496 d[H2(i + 1)] = float16_muladd(e4, e3, d[H2(i + 1)], 0, fpst);
497 }
498 clear_tail(d, opr_sz, simd_maxsz(desc));
499}
500
501void HELPER(gvec_fcmlah_idx)(void *vd, void *vn, void *vm,
502 void *vfpst, uint32_t desc)
503{
504 uintptr_t opr_sz = simd_oprsz(desc);
505 float16 *d = vd;
506 float16 *n = vn;
507 float16 *m = vm;
508 float_status *fpst = vfpst;
509 intptr_t flip = extract32(desc, SIMD_DATA_SHIFT, 1);
510 uint32_t neg_imag = extract32(desc, SIMD_DATA_SHIFT + 1, 1);
2cc99919 511 intptr_t index = extract32(desc, SIMD_DATA_SHIFT + 2, 2);
d17b7cdc 512 uint32_t neg_real = flip ^ neg_imag;
18fc2405
RH		 513 intptr_t elements = opr_sz / sizeof(float16);
514 intptr_t eltspersegment = 16 / sizeof(float16);
515 intptr_t i, j;
d17b7cdc
RH		 516
517 /* Shift boolean to the sign bit so we can xor to negate. */
518 neg_real <<= 15;
519 neg_imag <<= 15;
d17b7cdc 520
18fc2405
RH		 521 for (i = 0; i < elements; i += eltspersegment) {
522 float16 mr = m[H2(i + 2 * index + 0)];
523 float16 mi = m[H2(i + 2 * index + 1)];
524 float16 e1 = neg_real ^ (flip ? mi : mr);
525 float16 e3 = neg_imag ^ (flip ? mr : mi);
d17b7cdc 526
18fc2405
RH		 527 for (j = i; j < i + eltspersegment; j += 2) {
528 float16 e2 = n[H2(j + flip)];
529 float16 e4 = e2;
530
531 d[H2(j)] = float16_muladd(e2, e1, d[H2(j)], 0, fpst);
532 d[H2(j + 1)] = float16_muladd(e4, e3, d[H2(j + 1)], 0, fpst);
533 }
d17b7cdc
RH		 534 }
535 clear_tail(d, opr_sz, simd_maxsz(desc));
536}
537
538void HELPER(gvec_fcmlas)(void *vd, void *vn, void *vm,
539 void *vfpst, uint32_t desc)
540{
541 uintptr_t opr_sz = simd_oprsz(desc);
542 float32 *d = vd;
543 float32 *n = vn;
544 float32 *m = vm;
545 float_status *fpst = vfpst;
546 intptr_t flip = extract32(desc, SIMD_DATA_SHIFT, 1);
547 uint32_t neg_imag = extract32(desc, SIMD_DATA_SHIFT + 1, 1);
548 uint32_t neg_real = flip ^ neg_imag;
549 uintptr_t i;
550
551 /* Shift boolean to the sign bit so we can xor to negate. */
552 neg_real <<= 31;
553 neg_imag <<= 31;
554
555 for (i = 0; i < opr_sz / 4; i += 2) {
556 float32 e2 = n[H4(i + flip)];
557 float32 e1 = m[H4(i + flip)] ^ neg_real;
558 float32 e4 = e2;
559 float32 e3 = m[H4(i + 1 - flip)] ^ neg_imag;
560
561 d[H4(i)] = float32_muladd(e2, e1, d[H4(i)], 0, fpst);
562 d[H4(i + 1)] = float32_muladd(e4, e3, d[H4(i + 1)], 0, fpst);
563 }
564 clear_tail(d, opr_sz, simd_maxsz(desc));
565}
566
567void HELPER(gvec_fcmlas_idx)(void *vd, void *vn, void *vm,
568 void *vfpst, uint32_t desc)
569{
570 uintptr_t opr_sz = simd_oprsz(desc);
571 float32 *d = vd;
572 float32 *n = vn;
573 float32 *m = vm;
574 float_status *fpst = vfpst;
575 intptr_t flip = extract32(desc, SIMD_DATA_SHIFT, 1);
576 uint32_t neg_imag = extract32(desc, SIMD_DATA_SHIFT + 1, 1);
2cc99919 577 intptr_t index = extract32(desc, SIMD_DATA_SHIFT + 2, 2);
d17b7cdc 578 uint32_t neg_real = flip ^ neg_imag;
18fc2405
RH		 579 intptr_t elements = opr_sz / sizeof(float32);
580 intptr_t eltspersegment = 16 / sizeof(float32);
581 intptr_t i, j;
d17b7cdc
RH		 582
583 /* Shift boolean to the sign bit so we can xor to negate. */
584 neg_real <<= 31;
585 neg_imag <<= 31;
d17b7cdc 586
18fc2405
RH		 587 for (i = 0; i < elements; i += eltspersegment) {
588 float32 mr = m[H4(i + 2 * index + 0)];
589 float32 mi = m[H4(i + 2 * index + 1)];
590 float32 e1 = neg_real ^ (flip ? mi : mr);
591 float32 e3 = neg_imag ^ (flip ? mr : mi);
d17b7cdc 592
18fc2405
RH		 593 for (j = i; j < i + eltspersegment; j += 2) {
594 float32 e2 = n[H4(j + flip)];
595 float32 e4 = e2;
596
597 d[H4(j)] = float32_muladd(e2, e1, d[H4(j)], 0, fpst);
598 d[H4(j + 1)] = float32_muladd(e4, e3, d[H4(j + 1)], 0, fpst);
599 }
d17b7cdc
RH		 600 }
601 clear_tail(d, opr_sz, simd_maxsz(desc));
602}
603
604void HELPER(gvec_fcmlad)(void *vd, void *vn, void *vm,
605 void *vfpst, uint32_t desc)
606{
607 uintptr_t opr_sz = simd_oprsz(desc);
608 float64 *d = vd;
609 float64 *n = vn;
610 float64 *m = vm;
611 float_status *fpst = vfpst;
612 intptr_t flip = extract32(desc, SIMD_DATA_SHIFT, 1);
613 uint64_t neg_imag = extract32(desc, SIMD_DATA_SHIFT + 1, 1);
614 uint64_t neg_real = flip ^ neg_imag;
615 uintptr_t i;
616
617 /* Shift boolean to the sign bit so we can xor to negate. */
618 neg_real <<= 63;
619 neg_imag <<= 63;
620
621 for (i = 0; i < opr_sz / 8; i += 2) {
622 float64 e2 = n[i + flip];
623 float64 e1 = m[i + flip] ^ neg_real;
624 float64 e4 = e2;
625 float64 e3 = m[i + 1 - flip] ^ neg_imag;
626
627 d[i] = float64_muladd(e2, e1, d[i], 0, fpst);
628 d[i + 1] = float64_muladd(e4, e3, d[i + 1], 0, fpst);
629 }
630 clear_tail(d, opr_sz, simd_maxsz(desc));
631}
29b80469 632
3887c038
RH		 633#define DO_2OP(NAME, FUNC, TYPE) \
634void HELPER(NAME)(void *vd, void *vn, void *stat, uint32_t desc) \
635{ \
636 intptr_t i, oprsz = simd_oprsz(desc); \
637 TYPE *d = vd, *n = vn; \
638 for (i = 0; i < oprsz / sizeof(TYPE); i++) { \
639 d[i] = FUNC(n[i], stat); \
640 } \
d8efe78e 641 clear_tail(d, oprsz, simd_maxsz(desc)); \
3887c038
RH		 642}
643
644DO_2OP(gvec_frecpe_h, helper_recpe_f16, float16)
645DO_2OP(gvec_frecpe_s, helper_recpe_f32, float32)
646DO_2OP(gvec_frecpe_d, helper_recpe_f64, float64)
647
648DO_2OP(gvec_frsqrte_h, helper_rsqrte_f16, float16)
649DO_2OP(gvec_frsqrte_s, helper_rsqrte_f32, float32)
650DO_2OP(gvec_frsqrte_d, helper_rsqrte_f64, float64)
651
652#undef DO_2OP
653
29b80469
RH		 654/* Floating-point trigonometric starting value.
655 * See the ARM ARM pseudocode function FPTrigSMul.
656 */
657static float16 float16_ftsmul(float16 op1, uint16_t op2, float_status *stat)
658{
659 float16 result = float16_mul(op1, op1, stat);
660 if (!float16_is_any_nan(result)) {
661 result = float16_set_sign(result, op2 & 1);
662 }
663 return result;
664}
665
666static float32 float32_ftsmul(float32 op1, uint32_t op2, float_status *stat)
667{
668 float32 result = float32_mul(op1, op1, stat);
669 if (!float32_is_any_nan(result)) {
670 result = float32_set_sign(result, op2 & 1);
671 }
672 return result;
673}
674
675static float64 float64_ftsmul(float64 op1, uint64_t op2, float_status *stat)
676{
677 float64 result = float64_mul(op1, op1, stat);
678 if (!float64_is_any_nan(result)) {
679 result = float64_set_sign(result, op2 & 1);
680 }
681 return result;
682}
683
684#define DO_3OP(NAME, FUNC, TYPE) \
685void HELPER(NAME)(void *vd, void *vn, void *vm, void *stat, uint32_t desc) \
686{ \
687 intptr_t i, oprsz = simd_oprsz(desc); \
688 TYPE *d = vd, *n = vn, *m = vm; \
689 for (i = 0; i < oprsz / sizeof(TYPE); i++) { \
690 d[i] = FUNC(n[i], m[i], stat); \
691 } \
d8efe78e 692 clear_tail(d, oprsz, simd_maxsz(desc)); \
29b80469
RH		 693}
694
695DO_3OP(gvec_fadd_h, float16_add, float16)
696DO_3OP(gvec_fadd_s, float32_add, float32)
697DO_3OP(gvec_fadd_d, float64_add, float64)
698
699DO_3OP(gvec_fsub_h, float16_sub, float16)
700DO_3OP(gvec_fsub_s, float32_sub, float32)
701DO_3OP(gvec_fsub_d, float64_sub, float64)
702
703DO_3OP(gvec_fmul_h, float16_mul, float16)
704DO_3OP(gvec_fmul_s, float32_mul, float32)
705DO_3OP(gvec_fmul_d, float64_mul, float64)
706
707DO_3OP(gvec_ftsmul_h, float16_ftsmul, float16)
708DO_3OP(gvec_ftsmul_s, float32_ftsmul, float32)
709DO_3OP(gvec_ftsmul_d, float64_ftsmul, float64)
710
711#ifdef TARGET_AARCH64
712
713DO_3OP(gvec_recps_h, helper_recpsf_f16, float16)
714DO_3OP(gvec_recps_s, helper_recpsf_f32, float32)
715DO_3OP(gvec_recps_d, helper_recpsf_f64, float64)
716
717DO_3OP(gvec_rsqrts_h, helper_rsqrtsf_f16, float16)
718DO_3OP(gvec_rsqrts_s, helper_rsqrtsf_f32, float32)
719DO_3OP(gvec_rsqrts_d, helper_rsqrtsf_f64, float64)
720
721#endif
722#undef DO_3OP
ca40a6e6
RH		 723
724/* For the indexed ops, SVE applies the index per 128-bit vector segment.
725 * For AdvSIMD, there is of course only one such vector segment.
726 */
727
728#define DO_MUL_IDX(NAME, TYPE, H) \
729void HELPER(NAME)(void *vd, void *vn, void *vm, void *stat, uint32_t desc) \
730{ \
731 intptr_t i, j, oprsz = simd_oprsz(desc), segment = 16 / sizeof(TYPE); \
732 intptr_t idx = simd_data(desc); \
733 TYPE *d = vd, *n = vn, *m = vm; \
734 for (i = 0; i < oprsz / sizeof(TYPE); i += segment) { \
735 TYPE mm = m[H(i + idx)]; \
736 for (j = 0; j < segment; j++) { \
737 d[i + j] = TYPE##_mul(n[i + j], mm, stat); \
738 } \
739 } \
740}
741
742DO_MUL_IDX(gvec_fmul_idx_h, float16, H2)
743DO_MUL_IDX(gvec_fmul_idx_s, float32, H4)
744DO_MUL_IDX(gvec_fmul_idx_d, float64, )
745
746#undef DO_MUL_IDX
747
748#define DO_FMLA_IDX(NAME, TYPE, H) \
749void HELPER(NAME)(void *vd, void *vn, void *vm, void *va, \
750 void *stat, uint32_t desc) \
751{ \
752 intptr_t i, j, oprsz = simd_oprsz(desc), segment = 16 / sizeof(TYPE); \
753 TYPE op1_neg = extract32(desc, SIMD_DATA_SHIFT, 1); \
754 intptr_t idx = desc >> (SIMD_DATA_SHIFT + 1); \
755 TYPE *d = vd, *n = vn, *m = vm, *a = va; \
756 op1_neg <<= (8 * sizeof(TYPE) - 1); \
757 for (i = 0; i < oprsz / sizeof(TYPE); i += segment) { \
758 TYPE mm = m[H(i + idx)]; \
759 for (j = 0; j < segment; j++) { \
760 d[i + j] = TYPE##_muladd(n[i + j] ^ op1_neg, \
761 mm, a[i + j], 0, stat); \
762 } \
763 } \
764}
765
766DO_FMLA_IDX(gvec_fmla_idx_h, float16, H2)
767DO_FMLA_IDX(gvec_fmla_idx_s, float32, H4)
768DO_FMLA_IDX(gvec_fmla_idx_d, float64, )
769
770#undef DO_FMLA_IDX
89e68b57
RH		 771
772#define DO_SAT(NAME, WTYPE, TYPEN, TYPEM, OP, MIN, MAX) \
773void HELPER(NAME)(void *vd, void *vq, void *vn, void *vm, uint32_t desc) \
774{ \
775 intptr_t i, oprsz = simd_oprsz(desc); \
776 TYPEN *d = vd, *n = vn; TYPEM *m = vm; \
777 bool q = false; \
778 for (i = 0; i < oprsz / sizeof(TYPEN); i++) { \
779 WTYPE dd = (WTYPE)n[i] OP m[i]; \
780 if (dd < MIN) { \
781 dd = MIN; \
782 q = true; \
783 } else if (dd > MAX) { \
784 dd = MAX; \
785 q = true; \
786 } \
787 d[i] = dd; \
788 } \
789 if (q) { \
790 uint32_t *qc = vq; \
791 qc[0] = 1; \
792 } \
793 clear_tail(d, oprsz, simd_maxsz(desc)); \
794}
795
796DO_SAT(gvec_uqadd_b, int, uint8_t, uint8_t, +, 0, UINT8_MAX)
797DO_SAT(gvec_uqadd_h, int, uint16_t, uint16_t, +, 0, UINT16_MAX)
798DO_SAT(gvec_uqadd_s, int64_t, uint32_t, uint32_t, +, 0, UINT32_MAX)
799
800DO_SAT(gvec_sqadd_b, int, int8_t, int8_t, +, INT8_MIN, INT8_MAX)
801DO_SAT(gvec_sqadd_h, int, int16_t, int16_t, +, INT16_MIN, INT16_MAX)
802DO_SAT(gvec_sqadd_s, int64_t, int32_t, int32_t, +, INT32_MIN, INT32_MAX)
803
804DO_SAT(gvec_uqsub_b, int, uint8_t, uint8_t, -, 0, UINT8_MAX)
805DO_SAT(gvec_uqsub_h, int, uint16_t, uint16_t, -, 0, UINT16_MAX)
806DO_SAT(gvec_uqsub_s, int64_t, uint32_t, uint32_t, -, 0, UINT32_MAX)
807
808DO_SAT(gvec_sqsub_b, int, int8_t, int8_t, -, INT8_MIN, INT8_MAX)
809DO_SAT(gvec_sqsub_h, int, int16_t, int16_t, -, INT16_MIN, INT16_MAX)
810DO_SAT(gvec_sqsub_s, int64_t, int32_t, int32_t, -, INT32_MIN, INT32_MAX)
811
812#undef DO_SAT
813
814void HELPER(gvec_uqadd_d)(void *vd, void *vq, void *vn,
815 void *vm, uint32_t desc)
816{
817 intptr_t i, oprsz = simd_oprsz(desc);
818 uint64_t *d = vd, *n = vn, *m = vm;
819 bool q = false;
820
821 for (i = 0; i < oprsz / 8; i++) {
822 uint64_t nn = n[i], mm = m[i], dd = nn + mm;
823 if (dd < nn) {
824 dd = UINT64_MAX;
825 q = true;
826 }
827 d[i] = dd;
828 }
829 if (q) {
830 uint32_t *qc = vq;
831 qc[0] = 1;
832 }
833 clear_tail(d, oprsz, simd_maxsz(desc));
834}
835
836void HELPER(gvec_uqsub_d)(void *vd, void *vq, void *vn,
837 void *vm, uint32_t desc)
838{
839 intptr_t i, oprsz = simd_oprsz(desc);
840 uint64_t *d = vd, *n = vn, *m = vm;
841 bool q = false;
842
843 for (i = 0; i < oprsz / 8; i++) {
844 uint64_t nn = n[i], mm = m[i], dd = nn - mm;
845 if (nn < mm) {
846 dd = 0;
847 q = true;
848 }
849 d[i] = dd;
850 }
851 if (q) {
852 uint32_t *qc = vq;
853 qc[0] = 1;
854 }
855 clear_tail(d, oprsz, simd_maxsz(desc));
856}
857
858void HELPER(gvec_sqadd_d)(void *vd, void *vq, void *vn,
859 void *vm, uint32_t desc)
860{
861 intptr_t i, oprsz = simd_oprsz(desc);
862 int64_t *d = vd, *n = vn, *m = vm;
863 bool q = false;
864
865 for (i = 0; i < oprsz / 8; i++) {
866 int64_t nn = n[i], mm = m[i], dd = nn + mm;
867 if (((dd ^ nn) & ~(nn ^ mm)) & INT64_MIN) {
868 dd = (nn >> 63) ^ ~INT64_MIN;
869 q = true;
870 }
871 d[i] = dd;
872 }
873 if (q) {
874 uint32_t *qc = vq;
875 qc[0] = 1;
876 }
877 clear_tail(d, oprsz, simd_maxsz(desc));
878}
879
880void HELPER(gvec_sqsub_d)(void *vd, void *vq, void *vn,
881 void *vm, uint32_t desc)
882{
883 intptr_t i, oprsz = simd_oprsz(desc);
884 int64_t *d = vd, *n = vn, *m = vm;
885 bool q = false;
886
887 for (i = 0; i < oprsz / 8; i++) {
888 int64_t nn = n[i], mm = m[i], dd = nn - mm;
889 if (((dd ^ nn) & (nn ^ mm)) & INT64_MIN) {
890 dd = (nn >> 63) ^ ~INT64_MIN;
891 q = true;
892 }
893 d[i] = dd;
894 }
895 if (q) {
896 uint32_t *qc = vq;
897 qc[0] = 1;
898 }
899 clear_tail(d, oprsz, simd_maxsz(desc));
900}
a4e943a7 901
631e5654
RH		 902
903#define DO_SRA(NAME, TYPE) \
904void HELPER(NAME)(void *vd, void *vn, uint32_t desc) \
905{ \
906 intptr_t i, oprsz = simd_oprsz(desc); \
907 int shift = simd_data(desc); \
908 TYPE *d = vd, *n = vn; \
909 for (i = 0; i < oprsz / sizeof(TYPE); i++) { \
910 d[i] += n[i] >> shift; \
911 } \
912 clear_tail(d, oprsz, simd_maxsz(desc)); \
913}
914
915DO_SRA(gvec_ssra_b, int8_t)
916DO_SRA(gvec_ssra_h, int16_t)
917DO_SRA(gvec_ssra_s, int32_t)
918DO_SRA(gvec_ssra_d, int64_t)
919
920DO_SRA(gvec_usra_b, uint8_t)
921DO_SRA(gvec_usra_h, uint16_t)
922DO_SRA(gvec_usra_s, uint32_t)
923DO_SRA(gvec_usra_d, uint64_t)
924
925#undef DO_SRA
926
6ccd48d4
RH		 927#define DO_RSHR(NAME, TYPE) \
928void HELPER(NAME)(void *vd, void *vn, uint32_t desc) \
929{ \
930 intptr_t i, oprsz = simd_oprsz(desc); \
931 int shift = simd_data(desc); \
932 TYPE *d = vd, *n = vn; \
933 for (i = 0; i < oprsz / sizeof(TYPE); i++) { \
934 TYPE tmp = n[i] >> (shift - 1); \
935 d[i] = (tmp >> 1) + (tmp & 1); \
936 } \
937 clear_tail(d, oprsz, simd_maxsz(desc)); \
938}
939
940DO_RSHR(gvec_srshr_b, int8_t)
941DO_RSHR(gvec_srshr_h, int16_t)
942DO_RSHR(gvec_srshr_s, int32_t)
943DO_RSHR(gvec_srshr_d, int64_t)
944
945DO_RSHR(gvec_urshr_b, uint8_t)
946DO_RSHR(gvec_urshr_h, uint16_t)
947DO_RSHR(gvec_urshr_s, uint32_t)
948DO_RSHR(gvec_urshr_d, uint64_t)
949
950#undef DO_RSHR
951
952#define DO_RSRA(NAME, TYPE) \
953void HELPER(NAME)(void *vd, void *vn, uint32_t desc) \
954{ \
955 intptr_t i, oprsz = simd_oprsz(desc); \
956 int shift = simd_data(desc); \
957 TYPE *d = vd, *n = vn; \
958 for (i = 0; i < oprsz / sizeof(TYPE); i++) { \
959 TYPE tmp = n[i] >> (shift - 1); \
960 d[i] += (tmp >> 1) + (tmp & 1); \
961 } \
962 clear_tail(d, oprsz, simd_maxsz(desc)); \
963}
964
965DO_RSRA(gvec_srsra_b, int8_t)
966DO_RSRA(gvec_srsra_h, int16_t)
967DO_RSRA(gvec_srsra_s, int32_t)
968DO_RSRA(gvec_srsra_d, int64_t)
969
970DO_RSRA(gvec_ursra_b, uint8_t)
971DO_RSRA(gvec_ursra_h, uint16_t)
972DO_RSRA(gvec_ursra_s, uint32_t)
973DO_RSRA(gvec_ursra_d, uint64_t)
974
975#undef DO_RSRA
976
a4e943a7
RH		 977/*
978 * Convert float16 to float32, raising no exceptions and
979 * preserving exceptional values, including SNaN.
980 * This is effectively an unpack+repack operation.
981 */
982static float32 float16_to_float32_by_bits(uint32_t f16, bool fz16)
983{
984 const int f16_bias = 15;
985 const int f32_bias = 127;
986 uint32_t sign = extract32(f16, 15, 1);
987 uint32_t exp = extract32(f16, 10, 5);
988 uint32_t frac = extract32(f16, 0, 10);
989
990 if (exp == 0x1f) {
991 /* Inf or NaN */
992 exp = 0xff;
993 } else if (exp == 0) {
994 /* Zero or denormal. */
995 if (frac != 0) {
996 if (fz16) {
997 frac = 0;
998 } else {
999 /*
1000 * Denormal; these are all normal float32.
1001 * Shift the fraction so that the msb is at bit 11,
1002 * then remove bit 11 as the implicit bit of the
1003 * normalized float32. Note that we still go through
1004 * the shift for normal numbers below, to put the
1005 * float32 fraction at the right place.
1006 */
1007 int shift = clz32(frac) - 21;
1008 frac = (frac << shift) & 0x3ff;
1009 exp = f32_bias - f16_bias - shift + 1;
1010 }
1011 }
1012 } else {
1013 /* Normal number; adjust the bias. */
1014 exp += f32_bias - f16_bias;
1015 }
1016 sign <<= 31;
1017 exp <<= 23;
1018 frac <<= 23 - 10;
1019
1020 return sign | exp | frac;
1021}
1022
1023static uint64_t load4_f16(uint64_t *ptr, int is_q, int is_2)
1024{
1025 /*
1026 * Branchless load of u32[0], u64[0], u32[1], or u64[1].
1027 * Load the 2nd qword iff is_q & is_2.
1028 * Shift to the 2nd dword iff !is_q & is_2.
1029 * For !is_q & !is_2, the upper bits of the result are garbage.
1030 */
1031 return ptr[is_q & is_2] >> ((is_2 & ~is_q) << 5);
1032}
1033
1034/*
1035 * Note that FMLAL requires oprsz == 8 or oprsz == 16,
1036 * as there is not yet SVE versions that might use blocking.
1037 */
1038
1039static void do_fmlal(float32 *d, void *vn, void *vm, float_status *fpst,
1040 uint32_t desc, bool fz16)
1041{
1042 intptr_t i, oprsz = simd_oprsz(desc);
1043 int is_s = extract32(desc, SIMD_DATA_SHIFT, 1);
1044 int is_2 = extract32(desc, SIMD_DATA_SHIFT + 1, 1);
1045 int is_q = oprsz == 16;
1046 uint64_t n_4, m_4;
1047
1048 /* Pre-load all of the f16 data, avoiding overlap issues. */
1049 n_4 = load4_f16(vn, is_q, is_2);
1050 m_4 = load4_f16(vm, is_q, is_2);
1051
1052 /* Negate all inputs for FMLSL at once. */
1053 if (is_s) {
1054 n_4 ^= 0x8000800080008000ull;
1055 }
1056
1057 for (i = 0; i < oprsz / 4; i++) {
1058 float32 n_1 = float16_to_float32_by_bits(n_4 >> (i * 16), fz16);
1059 float32 m_1 = float16_to_float32_by_bits(m_4 >> (i * 16), fz16);
1060 d[H4(i)] = float32_muladd(n_1, m_1, d[H4(i)], 0, fpst);
1061 }
1062 clear_tail(d, oprsz, simd_maxsz(desc));
1063}
1064
1065void HELPER(gvec_fmlal_a32)(void *vd, void *vn, void *vm,
1066 void *venv, uint32_t desc)
1067{
1068 CPUARMState *env = venv;
1069 do_fmlal(vd, vn, vm, &env->vfp.standard_fp_status, desc,
1070 get_flush_inputs_to_zero(&env->vfp.fp_status_f16));
1071}
1072
1073void HELPER(gvec_fmlal_a64)(void *vd, void *vn, void *vm,
1074 void *venv, uint32_t desc)
1075{
1076 CPUARMState *env = venv;
1077 do_fmlal(vd, vn, vm, &env->vfp.fp_status, desc,
1078 get_flush_inputs_to_zero(&env->vfp.fp_status_f16));
1079}
1080
1081static void do_fmlal_idx(float32 *d, void *vn, void *vm, float_status *fpst,
1082 uint32_t desc, bool fz16)
1083{
1084 intptr_t i, oprsz = simd_oprsz(desc);
1085 int is_s = extract32(desc, SIMD_DATA_SHIFT, 1);
1086 int is_2 = extract32(desc, SIMD_DATA_SHIFT + 1, 1);
1087 int index = extract32(desc, SIMD_DATA_SHIFT + 2, 3);
1088 int is_q = oprsz == 16;
1089 uint64_t n_4;
1090 float32 m_1;
1091
1092 /* Pre-load all of the f16 data, avoiding overlap issues. */
1093 n_4 = load4_f16(vn, is_q, is_2);
1094
1095 /* Negate all inputs for FMLSL at once. */
1096 if (is_s) {
1097 n_4 ^= 0x8000800080008000ull;
1098 }
1099
1100 m_1 = float16_to_float32_by_bits(((float16 *)vm)[H2(index)], fz16);
1101
1102 for (i = 0; i < oprsz / 4; i++) {
1103 float32 n_1 = float16_to_float32_by_bits(n_4 >> (i * 16), fz16);
1104 d[H4(i)] = float32_muladd(n_1, m_1, d[H4(i)], 0, fpst);
1105 }
1106 clear_tail(d, oprsz, simd_maxsz(desc));
1107}
1108
1109void HELPER(gvec_fmlal_idx_a32)(void *vd, void *vn, void *vm,
1110 void *venv, uint32_t desc)
1111{
1112 CPUARMState *env = venv;
1113 do_fmlal_idx(vd, vn, vm, &env->vfp.standard_fp_status, desc,
1114 get_flush_inputs_to_zero(&env->vfp.fp_status_f16));
1115}
1116
1117void HELPER(gvec_fmlal_idx_a64)(void *vd, void *vn, void *vm,
1118 void *venv, uint32_t desc)
1119{
1120 CPUARMState *env = venv;
1121 do_fmlal_idx(vd, vn, vm, &env->vfp.fp_status, desc,
1122 get_flush_inputs_to_zero(&env->vfp.fp_status_f16));
1123}
87b74e8b
RH		 1124
1125void HELPER(gvec_sshl_b)(void *vd, void *vn, void *vm, uint32_t desc)
1126{
1127 intptr_t i, opr_sz = simd_oprsz(desc);
1128 int8_t *d = vd, *n = vn, *m = vm;
1129
1130 for (i = 0; i < opr_sz; ++i) {
1131 int8_t mm = m[i];
1132 int8_t nn = n[i];
1133 int8_t res = 0;
1134 if (mm >= 0) {
1135 if (mm < 8) {
1136 res = nn << mm;
1137 }
1138 } else {
1139 res = nn >> (mm > -8 ? -mm : 7);
1140 }
1141 d[i] = res;
1142 }
1143 clear_tail(d, opr_sz, simd_maxsz(desc));
1144}
1145
1146void HELPER(gvec_sshl_h)(void *vd, void *vn, void *vm, uint32_t desc)
1147{
1148 intptr_t i, opr_sz = simd_oprsz(desc);
1149 int16_t *d = vd, *n = vn, *m = vm;
1150
1151 for (i = 0; i < opr_sz / 2; ++i) {
1152 int8_t mm = m[i]; /* only 8 bits of shift are significant */
1153 int16_t nn = n[i];
1154 int16_t res = 0;
1155 if (mm >= 0) {
1156 if (mm < 16) {
1157 res = nn << mm;
1158 }
1159 } else {
1160 res = nn >> (mm > -16 ? -mm : 15);
1161 }
1162 d[i] = res;
1163 }
1164 clear_tail(d, opr_sz, simd_maxsz(desc));
1165}
1166
1167void HELPER(gvec_ushl_b)(void *vd, void *vn, void *vm, uint32_t desc)
1168{
1169 intptr_t i, opr_sz = simd_oprsz(desc);
1170 uint8_t *d = vd, *n = vn, *m = vm;
1171
1172 for (i = 0; i < opr_sz; ++i) {
1173 int8_t mm = m[i];
1174 uint8_t nn = n[i];
1175 uint8_t res = 0;
1176 if (mm >= 0) {
1177 if (mm < 8) {
1178 res = nn << mm;
1179 }
1180 } else {
1181 if (mm > -8) {
1182 res = nn >> -mm;
1183 }
1184 }
1185 d[i] = res;
1186 }
1187 clear_tail(d, opr_sz, simd_maxsz(desc));
1188}
1189
1190void HELPER(gvec_ushl_h)(void *vd, void *vn, void *vm, uint32_t desc)
1191{
1192 intptr_t i, opr_sz = simd_oprsz(desc);
1193 uint16_t *d = vd, *n = vn, *m = vm;
1194
1195 for (i = 0; i < opr_sz / 2; ++i) {
1196 int8_t mm = m[i]; /* only 8 bits of shift are significant */
1197 uint16_t nn = n[i];
1198 uint16_t res = 0;
1199 if (mm >= 0) {
1200 if (mm < 16) {
1201 res = nn << mm;
1202 }
1203 } else {
1204 if (mm > -16) {
1205 res = nn >> -mm;
1206 }
1207 }
1208 d[i] = res;
1209 }
1210 clear_tail(d, opr_sz, simd_maxsz(desc));
1211}
a21bb78e
RH		 1212
1213/*
1214 * 8x8->8 polynomial multiply.
1215 *
1216 * Polynomial multiplication is like integer multiplication except the
1217 * partial products are XORed, not added.
1218 *
1219 * TODO: expose this as a generic vector operation, as it is a common
1220 * crypto building block.
1221 */
1222void HELPER(gvec_pmul_b)(void *vd, void *vn, void *vm, uint32_t desc)
1223{
1224 intptr_t i, j, opr_sz = simd_oprsz(desc);
1225 uint64_t *d = vd, *n = vn, *m = vm;
1226
1227 for (i = 0; i < opr_sz / 8; ++i) {
1228 uint64_t nn = n[i];
1229 uint64_t mm = m[i];
1230 uint64_t rr = 0;
1231
1232 for (j = 0; j < 8; ++j) {
1233 uint64_t mask = (nn & 0x0101010101010101ull) * 0xff;
1234 rr ^= mm & mask;
1235 mm = (mm << 1) & 0xfefefefefefefefeull;
1236 nn >>= 1;
1237 }
1238 d[i] = rr;
1239 }
1240 clear_tail(d, opr_sz, simd_maxsz(desc));
1241}
b9ed510e
RH		 1242
1243/*
1244 * 64x64->128 polynomial multiply.
1245 * Because of the lanes are not accessed in strict columns,
1246 * this probably cannot be turned into a generic helper.
1247 */
1248void HELPER(gvec_pmull_q)(void *vd, void *vn, void *vm, uint32_t desc)
1249{
1250 intptr_t i, j, opr_sz = simd_oprsz(desc);
1251 intptr_t hi = simd_data(desc);
1252 uint64_t *d = vd, *n = vn, *m = vm;
1253
1254 for (i = 0; i < opr_sz / 8; i += 2) {
1255 uint64_t nn = n[i + hi];
1256 uint64_t mm = m[i + hi];
1257 uint64_t rhi = 0;
1258 uint64_t rlo = 0;
1259
1260 /* Bit 0 can only influence the low 64-bit result. */
1261 if (nn & 1) {
1262 rlo = mm;
1263 }
1264
1265 for (j = 1; j < 64; ++j) {
1266 uint64_t mask = -((nn >> j) & 1);
1267 rlo ^= (mm << j) & mask;
1268 rhi ^= (mm >> (64 - j)) & mask;
1269 }
1270 d[i] = rlo;
1271 d[i + 1] = rhi;
1272 }
1273 clear_tail(d, opr_sz, simd_maxsz(desc));
1274}
e7e96fc5
RH		 1275
1276/*
1277 * 8x8->16 polynomial multiply.
1278 *
1279 * The byte inputs are expanded to (or extracted from) half-words.
1280 * Note that neon and sve2 get the inputs from different positions.
1281 * This allows 4 bytes to be processed in parallel with uint64_t.
1282 */
1283
1284static uint64_t expand_byte_to_half(uint64_t x)
1285{
1286 return (x & 0x000000ff)
1287 | ((x & 0x0000ff00) << 8)
1288 | ((x & 0x00ff0000) << 16)
1289 | ((x & 0xff000000) << 24);
1290}
1291
1292static uint64_t pmull_h(uint64_t op1, uint64_t op2)
1293{
1294 uint64_t result = 0;
1295 int i;
1296
1297 for (i = 0; i < 8; ++i) {
1298 uint64_t mask = (op1 & 0x0001000100010001ull) * 0xffff;
1299 result ^= op2 & mask;
1300 op1 >>= 1;
1301 op2 <<= 1;
1302 }
1303 return result;
1304}
1305
1306void HELPER(neon_pmull_h)(void *vd, void *vn, void *vm, uint32_t desc)
1307{
1308 int hi = simd_data(desc);
1309 uint64_t *d = vd, *n = vn, *m = vm;
1310 uint64_t nn = n[hi], mm = m[hi];
1311
1312 d[0] = pmull_h(expand_byte_to_half(nn), expand_byte_to_half(mm));
1313 nn >>= 32;
1314 mm >>= 32;
1315 d[1] = pmull_h(expand_byte_to_half(nn), expand_byte_to_half(mm));
1316
1317 clear_tail(d, 16, simd_maxsz(desc));
1318}
1319
1320#ifdef TARGET_AARCH64
1321void HELPER(sve2_pmull_h)(void *vd, void *vn, void *vm, uint32_t desc)
1322{
1323 int shift = simd_data(desc) * 8;
1324 intptr_t i, opr_sz = simd_oprsz(desc);
1325 uint64_t *d = vd, *n = vn, *m = vm;
1326
1327 for (i = 0; i < opr_sz / 8; ++i) {
1328 uint64_t nn = (n[i] >> shift) & 0x00ff00ff00ff00ffull;
1329 uint64_t mm = (m[i] >> shift) & 0x00ff00ff00ff00ffull;
1330
1331 d[i] = pmull_h(nn, mm);
1332 }
1333}
1334#endif
6b375d35
RH		 1335
1336#define DO_CMP0(NAME, TYPE, OP) \
1337void HELPER(NAME)(void *vd, void *vn, uint32_t desc) \
1338{ \
1339 intptr_t i, opr_sz = simd_oprsz(desc); \
1340 for (i = 0; i < opr_sz; i += sizeof(TYPE)) { \
1341 TYPE nn = *(TYPE *)(vn + i); \
1342 *(TYPE *)(vd + i) = -(nn OP 0); \
1343 } \
1344 clear_tail(vd, opr_sz, simd_maxsz(desc)); \
1345}
1346
1347DO_CMP0(gvec_ceq0_b, int8_t, ==)
1348DO_CMP0(gvec_clt0_b, int8_t, <)
1349DO_CMP0(gvec_cle0_b, int8_t, <=)
1350DO_CMP0(gvec_cgt0_b, int8_t, >)
1351DO_CMP0(gvec_cge0_b, int8_t, >=)
1352
1353DO_CMP0(gvec_ceq0_h, int16_t, ==)
1354DO_CMP0(gvec_clt0_h, int16_t, <)
1355DO_CMP0(gvec_cle0_h, int16_t, <=)
1356DO_CMP0(gvec_cgt0_h, int16_t, >)
1357DO_CMP0(gvec_cge0_h, int16_t, >=)
1358
1359#undef DO_CMP0
Empty description
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