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s390x: fix s390-virtio-serial
[qemu.git] / cpu-exec.c
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7d13299d
FB		 1/*
2 * i386 emulator main execution loop
5fafdf24 3 *
66321a11 4 * Copyright (c) 2003-2005 Fabrice Bellard
7d13299d 5 *
3ef693a0
FB		 6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
7d13299d 10 *
3ef693a0
FB		 11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
7d13299d 15 *
3ef693a0 16 * You should have received a copy of the GNU Lesser General Public
8167ee88 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
7d13299d 18 */
e4533c7a 19#include "config.h"
93ac68bc 20#include "exec.h"
956034d7 21#include "disas.h"
7cb69cae 22#include "tcg.h"
7ba1e619 23#include "kvm.h"
1d93f0f0 24#include "qemu-barrier.h"
7d13299d 25
fbf9eeb3
FB		 26#if !defined(CONFIG_SOFTMMU)
27#undef EAX
28#undef ECX
29#undef EDX
30#undef EBX
31#undef ESP
32#undef EBP
33#undef ESI
34#undef EDI
35#undef EIP
36#include <signal.h>
84778508 37#ifdef __linux__
fbf9eeb3
FB		 38#include <sys/ucontext.h>
39#endif
84778508 40#endif
fbf9eeb3 41
dfe5fff3 42#if defined(__sparc__) && !defined(CONFIG_SOLARIS)
572a9d4a
BS		 43// Work around ugly bugs in glibc that mangle global register contents
44#undef env
45#define env cpu_single_env
46#endif
47
36bdbe54
FB		 48int tb_invalidated_flag;
49
f0667e66 50//#define CONFIG_DEBUG_EXEC
9de5e440 51//#define DEBUG_SIGNAL
7d13299d 52
6a4955a8
AL		 53int qemu_cpu_has_work(CPUState *env)
54{
55 return cpu_has_work(env);
56}
57
e4533c7a
FB		 58void cpu_loop_exit(void)
59{
1c3569fe 60 env->current_tb = NULL;
e4533c7a
FB		 61 longjmp(env->jmp_env, 1);
62}
bfed01fc 63
fbf9eeb3
FB		 64/* exit the current TB from a signal handler. The host registers are
65 restored in a state compatible with the CPU emulator
66 */
5fafdf24 67void cpu_resume_from_signal(CPUState *env1, void *puc)
fbf9eeb3
FB		 68{
69#if !defined(CONFIG_SOFTMMU)
84778508 70#ifdef __linux__
fbf9eeb3 71 struct ucontext *uc = puc;
84778508
BS		 72#elif defined(__OpenBSD__)
73 struct sigcontext *uc = puc;
74#endif
fbf9eeb3
FB		 75#endif
76
77 env = env1;
78
79 /* XXX: restore cpu registers saved in host registers */
80
81#if !defined(CONFIG_SOFTMMU)
82 if (puc) {
83 /* XXX: use siglongjmp ? */
84778508 84#ifdef __linux__
60e99246
AJ		 85#ifdef __ia64
86 sigprocmask(SIG_SETMASK, (sigset_t *)&uc->uc_sigmask, NULL);
87#else
fbf9eeb3 88 sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
60e99246 89#endif
84778508
BS		 90#elif defined(__OpenBSD__)
91 sigprocmask(SIG_SETMASK, &uc->sc_mask, NULL);
92#endif
fbf9eeb3
FB		 93 }
94#endif
9a3ea654 95 env->exception_index = -1;
fbf9eeb3
FB		 96 longjmp(env->jmp_env, 1);
97}
98
2e70f6ef
PB		 99/* Execute the code without caching the generated code. An interpreter
100 could be used if available. */
101static void cpu_exec_nocache(int max_cycles, TranslationBlock *orig_tb)
102{
103 unsigned long next_tb;
104 TranslationBlock *tb;
105
106 /* Should never happen.
107 We only end up here when an existing TB is too long. */
108 if (max_cycles > CF_COUNT_MASK)
109 max_cycles = CF_COUNT_MASK;
110
111 tb = tb_gen_code(env, orig_tb->pc, orig_tb->cs_base, orig_tb->flags,
112 max_cycles);
113 env->current_tb = tb;
114 /* execute the generated code */
115 next_tb = tcg_qemu_tb_exec(tb->tc_ptr);
1c3569fe 116 env->current_tb = NULL;
2e70f6ef
PB		 117
118 if ((next_tb & 3) == 2) {
119 /* Restore PC. This may happen if async event occurs before
120 the TB starts executing. */
622ed360 121 cpu_pc_from_tb(env, tb);
2e70f6ef
PB		 122 }
123 tb_phys_invalidate(tb, -1);
124 tb_free(tb);
125}
126
8a40a180
FB		 127static TranslationBlock *tb_find_slow(target_ulong pc,
128 target_ulong cs_base,
c068688b 129 uint64_t flags)
8a40a180
FB		 130{
131 TranslationBlock *tb, **ptb1;
8a40a180 132 unsigned int h;
41c1b1c9
PB		 133 tb_page_addr_t phys_pc, phys_page1, phys_page2;
134 target_ulong virt_page2;
3b46e624 135
8a40a180 136 tb_invalidated_flag = 0;
3b46e624 137
8a40a180 138 /* find translated block using physical mappings */
41c1b1c9 139 phys_pc = get_page_addr_code(env, pc);
8a40a180
FB		 140 phys_page1 = phys_pc & TARGET_PAGE_MASK;
141 phys_page2 = -1;
142 h = tb_phys_hash_func(phys_pc);
143 ptb1 = &tb_phys_hash[h];
144 for(;;) {
145 tb = *ptb1;
146 if (!tb)
147 goto not_found;
5fafdf24 148 if (tb->pc == pc &&
8a40a180 149 tb->page_addr[0] == phys_page1 &&
5fafdf24 150 tb->cs_base == cs_base &&
8a40a180
FB		 151 tb->flags == flags) {
152 /* check next page if needed */
153 if (tb->page_addr[1] != -1) {
5fafdf24 154 virt_page2 = (pc & TARGET_PAGE_MASK) +
8a40a180 155 TARGET_PAGE_SIZE;
41c1b1c9 156 phys_page2 = get_page_addr_code(env, virt_page2);
8a40a180
FB		 157 if (tb->page_addr[1] == phys_page2)
158 goto found;
159 } else {
160 goto found;
161 }
162 }
163 ptb1 = &tb->phys_hash_next;
164 }
165 not_found:
2e70f6ef
PB		 166 /* if no translated code available, then translate it now */
167 tb = tb_gen_code(env, pc, cs_base, flags, 0);
3b46e624 168
8a40a180 169 found:
2c90fe2b
KB		 170 /* Move the last found TB to the head of the list */
171 if (likely(*ptb1)) {
172 *ptb1 = tb->phys_hash_next;
173 tb->phys_hash_next = tb_phys_hash[h];
174 tb_phys_hash[h] = tb;
175 }
8a40a180
FB		 176 /* we add the TB in the virtual pc hash table */
177 env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)] = tb;
8a40a180
FB		 178 return tb;
179}
180
181static inline TranslationBlock *tb_find_fast(void)
182{
183 TranslationBlock *tb;
184 target_ulong cs_base, pc;
6b917547 185 int flags;
8a40a180
FB		 186
187 /* we record a subset of the CPU state. It will
188 always be the same before a given translated block
189 is executed. */
6b917547 190 cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags);
bce61846 191 tb = env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)];
551bd27f
TS		 192 if (unlikely(!tb || tb->pc != pc || tb->cs_base != cs_base ||
193 tb->flags != flags)) {
8a40a180
FB		 194 tb = tb_find_slow(pc, cs_base, flags);
195 }
196 return tb;
197}
198
1009d2ed
JK		 199static CPUDebugExcpHandler *debug_excp_handler;
200
201CPUDebugExcpHandler *cpu_set_debug_excp_handler(CPUDebugExcpHandler *handler)
202{
203 CPUDebugExcpHandler *old_handler = debug_excp_handler;
204
205 debug_excp_handler = handler;
206 return old_handler;
207}
208
209static void cpu_handle_debug_exception(CPUState *env)
210{
211 CPUWatchpoint *wp;
212
213 if (!env->watchpoint_hit) {
214 QTAILQ_FOREACH(wp, &env->watchpoints, entry) {
215 wp->flags &= ~BP_WATCHPOINT_HIT;
216 }
217 }
218 if (debug_excp_handler) {
219 debug_excp_handler(env);
220 }
221}
222
7d13299d
FB		 223/* main execution loop */
224
1a28cac3
MT		 225volatile sig_atomic_t exit_request;
226
e4533c7a 227int cpu_exec(CPUState *env1)
7d13299d 228{
1d9000e8 229 volatile host_reg_t saved_env_reg;
8a40a180 230 int ret, interrupt_request;
8a40a180 231 TranslationBlock *tb;
c27004ec 232 uint8_t *tc_ptr;
d5975363 233 unsigned long next_tb;
8c6939c0 234
eda48c34
PB		 235 if (env1->halted) {
236 if (!cpu_has_work(env1)) {
237 return EXCP_HALTED;
238 }
239
240 env1->halted = 0;
241 }
5a1e3cfc 242
5fafdf24 243 cpu_single_env = env1;
6a00d601 244
24ebf5f3
PB		 245 /* the access to env below is actually saving the global register's
246 value, so that files not including target-xyz/exec.h are free to
247 use it. */
248 QEMU_BUILD_BUG_ON (sizeof (saved_env_reg) != sizeof (env));
249 saved_env_reg = (host_reg_t) env;
1d93f0f0 250 barrier();
c27004ec 251 env = env1;
e4533c7a 252
c629a4bc 253 if (unlikely(exit_request)) {
1a28cac3 254 env->exit_request = 1;
1a28cac3
MT		 255 }
256
ecb644f4 257#if defined(TARGET_I386)
6792a57b
JK		 258 /* put eflags in CPU temporary format */
259 CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
260 DF = 1 - (2 * ((env->eflags >> 10) & 1));
261 CC_OP = CC_OP_EFLAGS;
262 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
93ac68bc 263#elif defined(TARGET_SPARC)
e6e5906b
PB		 264#elif defined(TARGET_M68K)
265 env->cc_op = CC_OP_FLAGS;
266 env->cc_dest = env->sr & 0xf;
267 env->cc_x = (env->sr >> 4) & 1;
ecb644f4
TS		 268#elif defined(TARGET_ALPHA)
269#elif defined(TARGET_ARM)
270#elif defined(TARGET_PPC)
81ea0e13 271#elif defined(TARGET_LM32)
b779e29e 272#elif defined(TARGET_MICROBLAZE)
6af0bf9c 273#elif defined(TARGET_MIPS)
fdf9b3e8 274#elif defined(TARGET_SH4)
f1ccf904 275#elif defined(TARGET_CRIS)
10ec5117 276#elif defined(TARGET_S390X)
fdf9b3e8 277 /* XXXXX */
e4533c7a
FB		 278#else
279#error unsupported target CPU
280#endif
3fb2ded1 281 env->exception_index = -1;
9d27abd9 282
7d13299d 283 /* prepare setjmp context for exception handling */
3fb2ded1
FB		 284 for(;;) {
285 if (setjmp(env->jmp_env) == 0) {
dfe5fff3 286#if defined(__sparc__) && !defined(CONFIG_SOLARIS)
9ddff3d2 287#undef env
6792a57b 288 env = cpu_single_env;
9ddff3d2
BS		 289#define env cpu_single_env
290#endif
3fb2ded1
FB		 291 /* if an exception is pending, we execute it here */
292 if (env->exception_index >= 0) {
293 if (env->exception_index >= EXCP_INTERRUPT) {
294 /* exit request from the cpu execution loop */
295 ret = env->exception_index;
1009d2ed
JK		 296 if (ret == EXCP_DEBUG) {
297 cpu_handle_debug_exception(env);
298 }
3fb2ded1 299 break;
72d239ed
AJ		 300 } else {
301#if defined(CONFIG_USER_ONLY)
3fb2ded1 302 /* if user mode only, we simulate a fake exception
9f083493 303 which will be handled outside the cpu execution
3fb2ded1 304 loop */
83479e77 305#if defined(TARGET_I386)
5fafdf24
TS		 306 do_interrupt_user(env->exception_index,
307 env->exception_is_int,
308 env->error_code,
3fb2ded1 309 env->exception_next_eip);
eba01623
FB		 310 /* successfully delivered */
311 env->old_exception = -1;
83479e77 312#endif
3fb2ded1
FB		 313 ret = env->exception_index;
314 break;
72d239ed 315#else
83479e77 316#if defined(TARGET_I386)
3fb2ded1
FB		 317 /* simulate a real cpu exception. On i386, it can
318 trigger new exceptions, but we do not handle
319 double or triple faults yet. */
5fafdf24
TS		 320 do_interrupt(env->exception_index,
321 env->exception_is_int,
322 env->error_code,
d05e66d2 323 env->exception_next_eip, 0);
678dde13
TS		 324 /* successfully delivered */
325 env->old_exception = -1;
ce09776b
FB		 326#elif defined(TARGET_PPC)
327 do_interrupt(env);
81ea0e13
MW		 328#elif defined(TARGET_LM32)
329 do_interrupt(env);
b779e29e
EI		 330#elif defined(TARGET_MICROBLAZE)
331 do_interrupt(env);
6af0bf9c
FB		 332#elif defined(TARGET_MIPS)
333 do_interrupt(env);
e95c8d51 334#elif defined(TARGET_SPARC)
f2bc7e7f 335 do_interrupt(env);
b5ff1b31
FB		 336#elif defined(TARGET_ARM)
337 do_interrupt(env);
fdf9b3e8
FB		 338#elif defined(TARGET_SH4)
339 do_interrupt(env);
eddf68a6
JM		 340#elif defined(TARGET_ALPHA)
341 do_interrupt(env);
f1ccf904
TS		 342#elif defined(TARGET_CRIS)
343 do_interrupt(env);
0633879f
PB		 344#elif defined(TARGET_M68K)
345 do_interrupt(0);
72d239ed 346#endif
301d2908 347 env->exception_index = -1;
83479e77 348#endif
3fb2ded1 349 }
5fafdf24 350 }
9df217a3 351
b5fc09ae 352 next_tb = 0; /* force lookup of first TB */
3fb2ded1 353 for(;;) {
68a79315 354 interrupt_request = env->interrupt_request;
e1638bd8 355 if (unlikely(interrupt_request)) {
356 if (unlikely(env->singlestep_enabled & SSTEP_NOIRQ)) {
357 /* Mask out external interrupts for this step. */
358 interrupt_request &= ~(CPU_INTERRUPT_HARD |
359 CPU_INTERRUPT_FIQ |
360 CPU_INTERRUPT_SMI |
361 CPU_INTERRUPT_NMI);
362 }
6658ffb8
PB		 363 if (interrupt_request & CPU_INTERRUPT_DEBUG) {
364 env->interrupt_request &= ~CPU_INTERRUPT_DEBUG;
365 env->exception_index = EXCP_DEBUG;
366 cpu_loop_exit();
367 }
a90b7318 368#if defined(TARGET_ARM) || defined(TARGET_SPARC) || defined(TARGET_MIPS) || \
b779e29e 369 defined(TARGET_PPC) || defined(TARGET_ALPHA) || defined(TARGET_CRIS) || \
81ea0e13 370 defined(TARGET_MICROBLAZE) || defined(TARGET_LM32)
a90b7318
AZ		 371 if (interrupt_request & CPU_INTERRUPT_HALT) {
372 env->interrupt_request &= ~CPU_INTERRUPT_HALT;
373 env->halted = 1;
374 env->exception_index = EXCP_HLT;
375 cpu_loop_exit();
376 }
377#endif
68a79315 378#if defined(TARGET_I386)
b09ea7d5
GN		 379 if (interrupt_request & CPU_INTERRUPT_INIT) {
380 svm_check_intercept(SVM_EXIT_INIT);
381 do_cpu_init(env);
382 env->exception_index = EXCP_HALTED;
383 cpu_loop_exit();
384 } else if (interrupt_request & CPU_INTERRUPT_SIPI) {
385 do_cpu_sipi(env);
386 } else if (env->hflags2 & HF2_GIF_MASK) {
db620f46
FB		 387 if ((interrupt_request & CPU_INTERRUPT_SMI) &&
388 !(env->hflags & HF_SMM_MASK)) {
389 svm_check_intercept(SVM_EXIT_SMI);
390 env->interrupt_request &= ~CPU_INTERRUPT_SMI;
391 do_smm_enter();
392 next_tb = 0;
393 } else if ((interrupt_request & CPU_INTERRUPT_NMI) &&
394 !(env->hflags2 & HF2_NMI_MASK)) {
395 env->interrupt_request &= ~CPU_INTERRUPT_NMI;
396 env->hflags2 |= HF2_NMI_MASK;
397 do_interrupt(EXCP02_NMI, 0, 0, 0, 1);
398 next_tb = 0;
79c4f6b0
HY		 399 } else if (interrupt_request & CPU_INTERRUPT_MCE) {
400 env->interrupt_request &= ~CPU_INTERRUPT_MCE;
401 do_interrupt(EXCP12_MCHK, 0, 0, 0, 0);
402 next_tb = 0;
db620f46
FB		 403 } else if ((interrupt_request & CPU_INTERRUPT_HARD) &&
404 (((env->hflags2 & HF2_VINTR_MASK) &&
405 (env->hflags2 & HF2_HIF_MASK)) ||
406 (!(env->hflags2 & HF2_VINTR_MASK) &&
407 (env->eflags & IF_MASK &&
408 !(env->hflags & HF_INHIBIT_IRQ_MASK))))) {
409 int intno;
410 svm_check_intercept(SVM_EXIT_INTR);
411 env->interrupt_request &= ~(CPU_INTERRUPT_HARD | CPU_INTERRUPT_VIRQ);
412 intno = cpu_get_pic_interrupt(env);
93fcfe39 413 qemu_log_mask(CPU_LOG_TB_IN_ASM, "Servicing hardware INT=0x%02x\n", intno);
dfe5fff3 414#if defined(__sparc__) && !defined(CONFIG_SOLARIS)
9ddff3d2
BS		 415#undef env
416 env = cpu_single_env;
417#define env cpu_single_env
418#endif
db620f46
FB		 419 do_interrupt(intno, 0, 0, 0, 1);
420 /* ensure that no TB jump will be modified as
421 the program flow was changed */
422 next_tb = 0;
0573fbfc 423#if !defined(CONFIG_USER_ONLY)
db620f46
FB		 424 } else if ((interrupt_request & CPU_INTERRUPT_VIRQ) &&
425 (env->eflags & IF_MASK) &&
426 !(env->hflags & HF_INHIBIT_IRQ_MASK)) {
427 int intno;
428 /* FIXME: this should respect TPR */
429 svm_check_intercept(SVM_EXIT_VINTR);
db620f46 430 intno = ldl_phys(env->vm_vmcb + offsetof(struct vmcb, control.int_vector));
93fcfe39 431 qemu_log_mask(CPU_LOG_TB_IN_ASM, "Servicing virtual hardware INT=0x%02x\n", intno);
db620f46 432 do_interrupt(intno, 0, 0, 0, 1);
d40c54d6 433 env->interrupt_request &= ~CPU_INTERRUPT_VIRQ;
db620f46 434 next_tb = 0;
907a5b26 435#endif
db620f46 436 }
68a79315 437 }
ce09776b 438#elif defined(TARGET_PPC)
9fddaa0c
FB		 439#if 0
440 if ((interrupt_request & CPU_INTERRUPT_RESET)) {
d84bda46 441 cpu_reset(env);
9fddaa0c
FB		 442 }
443#endif
47103572 444 if (interrupt_request & CPU_INTERRUPT_HARD) {
e9df014c
JM		 445 ppc_hw_interrupt(env);
446 if (env->pending_interrupts == 0)
447 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
b5fc09ae 448 next_tb = 0;
ce09776b 449 }
81ea0e13
MW		 450#elif defined(TARGET_LM32)
451 if ((interrupt_request & CPU_INTERRUPT_HARD)
452 && (env->ie & IE_IE)) {
453 env->exception_index = EXCP_IRQ;
454 do_interrupt(env);
455 next_tb = 0;
456 }
b779e29e
EI		 457#elif defined(TARGET_MICROBLAZE)
458 if ((interrupt_request & CPU_INTERRUPT_HARD)
459 && (env->sregs[SR_MSR] & MSR_IE)
460 && !(env->sregs[SR_MSR] & (MSR_EIP | MSR_BIP))
461 && !(env->iflags & (D_FLAG | IMM_FLAG))) {
462 env->exception_index = EXCP_IRQ;
463 do_interrupt(env);
464 next_tb = 0;
465 }
6af0bf9c
FB		 466#elif defined(TARGET_MIPS)
467 if ((interrupt_request & CPU_INTERRUPT_HARD) &&
4cdc1cd1 468 cpu_mips_hw_interrupts_pending(env)) {
6af0bf9c
FB		 469 /* Raise it */
470 env->exception_index = EXCP_EXT_INTERRUPT;
471 env->error_code = 0;
472 do_interrupt(env);
b5fc09ae 473 next_tb = 0;
6af0bf9c 474 }
e95c8d51 475#elif defined(TARGET_SPARC)
d532b26c
IK		 476 if (interrupt_request & CPU_INTERRUPT_HARD) {
477 if (cpu_interrupts_enabled(env) &&
478 env->interrupt_index > 0) {
479 int pil = env->interrupt_index & 0xf;
480 int type = env->interrupt_index & 0xf0;
481
482 if (((type == TT_EXTINT) &&
483 cpu_pil_allowed(env, pil)) ||
484 type != TT_EXTINT) {
485 env->exception_index = env->interrupt_index;
486 do_interrupt(env);
487 next_tb = 0;
488 }
489 }
e95c8d51
FB		 490 } else if (interrupt_request & CPU_INTERRUPT_TIMER) {
491 //do_interrupt(0, 0, 0, 0, 0);
492 env->interrupt_request &= ~CPU_INTERRUPT_TIMER;
a90b7318 493 }
b5ff1b31
FB		 494#elif defined(TARGET_ARM)
495 if (interrupt_request & CPU_INTERRUPT_FIQ
496 && !(env->uncached_cpsr & CPSR_F)) {
497 env->exception_index = EXCP_FIQ;
498 do_interrupt(env);
b5fc09ae 499 next_tb = 0;
b5ff1b31 500 }
9ee6e8bb
PB		 501 /* ARMv7-M interrupt return works by loading a magic value
502 into the PC. On real hardware the load causes the
503 return to occur. The qemu implementation performs the
504 jump normally, then does the exception return when the
505 CPU tries to execute code at the magic address.
506 This will cause the magic PC value to be pushed to
507 the stack if an interrupt occured at the wrong time.
508 We avoid this by disabling interrupts when
509 pc contains a magic address. */
b5ff1b31 510 if (interrupt_request & CPU_INTERRUPT_HARD
9ee6e8bb
PB		 511 && ((IS_M(env) && env->regs[15] < 0xfffffff0)
512 || !(env->uncached_cpsr & CPSR_I))) {
b5ff1b31
FB		 513 env->exception_index = EXCP_IRQ;
514 do_interrupt(env);
b5fc09ae 515 next_tb = 0;
b5ff1b31 516 }
fdf9b3e8 517#elif defined(TARGET_SH4)
e96e2044
TS		 518 if (interrupt_request & CPU_INTERRUPT_HARD) {
519 do_interrupt(env);
b5fc09ae 520 next_tb = 0;
e96e2044 521 }
eddf68a6
JM		 522#elif defined(TARGET_ALPHA)
523 if (interrupt_request & CPU_INTERRUPT_HARD) {
524 do_interrupt(env);
b5fc09ae 525 next_tb = 0;
eddf68a6 526 }
f1ccf904 527#elif defined(TARGET_CRIS)
1b1a38b0 528 if (interrupt_request & CPU_INTERRUPT_HARD
fb9fb692
EI		 529 && (env->pregs[PR_CCS] & I_FLAG)
530 && !env->locked_irq) {
1b1a38b0
EI		 531 env->exception_index = EXCP_IRQ;
532 do_interrupt(env);
533 next_tb = 0;
534 }
535 if (interrupt_request & CPU_INTERRUPT_NMI
536 && (env->pregs[PR_CCS] & M_FLAG)) {
537 env->exception_index = EXCP_NMI;
f1ccf904 538 do_interrupt(env);
b5fc09ae 539 next_tb = 0;
f1ccf904 540 }
0633879f
PB		 541#elif defined(TARGET_M68K)
542 if (interrupt_request & CPU_INTERRUPT_HARD
543 && ((env->sr & SR_I) >> SR_I_SHIFT)
544 < env->pending_level) {
545 /* Real hardware gets the interrupt vector via an
546 IACK cycle at this point. Current emulated
547 hardware doesn't rely on this, so we
548 provide/save the vector when the interrupt is
549 first signalled. */
550 env->exception_index = env->pending_vector;
551 do_interrupt(1);
b5fc09ae 552 next_tb = 0;
0633879f 553 }
68a79315 554#endif
9d05095e
FB		 555 /* Don't use the cached interupt_request value,
556 do_interrupt may have updated the EXITTB flag. */
b5ff1b31 557 if (env->interrupt_request & CPU_INTERRUPT_EXITTB) {
bf3e8bf1
FB		 558 env->interrupt_request &= ~CPU_INTERRUPT_EXITTB;
559 /* ensure that no TB jump will be modified as
560 the program flow was changed */
b5fc09ae 561 next_tb = 0;
bf3e8bf1 562 }
be214e6c
AJ		 563 }
564 if (unlikely(env->exit_request)) {
565 env->exit_request = 0;
566 env->exception_index = EXCP_INTERRUPT;
567 cpu_loop_exit();
3fb2ded1 568 }
a73b1fd9 569#if defined(DEBUG_DISAS) || defined(CONFIG_DEBUG_EXEC)
8fec2b8c 570 if (qemu_loglevel_mask(CPU_LOG_TB_CPU)) {
3fb2ded1 571 /* restore flags in standard format */
ecb644f4 572#if defined(TARGET_I386)
a7812ae4 573 env->eflags = env->eflags | helper_cc_compute_all(CC_OP) | (DF & DF_MASK);
93fcfe39 574 log_cpu_state(env, X86_DUMP_CCOP);
3fb2ded1 575 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
e6e5906b
PB		 576#elif defined(TARGET_M68K)
577 cpu_m68k_flush_flags(env, env->cc_op);
578 env->cc_op = CC_OP_FLAGS;
579 env->sr = (env->sr & 0xffe0)
580 | env->cc_dest | (env->cc_x << 4);
93fcfe39 581 log_cpu_state(env, 0);
e4533c7a 582#else
a73b1fd9 583 log_cpu_state(env, 0);
e4533c7a 584#endif
3fb2ded1 585 }
a73b1fd9 586#endif /* DEBUG_DISAS || CONFIG_DEBUG_EXEC */
d5975363 587 spin_lock(&tb_lock);
8a40a180 588 tb = tb_find_fast();
d5975363
PB		 589 /* Note: we do it here to avoid a gcc bug on Mac OS X when
590 doing it in tb_find_slow */
591 if (tb_invalidated_flag) {
592 /* as some TB could have been invalidated because
593 of memory exceptions while generating the code, we
594 must recompute the hash index here */
595 next_tb = 0;
2e70f6ef 596 tb_invalidated_flag = 0;
d5975363 597 }
f0667e66 598#ifdef CONFIG_DEBUG_EXEC
93fcfe39
AL		 599 qemu_log_mask(CPU_LOG_EXEC, "Trace 0x%08lx [" TARGET_FMT_lx "] %s\n",
600 (long)tb->tc_ptr, tb->pc,
601 lookup_symbol(tb->pc));
9d27abd9 602#endif
8a40a180
FB		 603 /* see if we can patch the calling TB. When the TB
604 spans two pages, we cannot safely do a direct
605 jump. */
040f2fb2 606 if (next_tb != 0 && tb->page_addr[1] == -1) {
b5fc09ae 607 tb_add_jump((TranslationBlock *)(next_tb & ~3), next_tb & 3, tb);
3fb2ded1 608 }
d5975363 609 spin_unlock(&tb_lock);
55e8b85e 610
611 /* cpu_interrupt might be called while translating the
612 TB, but before it is linked into a potentially
613 infinite loop and becomes env->current_tb. Avoid
614 starting execution if there is a pending interrupt. */
b0052d15
JK		 615 env->current_tb = tb;
616 barrier();
617 if (likely(!env->exit_request)) {
2e70f6ef 618 tc_ptr = tb->tc_ptr;
3fb2ded1 619 /* execute the generated code */
dfe5fff3 620#if defined(__sparc__) && !defined(CONFIG_SOLARIS)
572a9d4a 621#undef env
2e70f6ef 622 env = cpu_single_env;
572a9d4a
BS		 623#define env cpu_single_env
624#endif
2e70f6ef 625 next_tb = tcg_qemu_tb_exec(tc_ptr);
2e70f6ef 626 if ((next_tb & 3) == 2) {
bf20dc07 627 /* Instruction counter expired. */
2e70f6ef
PB		 628 int insns_left;
629 tb = (TranslationBlock *)(long)(next_tb & ~3);
630 /* Restore PC. */
622ed360 631 cpu_pc_from_tb(env, tb);
2e70f6ef
PB		 632 insns_left = env->icount_decr.u32;
633 if (env->icount_extra && insns_left >= 0) {
634 /* Refill decrementer and continue execution. */
635 env->icount_extra += insns_left;
636 if (env->icount_extra > 0xffff) {
637 insns_left = 0xffff;
638 } else {
639 insns_left = env->icount_extra;
640 }
641 env->icount_extra -= insns_left;
642 env->icount_decr.u16.low = insns_left;
643 } else {
644 if (insns_left > 0) {
645 /* Execute remaining instructions. */
646 cpu_exec_nocache(insns_left, tb);
647 }
648 env->exception_index = EXCP_INTERRUPT;
649 next_tb = 0;
650 cpu_loop_exit();
651 }
652 }
653 }
b0052d15 654 env->current_tb = NULL;
4cbf74b6
FB		 655 /* reset soft MMU for next block (it can currently
656 only be set by a memory fault) */
50a518e3 657 } /* for(;;) */
7d13299d 658 }
3fb2ded1
FB		 659 } /* for(;;) */
660
7d13299d 661
e4533c7a 662#if defined(TARGET_I386)
9de5e440 663 /* restore flags in standard format */
a7812ae4 664 env->eflags = env->eflags | helper_cc_compute_all(CC_OP) | (DF & DF_MASK);
e4533c7a 665#elif defined(TARGET_ARM)
b7bcbe95 666 /* XXX: Save/restore host fpu exception state?. */
93ac68bc 667#elif defined(TARGET_SPARC)
67867308 668#elif defined(TARGET_PPC)
81ea0e13 669#elif defined(TARGET_LM32)
e6e5906b
PB		 670#elif defined(TARGET_M68K)
671 cpu_m68k_flush_flags(env, env->cc_op);
672 env->cc_op = CC_OP_FLAGS;
673 env->sr = (env->sr & 0xffe0)
674 | env->cc_dest | (env->cc_x << 4);
b779e29e 675#elif defined(TARGET_MICROBLAZE)
6af0bf9c 676#elif defined(TARGET_MIPS)
fdf9b3e8 677#elif defined(TARGET_SH4)
eddf68a6 678#elif defined(TARGET_ALPHA)
f1ccf904 679#elif defined(TARGET_CRIS)
10ec5117 680#elif defined(TARGET_S390X)
fdf9b3e8 681 /* XXXXX */
e4533c7a
FB		 682#else
683#error unsupported target CPU
684#endif
1057eaa7
PB		 685
686 /* restore global registers */
1d93f0f0 687 barrier();
24ebf5f3 688 env = (void *) saved_env_reg;
1057eaa7 689
6a00d601 690 /* fail safe : never use cpu_single_env outside cpu_exec() */
5fafdf24 691 cpu_single_env = NULL;
7d13299d
FB		 692 return ret;
693}
6dbad63e 694
fbf9eeb3
FB		 695/* must only be called from the generated code as an exception can be
696 generated */
697void tb_invalidate_page_range(target_ulong start, target_ulong end)
698{
dc5d0b3d
FB		 699 /* XXX: cannot enable it yet because it yields to MMU exception
700 where NIP != read address on PowerPC */
701#if 0
fbf9eeb3
FB		 702 target_ulong phys_addr;
703 phys_addr = get_phys_addr_code(env, start);
704 tb_invalidate_phys_page_range(phys_addr, phys_addr + end - start, 0);
dc5d0b3d 705#endif
fbf9eeb3
FB		 706}
707
1a18c71b 708#if defined(TARGET_I386) && defined(CONFIG_USER_ONLY)
e4533c7a 709
6dbad63e
FB		 710void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector)
711{
712 CPUX86State *saved_env;
713
714 saved_env = env;
715 env = s;
a412ac57 716 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) {
a513fe19 717 selector &= 0xffff;
5fafdf24 718 cpu_x86_load_seg_cache(env, seg_reg, selector,
c27004ec 719 (selector << 4), 0xffff, 0);
a513fe19 720 } else {
5d97559d 721 helper_load_seg(seg_reg, selector);
a513fe19 722 }
6dbad63e
FB		 723 env = saved_env;
724}
9de5e440 725
6f12a2a6 726void cpu_x86_fsave(CPUX86State *s, target_ulong ptr, int data32)
d0a1ffc9
FB		 727{
728 CPUX86State *saved_env;
729
730 saved_env = env;
731 env = s;
3b46e624 732
6f12a2a6 733 helper_fsave(ptr, data32);
d0a1ffc9
FB		 734
735 env = saved_env;
736}
737
6f12a2a6 738void cpu_x86_frstor(CPUX86State *s, target_ulong ptr, int data32)
d0a1ffc9
FB		 739{
740 CPUX86State *saved_env;
741
742 saved_env = env;
743 env = s;
3b46e624 744
6f12a2a6 745 helper_frstor(ptr, data32);
d0a1ffc9
FB		 746
747 env = saved_env;
748}
749
e4533c7a
FB		 750#endif /* TARGET_I386 */
751
67b915a5
FB		 752#if !defined(CONFIG_SOFTMMU)
753
3fb2ded1 754#if defined(TARGET_I386)
0b5c1ce8
NF		 755#define EXCEPTION_ACTION raise_exception_err(env->exception_index, env->error_code)
756#else
757#define EXCEPTION_ACTION cpu_loop_exit()
758#endif
3fb2ded1 759
b56dad1c 760/* 'pc' is the host PC at which the exception was raised. 'address' is
fd6ce8f6
FB		 761 the effective address of the memory exception. 'is_write' is 1 if a
762 write caused the exception and otherwise 0'. 'old_set' is the
763 signal set which should be restored */
2b413144 764static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
5fafdf24 765 int is_write, sigset_t *old_set,
bf3e8bf1 766 void *puc)
9de5e440 767{
a513fe19
FB		 768 TranslationBlock *tb;
769 int ret;
68a79315 770
83479e77
FB		 771 if (cpu_single_env)
772 env = cpu_single_env; /* XXX: find a correct solution for multithread */
fd6ce8f6 773#if defined(DEBUG_SIGNAL)
5fafdf24 774 qemu_printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
bf3e8bf1 775 pc, address, is_write, *(unsigned long *)old_set);
9de5e440 776#endif
25eb4484 777 /* XXX: locking issue */
53a5960a 778 if (is_write && page_unprotect(h2g(address), pc, puc)) {
fd6ce8f6
FB		 779 return 1;
780 }
fbf9eeb3 781
3fb2ded1 782 /* see if it is an MMU fault */
0b5c1ce8 783 ret = cpu_handle_mmu_fault(env, address, is_write, MMU_USER_IDX, 0);
68016c62
FB		 784 if (ret < 0)
785 return 0; /* not an MMU fault */
786 if (ret == 0)
787 return 1; /* the MMU fault was handled without causing real CPU fault */
788 /* now we have a real cpu fault */
789 tb = tb_find_pc(pc);
790 if (tb) {
791 /* the PC is inside the translated code. It means that we have
792 a virtual CPU fault */
793 cpu_restore_state(tb, env, pc, puc);
794 }
68016c62 795
68016c62
FB		 796 /* we restore the process signal mask as the sigreturn should
797 do it (XXX: use sigsetjmp) */
798 sigprocmask(SIG_SETMASK, old_set, NULL);
0b5c1ce8 799 EXCEPTION_ACTION;
e6e5906b 800
e6e5906b 801 /* never comes here */
67867308
FB		 802 return 1;
803}
6af0bf9c 804
2b413144
FB		 805#if defined(__i386__)
806
d8ecc0b9
FB		 807#if defined(__APPLE__)
808# include <sys/ucontext.h>
809
810# define EIP_sig(context) (*((unsigned long*)&(context)->uc_mcontext->ss.eip))
811# define TRAP_sig(context) ((context)->uc_mcontext->es.trapno)
812# define ERROR_sig(context) ((context)->uc_mcontext->es.err)
d39bb24a 813# define MASK_sig(context) ((context)->uc_sigmask)
78cfb07f
JL		 814#elif defined (__NetBSD__)
815# include <ucontext.h>
816
817# define EIP_sig(context) ((context)->uc_mcontext.__gregs[_REG_EIP])
818# define TRAP_sig(context) ((context)->uc_mcontext.__gregs[_REG_TRAPNO])
819# define ERROR_sig(context) ((context)->uc_mcontext.__gregs[_REG_ERR])
820# define MASK_sig(context) ((context)->uc_sigmask)
821#elif defined (__FreeBSD__) || defined(__DragonFly__)
822# include <ucontext.h>
823
824# define EIP_sig(context) (*((unsigned long*)&(context)->uc_mcontext.mc_eip))
825# define TRAP_sig(context) ((context)->uc_mcontext.mc_trapno)
826# define ERROR_sig(context) ((context)->uc_mcontext.mc_err)
827# define MASK_sig(context) ((context)->uc_sigmask)
d39bb24a
BS		 828#elif defined(__OpenBSD__)
829# define EIP_sig(context) ((context)->sc_eip)
830# define TRAP_sig(context) ((context)->sc_trapno)
831# define ERROR_sig(context) ((context)->sc_err)
832# define MASK_sig(context) ((context)->sc_mask)
d8ecc0b9
FB		 833#else
834# define EIP_sig(context) ((context)->uc_mcontext.gregs[REG_EIP])
835# define TRAP_sig(context) ((context)->uc_mcontext.gregs[REG_TRAPNO])
836# define ERROR_sig(context) ((context)->uc_mcontext.gregs[REG_ERR])
d39bb24a 837# define MASK_sig(context) ((context)->uc_sigmask)
d8ecc0b9
FB		 838#endif
839
5fafdf24 840int cpu_signal_handler(int host_signum, void *pinfo,
e4533c7a 841 void *puc)
9de5e440 842{
5a7b542b 843 siginfo_t *info = pinfo;
78cfb07f
JL		 844#if defined(__NetBSD__) || defined (__FreeBSD__) || defined(__DragonFly__)
845 ucontext_t *uc = puc;
846#elif defined(__OpenBSD__)
d39bb24a
BS		 847 struct sigcontext *uc = puc;
848#else
9de5e440 849 struct ucontext *uc = puc;
d39bb24a 850#endif
9de5e440 851 unsigned long pc;
bf3e8bf1 852 int trapno;
97eb5b14 853
d691f669
FB		 854#ifndef REG_EIP
855/* for glibc 2.1 */
fd6ce8f6
FB		 856#define REG_EIP EIP
857#define REG_ERR ERR
858#define REG_TRAPNO TRAPNO
d691f669 859#endif
d8ecc0b9
FB		 860 pc = EIP_sig(uc);
861 trapno = TRAP_sig(uc);
ec6338ba
FB		 862 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
863 trapno == 0xe ?
864 (ERROR_sig(uc) >> 1) & 1 : 0,
d39bb24a 865 &MASK_sig(uc), puc);
2b413144
FB		 866}
867
bc51c5c9
FB		 868#elif defined(__x86_64__)
869
b3efe5c8 870#ifdef __NetBSD__
d397abbd
BS		 871#define PC_sig(context) _UC_MACHINE_PC(context)
872#define TRAP_sig(context) ((context)->uc_mcontext.__gregs[_REG_TRAPNO])
873#define ERROR_sig(context) ((context)->uc_mcontext.__gregs[_REG_ERR])
874#define MASK_sig(context) ((context)->uc_sigmask)
875#elif defined(__OpenBSD__)
876#define PC_sig(context) ((context)->sc_rip)
877#define TRAP_sig(context) ((context)->sc_trapno)
878#define ERROR_sig(context) ((context)->sc_err)
879#define MASK_sig(context) ((context)->sc_mask)
78cfb07f
JL		 880#elif defined (__FreeBSD__) || defined(__DragonFly__)
881#include <ucontext.h>
882
883#define PC_sig(context) (*((unsigned long*)&(context)->uc_mcontext.mc_rip))
884#define TRAP_sig(context) ((context)->uc_mcontext.mc_trapno)
885#define ERROR_sig(context) ((context)->uc_mcontext.mc_err)
886#define MASK_sig(context) ((context)->uc_sigmask)
b3efe5c8 887#else
d397abbd
BS		 888#define PC_sig(context) ((context)->uc_mcontext.gregs[REG_RIP])
889#define TRAP_sig(context) ((context)->uc_mcontext.gregs[REG_TRAPNO])
890#define ERROR_sig(context) ((context)->uc_mcontext.gregs[REG_ERR])
891#define MASK_sig(context) ((context)->uc_sigmask)
b3efe5c8
BS		 892#endif
893
5a7b542b 894int cpu_signal_handler(int host_signum, void *pinfo,
bc51c5c9
FB		 895 void *puc)
896{
5a7b542b 897 siginfo_t *info = pinfo;
bc51c5c9 898 unsigned long pc;
78cfb07f 899#if defined(__NetBSD__) || defined (__FreeBSD__) || defined(__DragonFly__)
b3efe5c8 900 ucontext_t *uc = puc;
d397abbd
BS		 901#elif defined(__OpenBSD__)
902 struct sigcontext *uc = puc;
b3efe5c8
BS		 903#else
904 struct ucontext *uc = puc;
905#endif
bc51c5c9 906
d397abbd 907 pc = PC_sig(uc);
5fafdf24 908 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
d397abbd
BS		 909 TRAP_sig(uc) == 0xe ?
910 (ERROR_sig(uc) >> 1) & 1 : 0,
911 &MASK_sig(uc), puc);
bc51c5c9
FB		 912}
913
e58ffeb3 914#elif defined(_ARCH_PPC)
2b413144 915
83fb7adf
FB		 916/***********************************************************************
917 * signal context platform-specific definitions
918 * From Wine
919 */
920#ifdef linux
921/* All Registers access - only for local access */
922# define REG_sig(reg_name, context) ((context)->uc_mcontext.regs->reg_name)
923/* Gpr Registers access */
924# define GPR_sig(reg_num, context) REG_sig(gpr[reg_num], context)
925# define IAR_sig(context) REG_sig(nip, context) /* Program counter */
926# define MSR_sig(context) REG_sig(msr, context) /* Machine State Register (Supervisor) */
927# define CTR_sig(context) REG_sig(ctr, context) /* Count register */
928# define XER_sig(context) REG_sig(xer, context) /* User's integer exception register */
929# define LR_sig(context) REG_sig(link, context) /* Link register */
930# define CR_sig(context) REG_sig(ccr, context) /* Condition register */
931/* Float Registers access */
932# define FLOAT_sig(reg_num, context) (((double*)((char*)((context)->uc_mcontext.regs+48*4)))[reg_num])
933# define FPSCR_sig(context) (*(int*)((char*)((context)->uc_mcontext.regs+(48+32*2)*4)))
934/* Exception Registers access */
935# define DAR_sig(context) REG_sig(dar, context)
936# define DSISR_sig(context) REG_sig(dsisr, context)
937# define TRAP_sig(context) REG_sig(trap, context)
938#endif /* linux */
939
58d9b1e0
JL		 940#if defined(__FreeBSD__) || defined(__FreeBSD_kernel__)
941#include <ucontext.h>
942# define IAR_sig(context) ((context)->uc_mcontext.mc_srr0)
943# define MSR_sig(context) ((context)->uc_mcontext.mc_srr1)
944# define CTR_sig(context) ((context)->uc_mcontext.mc_ctr)
945# define XER_sig(context) ((context)->uc_mcontext.mc_xer)
946# define LR_sig(context) ((context)->uc_mcontext.mc_lr)
947# define CR_sig(context) ((context)->uc_mcontext.mc_cr)
948/* Exception Registers access */
949# define DAR_sig(context) ((context)->uc_mcontext.mc_dar)
950# define DSISR_sig(context) ((context)->uc_mcontext.mc_dsisr)
951# define TRAP_sig(context) ((context)->uc_mcontext.mc_exc)
952#endif /* __FreeBSD__|| __FreeBSD_kernel__ */
953
83fb7adf
FB		 954#ifdef __APPLE__
955# include <sys/ucontext.h>
956typedef struct ucontext SIGCONTEXT;
957/* All Registers access - only for local access */
958# define REG_sig(reg_name, context) ((context)->uc_mcontext->ss.reg_name)
959# define FLOATREG_sig(reg_name, context) ((context)->uc_mcontext->fs.reg_name)
960# define EXCEPREG_sig(reg_name, context) ((context)->uc_mcontext->es.reg_name)
961# define VECREG_sig(reg_name, context) ((context)->uc_mcontext->vs.reg_name)
962/* Gpr Registers access */
963# define GPR_sig(reg_num, context) REG_sig(r##reg_num, context)
964# define IAR_sig(context) REG_sig(srr0, context) /* Program counter */
965# define MSR_sig(context) REG_sig(srr1, context) /* Machine State Register (Supervisor) */
966# define CTR_sig(context) REG_sig(ctr, context)
967# define XER_sig(context) REG_sig(xer, context) /* Link register */
968# define LR_sig(context) REG_sig(lr, context) /* User's integer exception register */
969# define CR_sig(context) REG_sig(cr, context) /* Condition register */
970/* Float Registers access */
971# define FLOAT_sig(reg_num, context) FLOATREG_sig(fpregs[reg_num], context)
972# define FPSCR_sig(context) ((double)FLOATREG_sig(fpscr, context))
973/* Exception Registers access */
974# define DAR_sig(context) EXCEPREG_sig(dar, context) /* Fault registers for coredump */
975# define DSISR_sig(context) EXCEPREG_sig(dsisr, context)
976# define TRAP_sig(context) EXCEPREG_sig(exception, context) /* number of powerpc exception taken */
977#endif /* __APPLE__ */
978
5fafdf24 979int cpu_signal_handler(int host_signum, void *pinfo,
e4533c7a 980 void *puc)
2b413144 981{
5a7b542b 982 siginfo_t *info = pinfo;
58d9b1e0
JL		 983#if defined(__FreeBSD__) || defined(__FreeBSD_kernel__)
984 ucontext_t *uc = puc;
985#else
25eb4484 986 struct ucontext *uc = puc;
58d9b1e0 987#endif
25eb4484 988 unsigned long pc;
25eb4484
FB		 989 int is_write;
990
83fb7adf 991 pc = IAR_sig(uc);
25eb4484
FB		 992 is_write = 0;
993#if 0
994 /* ppc 4xx case */
83fb7adf 995 if (DSISR_sig(uc) & 0x00800000)
25eb4484
FB		 996 is_write = 1;
997#else
83fb7adf 998 if (TRAP_sig(uc) != 0x400 && (DSISR_sig(uc) & 0x02000000))
25eb4484
FB		 999 is_write = 1;
1000#endif
5fafdf24 1001 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
bf3e8bf1 1002 is_write, &uc->uc_sigmask, puc);
2b413144
FB		 1003}
1004
2f87c607
FB		 1005#elif defined(__alpha__)
1006
5fafdf24 1007int cpu_signal_handler(int host_signum, void *pinfo,
2f87c607
FB		 1008 void *puc)
1009{
5a7b542b 1010 siginfo_t *info = pinfo;
2f87c607
FB		 1011 struct ucontext *uc = puc;
1012 uint32_t *pc = uc->uc_mcontext.sc_pc;
1013 uint32_t insn = *pc;
1014 int is_write = 0;
1015
8c6939c0 1016 /* XXX: need kernel patch to get write flag faster */
2f87c607
FB		 1017 switch (insn >> 26) {
1018 case 0x0d: // stw
1019 case 0x0e: // stb
1020 case 0x0f: // stq_u
1021 case 0x24: // stf
1022 case 0x25: // stg
1023 case 0x26: // sts
1024 case 0x27: // stt
1025 case 0x2c: // stl
1026 case 0x2d: // stq
1027 case 0x2e: // stl_c
1028 case 0x2f: // stq_c
1029 is_write = 1;
1030 }
1031
5fafdf24 1032 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
bf3e8bf1 1033 is_write, &uc->uc_sigmask, puc);
2f87c607 1034}
8c6939c0
FB		 1035#elif defined(__sparc__)
1036
5fafdf24 1037int cpu_signal_handler(int host_signum, void *pinfo,
e4533c7a 1038 void *puc)
8c6939c0 1039{
5a7b542b 1040 siginfo_t *info = pinfo;
8c6939c0
FB		 1041 int is_write;
1042 uint32_t insn;
dfe5fff3 1043#if !defined(__arch64__) || defined(CONFIG_SOLARIS)
c9e1e2b0
BS		 1044 uint32_t *regs = (uint32_t *)(info + 1);
1045 void *sigmask = (regs + 20);
8c6939c0 1046 /* XXX: is there a standard glibc define ? */
c9e1e2b0
BS		 1047 unsigned long pc = regs[1];
1048#else
84778508 1049#ifdef __linux__
c9e1e2b0
BS		 1050 struct sigcontext *sc = puc;
1051 unsigned long pc = sc->sigc_regs.tpc;
1052 void *sigmask = (void *)sc->sigc_mask;
84778508
BS		 1053#elif defined(__OpenBSD__)
1054 struct sigcontext *uc = puc;
1055 unsigned long pc = uc->sc_pc;
1056 void *sigmask = (void *)(long)uc->sc_mask;
1057#endif
c9e1e2b0
BS		 1058#endif
1059
8c6939c0
FB		 1060 /* XXX: need kernel patch to get write flag faster */
1061 is_write = 0;
1062 insn = *(uint32_t *)pc;
1063 if ((insn >> 30) == 3) {
1064 switch((insn >> 19) & 0x3f) {
1065 case 0x05: // stb
d877fa5a 1066 case 0x15: // stba
8c6939c0 1067 case 0x06: // sth
d877fa5a 1068 case 0x16: // stha
8c6939c0 1069 case 0x04: // st
d877fa5a 1070 case 0x14: // sta
8c6939c0 1071 case 0x07: // std
d877fa5a
BS		 1072 case 0x17: // stda
1073 case 0x0e: // stx
1074 case 0x1e: // stxa
8c6939c0 1075 case 0x24: // stf
d877fa5a 1076 case 0x34: // stfa
8c6939c0 1077 case 0x27: // stdf
d877fa5a
BS		 1078 case 0x37: // stdfa
1079 case 0x26: // stqf
1080 case 0x36: // stqfa
8c6939c0 1081 case 0x25: // stfsr
d877fa5a
BS		 1082 case 0x3c: // casa
1083 case 0x3e: // casxa
8c6939c0
FB		 1084 is_write = 1;
1085 break;
1086 }
1087 }
5fafdf24 1088 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
bf3e8bf1 1089 is_write, sigmask, NULL);
8c6939c0
FB		 1090}
1091
1092#elif defined(__arm__)
1093
5fafdf24 1094int cpu_signal_handler(int host_signum, void *pinfo,
e4533c7a 1095 void *puc)
8c6939c0 1096{
5a7b542b 1097 siginfo_t *info = pinfo;
8c6939c0
FB		 1098 struct ucontext *uc = puc;
1099 unsigned long pc;
1100 int is_write;
3b46e624 1101
48bbf11b 1102#if (__GLIBC__ < 2 || (__GLIBC__ == 2 && __GLIBC_MINOR__ <= 3))
5c49b363
AZ		 1103 pc = uc->uc_mcontext.gregs[R15];
1104#else
4eee57f5 1105 pc = uc->uc_mcontext.arm_pc;
5c49b363 1106#endif
8c6939c0
FB		 1107 /* XXX: compute is_write */
1108 is_write = 0;
5fafdf24 1109 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
8c6939c0 1110 is_write,
f3a9676a 1111 &uc->uc_sigmask, puc);
8c6939c0
FB		 1112}
1113
38e584a0
FB		 1114#elif defined(__mc68000)
1115
5fafdf24 1116int cpu_signal_handler(int host_signum, void *pinfo,
38e584a0
FB		 1117 void *puc)
1118{
5a7b542b 1119 siginfo_t *info = pinfo;
38e584a0
FB		 1120 struct ucontext *uc = puc;
1121 unsigned long pc;
1122 int is_write;
3b46e624 1123
38e584a0
FB		 1124 pc = uc->uc_mcontext.gregs[16];
1125 /* XXX: compute is_write */
1126 is_write = 0;
5fafdf24 1127 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
38e584a0 1128 is_write,
bf3e8bf1 1129 &uc->uc_sigmask, puc);
38e584a0
FB		 1130}
1131
b8076a74
FB		 1132#elif defined(__ia64)
1133
1134#ifndef __ISR_VALID
1135 /* This ought to be in <bits/siginfo.h>... */
1136# define __ISR_VALID 1
b8076a74
FB		 1137#endif
1138
5a7b542b 1139int cpu_signal_handler(int host_signum, void *pinfo, void *puc)
b8076a74 1140{
5a7b542b 1141 siginfo_t *info = pinfo;
b8076a74
FB		 1142 struct ucontext *uc = puc;
1143 unsigned long ip;
1144 int is_write = 0;
1145
1146 ip = uc->uc_mcontext.sc_ip;
1147 switch (host_signum) {
1148 case SIGILL:
1149 case SIGFPE:
1150 case SIGSEGV:
1151 case SIGBUS:
1152 case SIGTRAP:
fd4a43e4 1153 if (info->si_code && (info->si_segvflags & __ISR_VALID))
b8076a74
FB		 1154 /* ISR.W (write-access) is bit 33: */
1155 is_write = (info->si_isr >> 33) & 1;
1156 break;
1157
1158 default:
1159 break;
1160 }
1161 return handle_cpu_signal(ip, (unsigned long)info->si_addr,
1162 is_write,
60e99246 1163 (sigset_t *)&uc->uc_sigmask, puc);
b8076a74
FB		 1164}
1165
90cb9493
FB		 1166#elif defined(__s390__)
1167
5fafdf24 1168int cpu_signal_handler(int host_signum, void *pinfo,
90cb9493
FB		 1169 void *puc)
1170{
5a7b542b 1171 siginfo_t *info = pinfo;
90cb9493
FB		 1172 struct ucontext *uc = puc;
1173 unsigned long pc;
6a1621b9
RH		 1174 uint16_t *pinsn;
1175 int is_write = 0;
3b46e624 1176
90cb9493 1177 pc = uc->uc_mcontext.psw.addr;
6a1621b9
RH		 1178
1179 /* ??? On linux, the non-rt signal handler has 4 (!) arguments instead
1180 of the normal 2 arguments. The 3rd argument contains the "int_code"
1181 from the hardware which does in fact contain the is_write value.
1182 The rt signal handler, as far as I can tell, does not give this value
1183 at all. Not that we could get to it from here even if it were. */
1184 /* ??? This is not even close to complete, since it ignores all
1185 of the read-modify-write instructions. */
1186 pinsn = (uint16_t *)pc;
1187 switch (pinsn[0] >> 8) {
1188 case 0x50: /* ST */
1189 case 0x42: /* STC */
1190 case 0x40: /* STH */
1191 is_write = 1;
1192 break;
1193 case 0xc4: /* RIL format insns */
1194 switch (pinsn[0] & 0xf) {
1195 case 0xf: /* STRL */
1196 case 0xb: /* STGRL */
1197 case 0x7: /* STHRL */
1198 is_write = 1;
1199 }
1200 break;
1201 case 0xe3: /* RXY format insns */
1202 switch (pinsn[2] & 0xff) {
1203 case 0x50: /* STY */
1204 case 0x24: /* STG */
1205 case 0x72: /* STCY */
1206 case 0x70: /* STHY */
1207 case 0x8e: /* STPQ */
1208 case 0x3f: /* STRVH */
1209 case 0x3e: /* STRV */
1210 case 0x2f: /* STRVG */
1211 is_write = 1;
1212 }
1213 break;
1214 }
5fafdf24 1215 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
c4b89d18
TS		 1216 is_write, &uc->uc_sigmask, puc);
1217}
1218
1219#elif defined(__mips__)
1220
5fafdf24 1221int cpu_signal_handler(int host_signum, void *pinfo,
c4b89d18
TS		 1222 void *puc)
1223{
9617efe8 1224 siginfo_t *info = pinfo;
c4b89d18
TS		 1225 struct ucontext *uc = puc;
1226 greg_t pc = uc->uc_mcontext.pc;
1227 int is_write;
3b46e624 1228
c4b89d18
TS		 1229 /* XXX: compute is_write */
1230 is_write = 0;
5fafdf24 1231 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
c4b89d18 1232 is_write, &uc->uc_sigmask, puc);
90cb9493
FB		 1233}
1234
f54b3f92
AJ		 1235#elif defined(__hppa__)
1236
1237int cpu_signal_handler(int host_signum, void *pinfo,
1238 void *puc)
1239{
1240 struct siginfo *info = pinfo;
1241 struct ucontext *uc = puc;
f57040be
RH		 1242 unsigned long pc = uc->uc_mcontext.sc_iaoq[0];
1243 uint32_t insn = *(uint32_t *)pc;
1244 int is_write = 0;
1245
1246 /* XXX: need kernel patch to get write flag faster. */
1247 switch (insn >> 26) {
1248 case 0x1a: /* STW */
1249 case 0x19: /* STH */
1250 case 0x18: /* STB */
1251 case 0x1b: /* STWM */
1252 is_write = 1;
1253 break;
1254
1255 case 0x09: /* CSTWX, FSTWX, FSTWS */
1256 case 0x0b: /* CSTDX, FSTDX, FSTDS */
1257 /* Distinguish from coprocessor load ... */
1258 is_write = (insn >> 9) & 1;
1259 break;
1260
1261 case 0x03:
1262 switch ((insn >> 6) & 15) {
1263 case 0xa: /* STWS */
1264 case 0x9: /* STHS */
1265 case 0x8: /* STBS */
1266 case 0xe: /* STWAS */
1267 case 0xc: /* STBYS */
1268 is_write = 1;
1269 }
1270 break;
1271 }
f54b3f92 1272
f54b3f92 1273 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
f57040be 1274 is_write, &uc->uc_sigmask, puc);
f54b3f92
AJ		 1275}
1276
9de5e440 1277#else
2b413144 1278
3fb2ded1 1279#error host CPU specific signal handler needed
2b413144 1280
9de5e440 1281#endif
67b915a5
FB		 1282
1283#endif /* !defined(CONFIG_SOFTMMU) */
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