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c3d2689d
AZ		 1/*
2 * TI OMAP processors emulation.
3 *
b4e3104b 4 * Copyright (C) 2006-2008 Andrzej Zaborowski <[email protected]>
c3d2689d
AZ		 5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
827df9f3
AZ		 8 * published by the Free Software Foundation; either version 2 or
9 * (at your option) version 3 of the License.
c3d2689d
AZ		 10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
fad6cb1a 16 * You should have received a copy of the GNU General Public License along
8167ee88 17 * with this program; if not, see <http://www.gnu.org/licenses/>.
c3d2689d 18 */
c8623c02 19
12b16722 20#include "qemu/osdep.h"
c0dbca36 21#include "qemu/error-report.h"
db725815 22#include "qemu/main-loop.h"
da34e65c 23#include "qapi/error.h"
4771d756
PB		 24#include "qemu-common.h"
25#include "cpu.h"
4387b253 26#include "exec/address-spaces.h"
c8623c02 27#include "hw/boards.h"
83c9f4ca 28#include "hw/hw.h"
64552b6b 29#include "hw/irq.h"
a27bd6c7 30#include "hw/qdev-properties.h"
12ec8bd5 31#include "hw/arm/boot.h"
0d09e41a 32#include "hw/arm/omap.h"
12e9493d 33#include "sysemu/blockdev.h"
9c17d615 34#include "sysemu/sysemu.h"
0d09e41a 35#include "hw/arm/soc_dma.h"
a82929a2 36#include "sysemu/qtest.h"
71e8a915 37#include "sysemu/reset.h"
54d31236 38#include "sysemu/runstate.h"
1de7afc9 39#include "qemu/range.h"
83c9f4ca 40#include "hw/sysbus.h"
f348b6d1
VB		 41#include "qemu/cutils.h"
42#include "qemu/bcd.h"
c3d2689d 43
415202d4
PMD		 44static inline void omap_log_badwidth(const char *funcname, hwaddr addr, int sz)
45{
46 qemu_log_mask(LOG_GUEST_ERROR, "%s: %d-bit register %#08" HWADDR_PRIx "\n",
47 funcname, 8 * sz, addr);
48}
49
827df9f3 50/* Should signal the TCMI/GPMC */
a8170e5e 51uint32_t omap_badwidth_read8(void *opaque, hwaddr addr)
66450b15 52{
02645926
AZ		 53 uint8_t ret;
54
415202d4 55 omap_log_badwidth(__func__, addr, 1);
e1fe50dc 56 cpu_physical_memory_read(addr, &ret, 1);
02645926 57 return ret;
66450b15
AZ		 58}
59
a8170e5e 60void omap_badwidth_write8(void *opaque, hwaddr addr,
66450b15
AZ		 61 uint32_t value)
62{
b854bc19
AZ		 63 uint8_t val8 = value;
64
415202d4 65 omap_log_badwidth(__func__, addr, 1);
e1fe50dc 66 cpu_physical_memory_write(addr, &val8, 1);
66450b15
AZ		 67}
68
a8170e5e 69uint32_t omap_badwidth_read16(void *opaque, hwaddr addr)
c3d2689d 70{
b854bc19
AZ		 71 uint16_t ret;
72
415202d4 73 omap_log_badwidth(__func__, addr, 2);
e1fe50dc 74 cpu_physical_memory_read(addr, &ret, 2);
b854bc19 75 return ret;
c3d2689d
AZ		 76}
77
a8170e5e 78void omap_badwidth_write16(void *opaque, hwaddr addr,
c3d2689d
AZ		 79 uint32_t value)
80{
b854bc19
AZ		 81 uint16_t val16 = value;
82
415202d4 83 omap_log_badwidth(__func__, addr, 2);
e1fe50dc 84 cpu_physical_memory_write(addr, &val16, 2);
c3d2689d
AZ		 85}
86
a8170e5e 87uint32_t omap_badwidth_read32(void *opaque, hwaddr addr)
c3d2689d 88{
b854bc19
AZ		 89 uint32_t ret;
90
415202d4 91 omap_log_badwidth(__func__, addr, 4);
e1fe50dc 92 cpu_physical_memory_read(addr, &ret, 4);
b854bc19 93 return ret;
c3d2689d
AZ		 94}
95
a8170e5e 96void omap_badwidth_write32(void *opaque, hwaddr addr,
c3d2689d
AZ		 97 uint32_t value)
98{
415202d4 99 omap_log_badwidth(__func__, addr, 4);
e1fe50dc 100 cpu_physical_memory_write(addr, &value, 4);
c3d2689d
AZ		 101}
102
c3d2689d
AZ		 103/* MPU OS timers */
104struct omap_mpu_timer_s {
4b3fedf3 105 MemoryRegion iomem;
c3d2689d
AZ		 106 qemu_irq irq;
107 omap_clk clk;
c3d2689d
AZ		 108 uint32_t val;
109 int64_t time;
110 QEMUTimer *timer;
e856f2ad 111 QEMUBH *tick;
c3d2689d
AZ		 112 int64_t rate;
113 int it_ena;
114
115 int enable;
116 int ptv;
117 int ar;
118 int st;
119 uint32_t reset_val;
120};
121
122static inline uint32_t omap_timer_read(struct omap_mpu_timer_s *timer)
123{
bc72ad67 124 uint64_t distance = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - timer->time;
c3d2689d
AZ		 125
126 if (timer->st && timer->enable && timer->rate)
127 return timer->val - muldiv64(distance >> (timer->ptv + 1),
73bcb24d 128 timer->rate, NANOSECONDS_PER_SECOND);
c3d2689d
AZ		 129 else
130 return timer->val;
131}
132
133static inline void omap_timer_sync(struct omap_mpu_timer_s *timer)
134{
135 timer->val = omap_timer_read(timer);
bc72ad67 136 timer->time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
c3d2689d
AZ		 137}
138
139static inline void omap_timer_update(struct omap_mpu_timer_s *timer)
140{
141 int64_t expires;
142
143 if (timer->enable && timer->st && timer->rate) {
144 timer->val = timer->reset_val; /* Should skip this on clk enable */
b8b137d6 145 expires = muldiv64((uint64_t) timer->val << (timer->ptv + 1),
73bcb24d 146 NANOSECONDS_PER_SECOND, timer->rate);
b854bc19
AZ		 147
148 /* If timer expiry would be sooner than in about 1 ms and
149 * auto-reload isn't set, then fire immediately. This is a hack
150 * to make systems like PalmOS run in acceptable time. PalmOS
151 * sets the interval to a very low value and polls the status bit
152 * in a busy loop when it wants to sleep just a couple of CPU
153 * ticks. */
73bcb24d 154 if (expires > (NANOSECONDS_PER_SECOND >> 10) || timer->ar) {
bc72ad67 155 timer_mod(timer->timer, timer->time + expires);
73bcb24d 156 } else {
e856f2ad 157 qemu_bh_schedule(timer->tick);
73bcb24d 158 }
c3d2689d 159 } else
bc72ad67 160 timer_del(timer->timer);
c3d2689d
AZ		 161}
162
e856f2ad 163static void omap_timer_fire(void *opaque)
c3d2689d 164{
e856f2ad 165 struct omap_mpu_timer_s *timer = opaque;
c3d2689d
AZ		 166
167 if (!timer->ar) {
168 timer->val = 0;
169 timer->st = 0;
170 }
171
172 if (timer->it_ena)
106627d0
AZ		 173 /* Edge-triggered irq */
174 qemu_irq_pulse(timer->irq);
e856f2ad
AZ		 175}
176
177static void omap_timer_tick(void *opaque)
178{
179 struct omap_mpu_timer_s *timer = (struct omap_mpu_timer_s *) opaque;
180
181 omap_timer_sync(timer);
182 omap_timer_fire(timer);
c3d2689d
AZ		 183 omap_timer_update(timer);
184}
185
186static void omap_timer_clk_update(void *opaque, int line, int on)
187{
188 struct omap_mpu_timer_s *timer = (struct omap_mpu_timer_s *) opaque;
189
190 omap_timer_sync(timer);
191 timer->rate = on ? omap_clk_getrate(timer->clk) : 0;
192 omap_timer_update(timer);
193}
194
195static void omap_timer_clk_setup(struct omap_mpu_timer_s *timer)
196{
197 omap_clk_adduser(timer->clk,
f3c7d038 198 qemu_allocate_irq(omap_timer_clk_update, timer, 0));
c3d2689d
AZ		 199 timer->rate = omap_clk_getrate(timer->clk);
200}
201
a8170e5e 202static uint64_t omap_mpu_timer_read(void *opaque, hwaddr addr,
4b3fedf3 203 unsigned size)
c3d2689d
AZ		 204{
205 struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *) opaque;
c3d2689d 206
4b3fedf3
AK		 207 if (size != 4) {
208 return omap_badwidth_read32(opaque, addr);
209 }
210
8da3ff18 211 switch (addr) {
c3d2689d
AZ		 212 case 0x00: /* CNTL_TIMER */
213 return (s->enable << 5) | (s->ptv << 2) | (s->ar << 1) | s->st;
214
215 case 0x04: /* LOAD_TIM */
216 break;
217
218 case 0x08: /* READ_TIM */
219 return omap_timer_read(s);
220 }
221
222 OMAP_BAD_REG(addr);
223 return 0;
224}
225
a8170e5e 226static void omap_mpu_timer_write(void *opaque, hwaddr addr,
4b3fedf3 227 uint64_t value, unsigned size)
c3d2689d
AZ		 228{
229 struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *) opaque;
c3d2689d 230
4b3fedf3 231 if (size != 4) {
77a8257e
SW		 232 omap_badwidth_write32(opaque, addr, value);
233 return;
4b3fedf3
AK		 234 }
235
8da3ff18 236 switch (addr) {
c3d2689d
AZ		 237 case 0x00: /* CNTL_TIMER */
238 omap_timer_sync(s);
239 s->enable = (value >> 5) & 1;
240 s->ptv = (value >> 2) & 7;
241 s->ar = (value >> 1) & 1;
242 s->st = value & 1;
243 omap_timer_update(s);
244 return;
245
246 case 0x04: /* LOAD_TIM */
247 s->reset_val = value;
248 return;
249
250 case 0x08: /* READ_TIM */
251 OMAP_RO_REG(addr);
252 break;
253
254 default:
255 OMAP_BAD_REG(addr);
256 }
257}
258
4b3fedf3
AK		 259static const MemoryRegionOps omap_mpu_timer_ops = {
260 .read = omap_mpu_timer_read,
261 .write = omap_mpu_timer_write,
262 .endianness = DEVICE_LITTLE_ENDIAN,
c3d2689d
AZ		 263};
264
265static void omap_mpu_timer_reset(struct omap_mpu_timer_s *s)
266{
bc72ad67 267 timer_del(s->timer);
c3d2689d
AZ		 268 s->enable = 0;
269 s->reset_val = 31337;
270 s->val = 0;
271 s->ptv = 0;
272 s->ar = 0;
273 s->st = 0;
274 s->it_ena = 1;
275}
276
4b3fedf3 277static struct omap_mpu_timer_s *omap_mpu_timer_init(MemoryRegion *system_memory,
a8170e5e 278 hwaddr base,
c3d2689d
AZ		 279 qemu_irq irq, omap_clk clk)
280{
b45c03f5 281 struct omap_mpu_timer_s *s = g_new0(struct omap_mpu_timer_s, 1);
c3d2689d
AZ		 282
283 s->irq = irq;
284 s->clk = clk;
bc72ad67 285 s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, omap_timer_tick, s);
e856f2ad 286 s->tick = qemu_bh_new(omap_timer_fire, s);
c3d2689d
AZ		 287 omap_mpu_timer_reset(s);
288 omap_timer_clk_setup(s);
289
2c9b15ca 290 memory_region_init_io(&s->iomem, NULL, &omap_mpu_timer_ops, s,
4b3fedf3
AK		 291 "omap-mpu-timer", 0x100);
292
293 memory_region_add_subregion(system_memory, base, &s->iomem);
c3d2689d
AZ		 294
295 return s;
296}
297
298/* Watchdog timer */
299struct omap_watchdog_timer_s {
300 struct omap_mpu_timer_s timer;
4b3fedf3 301 MemoryRegion iomem;
c3d2689d
AZ		 302 uint8_t last_wr;
303 int mode;
304 int free;
305 int reset;
306};
307
a8170e5e 308static uint64_t omap_wd_timer_read(void *opaque, hwaddr addr,
4b3fedf3 309 unsigned size)
c3d2689d
AZ		 310{
311 struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *) opaque;
c3d2689d 312
4b3fedf3
AK		 313 if (size != 2) {
314 return omap_badwidth_read16(opaque, addr);
315 }
316
8da3ff18 317 switch (addr) {
c3d2689d
AZ		 318 case 0x00: /* CNTL_TIMER */
319 return (s->timer.ptv << 9) | (s->timer.ar << 8) |
320 (s->timer.st << 7) | (s->free << 1);
321
322 case 0x04: /* READ_TIMER */
323 return omap_timer_read(&s->timer);
324
325 case 0x08: /* TIMER_MODE */
326 return s->mode << 15;
327 }
328
329 OMAP_BAD_REG(addr);
330 return 0;
331}
332
a8170e5e 333static void omap_wd_timer_write(void *opaque, hwaddr addr,
4b3fedf3 334 uint64_t value, unsigned size)
c3d2689d
AZ		 335{
336 struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *) opaque;
c3d2689d 337
4b3fedf3 338 if (size != 2) {
77a8257e
SW		 339 omap_badwidth_write16(opaque, addr, value);
340 return;
4b3fedf3
AK		 341 }
342
8da3ff18 343 switch (addr) {
c3d2689d
AZ		 344 case 0x00: /* CNTL_TIMER */
345 omap_timer_sync(&s->timer);
346 s->timer.ptv = (value >> 9) & 7;
347 s->timer.ar = (value >> 8) & 1;
348 s->timer.st = (value >> 7) & 1;
349 s->free = (value >> 1) & 1;
350 omap_timer_update(&s->timer);
351 break;
352
353 case 0x04: /* LOAD_TIMER */
354 s->timer.reset_val = value & 0xffff;
355 break;
356
357 case 0x08: /* TIMER_MODE */
358 if (!s->mode && ((value >> 15) & 1))
359 omap_clk_get(s->timer.clk);
360 s->mode |= (value >> 15) & 1;
361 if (s->last_wr == 0xf5) {
362 if ((value & 0xff) == 0xa0) {
d8f699cb
AZ		 363 if (s->mode) {
364 s->mode = 0;
365 omap_clk_put(s->timer.clk);
366 }
c3d2689d
AZ		 367 } else {
368 /* XXX: on T|E hardware somehow this has no effect,
369 * on Zire 71 it works as specified. */
370 s->reset = 1;
cf83f140 371 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
c3d2689d
AZ		 372 }
373 }
374 s->last_wr = value & 0xff;
375 break;
376
377 default:
378 OMAP_BAD_REG(addr);
379 }
380}
381
4b3fedf3
AK		 382static const MemoryRegionOps omap_wd_timer_ops = {
383 .read = omap_wd_timer_read,
384 .write = omap_wd_timer_write,
385 .endianness = DEVICE_NATIVE_ENDIAN,
c3d2689d
AZ		 386};
387
388static void omap_wd_timer_reset(struct omap_watchdog_timer_s *s)
389{
bc72ad67 390 timer_del(s->timer.timer);
c3d2689d
AZ		 391 if (!s->mode)
392 omap_clk_get(s->timer.clk);
393 s->mode = 1;
394 s->free = 1;
395 s->reset = 0;
396 s->timer.enable = 1;
397 s->timer.it_ena = 1;
398 s->timer.reset_val = 0xffff;
399 s->timer.val = 0;
400 s->timer.st = 0;
401 s->timer.ptv = 0;
402 s->timer.ar = 0;
403 omap_timer_update(&s->timer);
404}
405
4b3fedf3 406static struct omap_watchdog_timer_s *omap_wd_timer_init(MemoryRegion *memory,
a8170e5e 407 hwaddr base,
c3d2689d
AZ		 408 qemu_irq irq, omap_clk clk)
409{
b45c03f5 410 struct omap_watchdog_timer_s *s = g_new0(struct omap_watchdog_timer_s, 1);
c3d2689d
AZ		 411
412 s->timer.irq = irq;
413 s->timer.clk = clk;
bc72ad67 414 s->timer.timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, omap_timer_tick, &s->timer);
c3d2689d
AZ		 415 omap_wd_timer_reset(s);
416 omap_timer_clk_setup(&s->timer);
417
2c9b15ca 418 memory_region_init_io(&s->iomem, NULL, &omap_wd_timer_ops, s,
4b3fedf3
AK		 419 "omap-wd-timer", 0x100);
420 memory_region_add_subregion(memory, base, &s->iomem);
c3d2689d
AZ		 421
422 return s;
423}
424
425/* 32-kHz timer */
426struct omap_32khz_timer_s {
427 struct omap_mpu_timer_s timer;
4b3fedf3 428 MemoryRegion iomem;
c3d2689d
AZ		 429};
430
a8170e5e 431static uint64_t omap_os_timer_read(void *opaque, hwaddr addr,
4b3fedf3 432 unsigned size)
c3d2689d
AZ		 433{
434 struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *) opaque;
cf965d24 435 int offset = addr & OMAP_MPUI_REG_MASK;
c3d2689d 436
4b3fedf3
AK		 437 if (size != 4) {
438 return omap_badwidth_read32(opaque, addr);
439 }
440
c3d2689d
AZ		 441 switch (offset) {
442 case 0x00: /* TVR */
443 return s->timer.reset_val;
444
445 case 0x04: /* TCR */
446 return omap_timer_read(&s->timer);
447
448 case 0x08: /* CR */
449 return (s->timer.ar << 3) | (s->timer.it_ena << 2) | s->timer.st;
450
451 default:
452 break;
453 }
454 OMAP_BAD_REG(addr);
455 return 0;
456}
457
a8170e5e 458static void omap_os_timer_write(void *opaque, hwaddr addr,
4b3fedf3 459 uint64_t value, unsigned size)
c3d2689d
AZ		 460{
461 struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *) opaque;
cf965d24 462 int offset = addr & OMAP_MPUI_REG_MASK;
c3d2689d 463
4b3fedf3 464 if (size != 4) {
77a8257e
SW		 465 omap_badwidth_write32(opaque, addr, value);
466 return;
4b3fedf3
AK		 467 }
468
c3d2689d
AZ		 469 switch (offset) {
470 case 0x00: /* TVR */
471 s->timer.reset_val = value & 0x00ffffff;
472 break;
473
474 case 0x04: /* TCR */
475 OMAP_RO_REG(addr);
476 break;
477
478 case 0x08: /* CR */
479 s->timer.ar = (value >> 3) & 1;
480 s->timer.it_ena = (value >> 2) & 1;
481 if (s->timer.st != (value & 1) || (value & 2)) {
482 omap_timer_sync(&s->timer);
483 s->timer.enable = value & 1;
484 s->timer.st = value & 1;
485 omap_timer_update(&s->timer);
486 }
487 break;
488
489 default:
490 OMAP_BAD_REG(addr);
491 }
492}
493
4b3fedf3
AK		 494static const MemoryRegionOps omap_os_timer_ops = {
495 .read = omap_os_timer_read,
496 .write = omap_os_timer_write,
497 .endianness = DEVICE_NATIVE_ENDIAN,
c3d2689d
AZ		 498};
499
500static void omap_os_timer_reset(struct omap_32khz_timer_s *s)
501{
bc72ad67 502 timer_del(s->timer.timer);
c3d2689d
AZ		 503 s->timer.enable = 0;
504 s->timer.it_ena = 0;
505 s->timer.reset_val = 0x00ffffff;
506 s->timer.val = 0;
507 s->timer.st = 0;
508 s->timer.ptv = 0;
509 s->timer.ar = 1;
510}
511
4b3fedf3 512static struct omap_32khz_timer_s *omap_os_timer_init(MemoryRegion *memory,
a8170e5e 513 hwaddr base,
c3d2689d
AZ		 514 qemu_irq irq, omap_clk clk)
515{
b45c03f5 516 struct omap_32khz_timer_s *s = g_new0(struct omap_32khz_timer_s, 1);
c3d2689d
AZ		 517
518 s->timer.irq = irq;
519 s->timer.clk = clk;
bc72ad67 520 s->timer.timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, omap_timer_tick, &s->timer);
c3d2689d
AZ		 521 omap_os_timer_reset(s);
522 omap_timer_clk_setup(&s->timer);
523
2c9b15ca 524 memory_region_init_io(&s->iomem, NULL, &omap_os_timer_ops, s,
4b3fedf3
AK		 525 "omap-os-timer", 0x800);
526 memory_region_add_subregion(memory, base, &s->iomem);
c3d2689d
AZ		 527
528 return s;
529}
530
531/* Ultra Low-Power Device Module */
a8170e5e 532static uint64_t omap_ulpd_pm_read(void *opaque, hwaddr addr,
4b3fedf3 533 unsigned size)
c3d2689d
AZ		 534{
535 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
c3d2689d
AZ		 536 uint16_t ret;
537
4b3fedf3
AK		 538 if (size != 2) {
539 return omap_badwidth_read16(opaque, addr);
540 }
541
8da3ff18 542 switch (addr) {
c3d2689d 543 case 0x14: /* IT_STATUS */
8da3ff18
PB		 544 ret = s->ulpd_pm_regs[addr >> 2];
545 s->ulpd_pm_regs[addr >> 2] = 0;
0919ac78 546 qemu_irq_lower(qdev_get_gpio_in(s->ih[1], OMAP_INT_GAUGE_32K));
c3d2689d
AZ		 547 return ret;
548
549 case 0x18: /* Reserved */
550 case 0x1c: /* Reserved */
551 case 0x20: /* Reserved */
552 case 0x28: /* Reserved */
553 case 0x2c: /* Reserved */
554 OMAP_BAD_REG(addr);
139bd956 555 /* fall through */
c3d2689d
AZ		 556 case 0x00: /* COUNTER_32_LSB */
557 case 0x04: /* COUNTER_32_MSB */
558 case 0x08: /* COUNTER_HIGH_FREQ_LSB */
559 case 0x0c: /* COUNTER_HIGH_FREQ_MSB */
560 case 0x10: /* GAUGING_CTRL */
561 case 0x24: /* SETUP_ANALOG_CELL3_ULPD1 */
562 case 0x30: /* CLOCK_CTRL */
563 case 0x34: /* SOFT_REQ */
564 case 0x38: /* COUNTER_32_FIQ */
565 case 0x3c: /* DPLL_CTRL */
566 case 0x40: /* STATUS_REQ */
567 /* XXX: check clk::usecount state for every clock */
568 case 0x48: /* LOCL_TIME */
569 case 0x4c: /* APLL_CTRL */
570 case 0x50: /* POWER_CTRL */
8da3ff18 571 return s->ulpd_pm_regs[addr >> 2];
c3d2689d
AZ		 572 }
573
574 OMAP_BAD_REG(addr);
575 return 0;
576}
577
578static inline void omap_ulpd_clk_update(struct omap_mpu_state_s *s,
579 uint16_t diff, uint16_t value)
580{
581 if (diff & (1 << 4)) /* USB_MCLK_EN */
582 omap_clk_onoff(omap_findclk(s, "usb_clk0"), (value >> 4) & 1);
583 if (diff & (1 << 5)) /* DIS_USB_PVCI_CLK */
584 omap_clk_onoff(omap_findclk(s, "usb_w2fc_ck"), (~value >> 5) & 1);
585}
586
587static inline void omap_ulpd_req_update(struct omap_mpu_state_s *s,
588 uint16_t diff, uint16_t value)
589{
590 if (diff & (1 << 0)) /* SOFT_DPLL_REQ */
591 omap_clk_canidle(omap_findclk(s, "dpll4"), (~value >> 0) & 1);
592 if (diff & (1 << 1)) /* SOFT_COM_REQ */
593 omap_clk_canidle(omap_findclk(s, "com_mclk_out"), (~value >> 1) & 1);
594 if (diff & (1 << 2)) /* SOFT_SDW_REQ */
595 omap_clk_canidle(omap_findclk(s, "bt_mclk_out"), (~value >> 2) & 1);
596 if (diff & (1 << 3)) /* SOFT_USB_REQ */
597 omap_clk_canidle(omap_findclk(s, "usb_clk0"), (~value >> 3) & 1);
598}
599
a8170e5e 600static void omap_ulpd_pm_write(void *opaque, hwaddr addr,
4b3fedf3 601 uint64_t value, unsigned size)
c3d2689d
AZ		 602{
603 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
c3d2689d
AZ		 604 int64_t now, ticks;
605 int div, mult;
606 static const int bypass_div[4] = { 1, 2, 4, 4 };
607 uint16_t diff;
608
4b3fedf3 609 if (size != 2) {
77a8257e
SW		 610 omap_badwidth_write16(opaque, addr, value);
611 return;
4b3fedf3
AK		 612 }
613
8da3ff18 614 switch (addr) {
c3d2689d
AZ		 615 case 0x00: /* COUNTER_32_LSB */
616 case 0x04: /* COUNTER_32_MSB */
617 case 0x08: /* COUNTER_HIGH_FREQ_LSB */
618 case 0x0c: /* COUNTER_HIGH_FREQ_MSB */
619 case 0x14: /* IT_STATUS */
620 case 0x40: /* STATUS_REQ */
621 OMAP_RO_REG(addr);
622 break;
623
624 case 0x10: /* GAUGING_CTRL */
625 /* Bits 0 and 1 seem to be confused in the OMAP 310 TRM */
8da3ff18 626 if ((s->ulpd_pm_regs[addr >> 2] ^ value) & 1) {
bc72ad67 627 now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
c3d2689d
AZ		 628
629 if (value & 1)
630 s->ulpd_gauge_start = now;
631 else {
632 now -= s->ulpd_gauge_start;
633
634 /* 32-kHz ticks */
73bcb24d 635 ticks = muldiv64(now, 32768, NANOSECONDS_PER_SECOND);
c3d2689d
AZ		 636 s->ulpd_pm_regs[0x00 >> 2] = (ticks >> 0) & 0xffff;
637 s->ulpd_pm_regs[0x04 >> 2] = (ticks >> 16) & 0xffff;
638 if (ticks >> 32) /* OVERFLOW_32K */
639 s->ulpd_pm_regs[0x14 >> 2] |= 1 << 2;
640
641 /* High frequency ticks */
73bcb24d 642 ticks = muldiv64(now, 12000000, NANOSECONDS_PER_SECOND);
c3d2689d
AZ		 643 s->ulpd_pm_regs[0x08 >> 2] = (ticks >> 0) & 0xffff;
644 s->ulpd_pm_regs[0x0c >> 2] = (ticks >> 16) & 0xffff;
645 if (ticks >> 32) /* OVERFLOW_HI_FREQ */
646 s->ulpd_pm_regs[0x14 >> 2] |= 1 << 1;
647
648 s->ulpd_pm_regs[0x14 >> 2] |= 1 << 0; /* IT_GAUGING */
0919ac78 649 qemu_irq_raise(qdev_get_gpio_in(s->ih[1], OMAP_INT_GAUGE_32K));
c3d2689d
AZ		 650 }
651 }
8da3ff18 652 s->ulpd_pm_regs[addr >> 2] = value;
c3d2689d
AZ		 653 break;
654
655 case 0x18: /* Reserved */
656 case 0x1c: /* Reserved */
657 case 0x20: /* Reserved */
658 case 0x28: /* Reserved */
659 case 0x2c: /* Reserved */
660 OMAP_BAD_REG(addr);
139bd956 661 /* fall through */
c3d2689d
AZ		 662 case 0x24: /* SETUP_ANALOG_CELL3_ULPD1 */
663 case 0x38: /* COUNTER_32_FIQ */
664 case 0x48: /* LOCL_TIME */
665 case 0x50: /* POWER_CTRL */
8da3ff18 666 s->ulpd_pm_regs[addr >> 2] = value;
c3d2689d
AZ		 667 break;
668
669 case 0x30: /* CLOCK_CTRL */
8da3ff18
PB		 670 diff = s->ulpd_pm_regs[addr >> 2] ^ value;
671 s->ulpd_pm_regs[addr >> 2] = value & 0x3f;
c3d2689d
AZ		 672 omap_ulpd_clk_update(s, diff, value);
673 break;
674
675 case 0x34: /* SOFT_REQ */
8da3ff18
PB		 676 diff = s->ulpd_pm_regs[addr >> 2] ^ value;
677 s->ulpd_pm_regs[addr >> 2] = value & 0x1f;
c3d2689d
AZ		 678 omap_ulpd_req_update(s, diff, value);
679 break;
680
681 case 0x3c: /* DPLL_CTRL */
682 /* XXX: OMAP310 TRM claims bit 3 is PLL_ENABLE, and bit 4 is
683 * omitted altogether, probably a typo. */
684 /* This register has identical semantics with DPLL(1:3) control
685 * registers, see omap_dpll_write() */
8da3ff18
PB		 686 diff = s->ulpd_pm_regs[addr >> 2] & value;
687 s->ulpd_pm_regs[addr >> 2] = value & 0x2fff;
c3d2689d
AZ		 688 if (diff & (0x3ff << 2)) {
689 if (value & (1 << 4)) { /* PLL_ENABLE */
690 div = ((value >> 5) & 3) + 1; /* PLL_DIV */
691 mult = MIN((value >> 7) & 0x1f, 1); /* PLL_MULT */
692 } else {
693 div = bypass_div[((value >> 2) & 3)]; /* BYPASS_DIV */
694 mult = 1;
695 }
696 omap_clk_setrate(omap_findclk(s, "dpll4"), div, mult);
697 }
698
699 /* Enter the desired mode. */
8da3ff18
PB		 700 s->ulpd_pm_regs[addr >> 2] =
701 (s->ulpd_pm_regs[addr >> 2] & 0xfffe) |
702 ((s->ulpd_pm_regs[addr >> 2] >> 4) & 1);
c3d2689d
AZ		 703
704 /* Act as if the lock is restored. */
8da3ff18 705 s->ulpd_pm_regs[addr >> 2] |= 2;
c3d2689d
AZ		 706 break;
707
708 case 0x4c: /* APLL_CTRL */
8da3ff18
PB		 709 diff = s->ulpd_pm_regs[addr >> 2] & value;
710 s->ulpd_pm_regs[addr >> 2] = value & 0xf;
c3d2689d
AZ		 711 if (diff & (1 << 0)) /* APLL_NDPLL_SWITCH */
712 omap_clk_reparent(omap_findclk(s, "ck_48m"), omap_findclk(s,
713 (value & (1 << 0)) ? "apll" : "dpll4"));
714 break;
715
716 default:
717 OMAP_BAD_REG(addr);
718 }
719}
720
4b3fedf3
AK		 721static const MemoryRegionOps omap_ulpd_pm_ops = {
722 .read = omap_ulpd_pm_read,
723 .write = omap_ulpd_pm_write,
724 .endianness = DEVICE_NATIVE_ENDIAN,
c3d2689d
AZ		 725};
726
727static void omap_ulpd_pm_reset(struct omap_mpu_state_s *mpu)
728{
729 mpu->ulpd_pm_regs[0x00 >> 2] = 0x0001;
730 mpu->ulpd_pm_regs[0x04 >> 2] = 0x0000;
731 mpu->ulpd_pm_regs[0x08 >> 2] = 0x0001;
732 mpu->ulpd_pm_regs[0x0c >> 2] = 0x0000;
733 mpu->ulpd_pm_regs[0x10 >> 2] = 0x0000;
734 mpu->ulpd_pm_regs[0x18 >> 2] = 0x01;
735 mpu->ulpd_pm_regs[0x1c >> 2] = 0x01;
736 mpu->ulpd_pm_regs[0x20 >> 2] = 0x01;
737 mpu->ulpd_pm_regs[0x24 >> 2] = 0x03ff;
738 mpu->ulpd_pm_regs[0x28 >> 2] = 0x01;
739 mpu->ulpd_pm_regs[0x2c >> 2] = 0x01;
740 omap_ulpd_clk_update(mpu, mpu->ulpd_pm_regs[0x30 >> 2], 0x0000);
741 mpu->ulpd_pm_regs[0x30 >> 2] = 0x0000;
742 omap_ulpd_req_update(mpu, mpu->ulpd_pm_regs[0x34 >> 2], 0x0000);
743 mpu->ulpd_pm_regs[0x34 >> 2] = 0x0000;
744 mpu->ulpd_pm_regs[0x38 >> 2] = 0x0001;
745 mpu->ulpd_pm_regs[0x3c >> 2] = 0x2211;
746 mpu->ulpd_pm_regs[0x40 >> 2] = 0x0000; /* FIXME: dump a real STATUS_REQ */
747 mpu->ulpd_pm_regs[0x48 >> 2] = 0x960;
748 mpu->ulpd_pm_regs[0x4c >> 2] = 0x08;
749 mpu->ulpd_pm_regs[0x50 >> 2] = 0x08;
750 omap_clk_setrate(omap_findclk(mpu, "dpll4"), 1, 4);
751 omap_clk_reparent(omap_findclk(mpu, "ck_48m"), omap_findclk(mpu, "dpll4"));
752}
753
4b3fedf3 754static void omap_ulpd_pm_init(MemoryRegion *system_memory,
a8170e5e 755 hwaddr base,
c3d2689d
AZ		 756 struct omap_mpu_state_s *mpu)
757{
2c9b15ca 758 memory_region_init_io(&mpu->ulpd_pm_iomem, NULL, &omap_ulpd_pm_ops, mpu,
4b3fedf3
AK		 759 "omap-ulpd-pm", 0x800);
760 memory_region_add_subregion(system_memory, base, &mpu->ulpd_pm_iomem);
c3d2689d
AZ		 761 omap_ulpd_pm_reset(mpu);
762}
763
764/* OMAP Pin Configuration */
a8170e5e 765static uint64_t omap_pin_cfg_read(void *opaque, hwaddr addr,
4b3fedf3 766 unsigned size)
c3d2689d
AZ		 767{
768 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
c3d2689d 769
4b3fedf3
AK		 770 if (size != 4) {
771 return omap_badwidth_read32(opaque, addr);
772 }
773
8da3ff18 774 switch (addr) {
c3d2689d
AZ		 775 case 0x00: /* FUNC_MUX_CTRL_0 */
776 case 0x04: /* FUNC_MUX_CTRL_1 */
777 case 0x08: /* FUNC_MUX_CTRL_2 */
8da3ff18 778 return s->func_mux_ctrl[addr >> 2];
c3d2689d
AZ		 779
780 case 0x0c: /* COMP_MODE_CTRL_0 */
781 return s->comp_mode_ctrl[0];
782
783 case 0x10: /* FUNC_MUX_CTRL_3 */
784 case 0x14: /* FUNC_MUX_CTRL_4 */
785 case 0x18: /* FUNC_MUX_CTRL_5 */
786 case 0x1c: /* FUNC_MUX_CTRL_6 */
787 case 0x20: /* FUNC_MUX_CTRL_7 */
788 case 0x24: /* FUNC_MUX_CTRL_8 */
789 case 0x28: /* FUNC_MUX_CTRL_9 */
790 case 0x2c: /* FUNC_MUX_CTRL_A */
791 case 0x30: /* FUNC_MUX_CTRL_B */
792 case 0x34: /* FUNC_MUX_CTRL_C */
793 case 0x38: /* FUNC_MUX_CTRL_D */
8da3ff18 794 return s->func_mux_ctrl[(addr >> 2) - 1];
c3d2689d
AZ		 795
796 case 0x40: /* PULL_DWN_CTRL_0 */
797 case 0x44: /* PULL_DWN_CTRL_1 */
798 case 0x48: /* PULL_DWN_CTRL_2 */
799 case 0x4c: /* PULL_DWN_CTRL_3 */
8da3ff18 800 return s->pull_dwn_ctrl[(addr & 0xf) >> 2];
c3d2689d
AZ		 801
802 case 0x50: /* GATE_INH_CTRL_0 */
803 return s->gate_inh_ctrl[0];
804
805 case 0x60: /* VOLTAGE_CTRL_0 */
806 return s->voltage_ctrl[0];
807
808 case 0x70: /* TEST_DBG_CTRL_0 */
809 return s->test_dbg_ctrl[0];
810
811 case 0x80: /* MOD_CONF_CTRL_0 */
812 return s->mod_conf_ctrl[0];
813 }
814
815 OMAP_BAD_REG(addr);
816 return 0;
817}
818
819static inline void omap_pin_funcmux0_update(struct omap_mpu_state_s *s,
820 uint32_t diff, uint32_t value)
821{
822 if (s->compat1509) {
823 if (diff & (1 << 9)) /* BLUETOOTH */
824 omap_clk_onoff(omap_findclk(s, "bt_mclk_out"),
825 (~value >> 9) & 1);
826 if (diff & (1 << 7)) /* USB.CLKO */
827 omap_clk_onoff(omap_findclk(s, "usb.clko"),
828 (value >> 7) & 1);
829 }
830}
831
832static inline void omap_pin_funcmux1_update(struct omap_mpu_state_s *s,
833 uint32_t diff, uint32_t value)
834{
835 if (s->compat1509) {
d2f41a11
PM		 836 if (diff & (1U << 31)) {
837 /* MCBSP3_CLK_HIZ_DI */
838 omap_clk_onoff(omap_findclk(s, "mcbsp3.clkx"), (value >> 31) & 1);
839 }
840 if (diff & (1 << 1)) {
841 /* CLK32K */
842 omap_clk_onoff(omap_findclk(s, "clk32k_out"), (~value >> 1) & 1);
843 }
c3d2689d
AZ		 844 }
845}
846
847static inline void omap_pin_modconf1_update(struct omap_mpu_state_s *s,
848 uint32_t diff, uint32_t value)
849{
d2f41a11
PM		 850 if (diff & (1U << 31)) {
851 /* CONF_MOD_UART3_CLK_MODE_R */
852 omap_clk_reparent(omap_findclk(s, "uart3_ck"),
853 omap_findclk(s, ((value >> 31) & 1) ?
854 "ck_48m" : "armper_ck"));
855 }
c3d2689d
AZ		 856 if (diff & (1 << 30)) /* CONF_MOD_UART2_CLK_MODE_R */
857 omap_clk_reparent(omap_findclk(s, "uart2_ck"),
858 omap_findclk(s, ((value >> 30) & 1) ?
859 "ck_48m" : "armper_ck"));
860 if (diff & (1 << 29)) /* CONF_MOD_UART1_CLK_MODE_R */
861 omap_clk_reparent(omap_findclk(s, "uart1_ck"),
862 omap_findclk(s, ((value >> 29) & 1) ?
863 "ck_48m" : "armper_ck"));
864 if (diff & (1 << 23)) /* CONF_MOD_MMC_SD_CLK_REQ_R */
865 omap_clk_reparent(omap_findclk(s, "mmc_ck"),
866 omap_findclk(s, ((value >> 23) & 1) ?
867 "ck_48m" : "armper_ck"));
868 if (diff & (1 << 12)) /* CONF_MOD_COM_MCLK_12_48_S */
869 omap_clk_reparent(omap_findclk(s, "com_mclk_out"),
870 omap_findclk(s, ((value >> 12) & 1) ?
871 "ck_48m" : "armper_ck"));
872 if (diff & (1 << 9)) /* CONF_MOD_USB_HOST_HHC_UHO */
873 omap_clk_onoff(omap_findclk(s, "usb_hhc_ck"), (value >> 9) & 1);
874}
875
a8170e5e 876static void omap_pin_cfg_write(void *opaque, hwaddr addr,
4b3fedf3 877 uint64_t value, unsigned size)
c3d2689d
AZ		 878{
879 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
c3d2689d
AZ		 880 uint32_t diff;
881
4b3fedf3 882 if (size != 4) {
77a8257e
SW		 883 omap_badwidth_write32(opaque, addr, value);
884 return;
4b3fedf3
AK		 885 }
886
8da3ff18 887 switch (addr) {
c3d2689d 888 case 0x00: /* FUNC_MUX_CTRL_0 */
8da3ff18
PB		 889 diff = s->func_mux_ctrl[addr >> 2] ^ value;
890 s->func_mux_ctrl[addr >> 2] = value;
c3d2689d
AZ		 891 omap_pin_funcmux0_update(s, diff, value);
892 return;
893
894 case 0x04: /* FUNC_MUX_CTRL_1 */
8da3ff18
PB		 895 diff = s->func_mux_ctrl[addr >> 2] ^ value;
896 s->func_mux_ctrl[addr >> 2] = value;
c3d2689d
AZ		 897 omap_pin_funcmux1_update(s, diff, value);
898 return;
899
900 case 0x08: /* FUNC_MUX_CTRL_2 */
8da3ff18 901 s->func_mux_ctrl[addr >> 2] = value;
c3d2689d
AZ		 902 return;
903
904 case 0x0c: /* COMP_MODE_CTRL_0 */
905 s->comp_mode_ctrl[0] = value;
906 s->compat1509 = (value != 0x0000eaef);
907 omap_pin_funcmux0_update(s, ~0, s->func_mux_ctrl[0]);
908 omap_pin_funcmux1_update(s, ~0, s->func_mux_ctrl[1]);
909 return;
910
911 case 0x10: /* FUNC_MUX_CTRL_3 */
912 case 0x14: /* FUNC_MUX_CTRL_4 */
913 case 0x18: /* FUNC_MUX_CTRL_5 */
914 case 0x1c: /* FUNC_MUX_CTRL_6 */
915 case 0x20: /* FUNC_MUX_CTRL_7 */
916 case 0x24: /* FUNC_MUX_CTRL_8 */
917 case 0x28: /* FUNC_MUX_CTRL_9 */
918 case 0x2c: /* FUNC_MUX_CTRL_A */
919 case 0x30: /* FUNC_MUX_CTRL_B */
920 case 0x34: /* FUNC_MUX_CTRL_C */
921 case 0x38: /* FUNC_MUX_CTRL_D */
8da3ff18 922 s->func_mux_ctrl[(addr >> 2) - 1] = value;
c3d2689d
AZ		 923 return;
924
925 case 0x40: /* PULL_DWN_CTRL_0 */
926 case 0x44: /* PULL_DWN_CTRL_1 */
927 case 0x48: /* PULL_DWN_CTRL_2 */
928 case 0x4c: /* PULL_DWN_CTRL_3 */
8da3ff18 929 s->pull_dwn_ctrl[(addr & 0xf) >> 2] = value;
c3d2689d
AZ		 930 return;
931
932 case 0x50: /* GATE_INH_CTRL_0 */
933 s->gate_inh_ctrl[0] = value;
934 return;
935
936 case 0x60: /* VOLTAGE_CTRL_0 */
937 s->voltage_ctrl[0] = value;
938 return;
939
940 case 0x70: /* TEST_DBG_CTRL_0 */
941 s->test_dbg_ctrl[0] = value;
942 return;
943
944 case 0x80: /* MOD_CONF_CTRL_0 */
945 diff = s->mod_conf_ctrl[0] ^ value;
946 s->mod_conf_ctrl[0] = value;
947 omap_pin_modconf1_update(s, diff, value);
948 return;
949
950 default:
951 OMAP_BAD_REG(addr);
952 }
953}
954
4b3fedf3
AK		 955static const MemoryRegionOps omap_pin_cfg_ops = {
956 .read = omap_pin_cfg_read,
957 .write = omap_pin_cfg_write,
958 .endianness = DEVICE_NATIVE_ENDIAN,
c3d2689d
AZ		 959};
960
961static void omap_pin_cfg_reset(struct omap_mpu_state_s *mpu)
962{
963 /* Start in Compatibility Mode. */
964 mpu->compat1509 = 1;
965 omap_pin_funcmux0_update(mpu, mpu->func_mux_ctrl[0], 0);
966 omap_pin_funcmux1_update(mpu, mpu->func_mux_ctrl[1], 0);
967 omap_pin_modconf1_update(mpu, mpu->mod_conf_ctrl[0], 0);
968 memset(mpu->func_mux_ctrl, 0, sizeof(mpu->func_mux_ctrl));
969 memset(mpu->comp_mode_ctrl, 0, sizeof(mpu->comp_mode_ctrl));
970 memset(mpu->pull_dwn_ctrl, 0, sizeof(mpu->pull_dwn_ctrl));
971 memset(mpu->gate_inh_ctrl, 0, sizeof(mpu->gate_inh_ctrl));
972 memset(mpu->voltage_ctrl, 0, sizeof(mpu->voltage_ctrl));
973 memset(mpu->test_dbg_ctrl, 0, sizeof(mpu->test_dbg_ctrl));
974 memset(mpu->mod_conf_ctrl, 0, sizeof(mpu->mod_conf_ctrl));
975}
976
4b3fedf3 977static void omap_pin_cfg_init(MemoryRegion *system_memory,
a8170e5e 978 hwaddr base,
c3d2689d
AZ		 979 struct omap_mpu_state_s *mpu)
980{
2c9b15ca 981 memory_region_init_io(&mpu->pin_cfg_iomem, NULL, &omap_pin_cfg_ops, mpu,
4b3fedf3
AK		 982 "omap-pin-cfg", 0x800);
983 memory_region_add_subregion(system_memory, base, &mpu->pin_cfg_iomem);
c3d2689d
AZ		 984 omap_pin_cfg_reset(mpu);
985}
986
987/* Device Identification, Die Identification */
a8170e5e 988static uint64_t omap_id_read(void *opaque, hwaddr addr,
4b3fedf3 989 unsigned size)
c3d2689d
AZ		 990{
991 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
992
4b3fedf3
AK		 993 if (size != 4) {
994 return omap_badwidth_read32(opaque, addr);
995 }
996
c3d2689d
AZ		 997 switch (addr) {
998 case 0xfffe1800: /* DIE_ID_LSB */
999 return 0xc9581f0e;
1000 case 0xfffe1804: /* DIE_ID_MSB */
1001 return 0xa8858bfa;
1002
1003 case 0xfffe2000: /* PRODUCT_ID_LSB */
1004 return 0x00aaaafc;
1005 case 0xfffe2004: /* PRODUCT_ID_MSB */
1006 return 0xcafeb574;
1007
1008 case 0xfffed400: /* JTAG_ID_LSB */
1009 switch (s->mpu_model) {
1010 case omap310:
1011 return 0x03310315;
1012 case omap1510:
1013 return 0x03310115;
827df9f3 1014 default:
a89f364a 1015 hw_error("%s: bad mpu model\n", __func__);
c3d2689d
AZ		 1016 }
1017 break;
1018
1019 case 0xfffed404: /* JTAG_ID_MSB */
1020 switch (s->mpu_model) {
1021 case omap310:
1022 return 0xfb57402f;
1023 case omap1510:
1024 return 0xfb47002f;
827df9f3 1025 default:
a89f364a 1026 hw_error("%s: bad mpu model\n", __func__);
c3d2689d
AZ		 1027 }
1028 break;
1029 }
1030
1031 OMAP_BAD_REG(addr);
1032 return 0;
1033}
1034
a8170e5e 1035static void omap_id_write(void *opaque, hwaddr addr,
4b3fedf3 1036 uint64_t value, unsigned size)
c3d2689d 1037{
4b3fedf3 1038 if (size != 4) {
77a8257e
SW		 1039 omap_badwidth_write32(opaque, addr, value);
1040 return;
4b3fedf3
AK		 1041 }
1042
c3d2689d
AZ		 1043 OMAP_BAD_REG(addr);
1044}
1045
4b3fedf3
AK		 1046static const MemoryRegionOps omap_id_ops = {
1047 .read = omap_id_read,
1048 .write = omap_id_write,
1049 .endianness = DEVICE_NATIVE_ENDIAN,
c3d2689d
AZ		 1050};
1051
4b3fedf3 1052static void omap_id_init(MemoryRegion *memory, struct omap_mpu_state_s *mpu)
c3d2689d 1053{
2c9b15ca 1054 memory_region_init_io(&mpu->id_iomem, NULL, &omap_id_ops, mpu,
4b3fedf3 1055 "omap-id", 0x100000000ULL);
2c9b15ca 1056 memory_region_init_alias(&mpu->id_iomem_e18, NULL, "omap-id-e18", &mpu->id_iomem,
4b3fedf3
AK		 1057 0xfffe1800, 0x800);
1058 memory_region_add_subregion(memory, 0xfffe1800, &mpu->id_iomem_e18);
2c9b15ca 1059 memory_region_init_alias(&mpu->id_iomem_ed4, NULL, "omap-id-ed4", &mpu->id_iomem,
4b3fedf3
AK		 1060 0xfffed400, 0x100);
1061 memory_region_add_subregion(memory, 0xfffed400, &mpu->id_iomem_ed4);
1062 if (!cpu_is_omap15xx(mpu)) {
2c9b15ca 1063 memory_region_init_alias(&mpu->id_iomem_ed4, NULL, "omap-id-e20",
4b3fedf3
AK		 1064 &mpu->id_iomem, 0xfffe2000, 0x800);
1065 memory_region_add_subregion(memory, 0xfffe2000, &mpu->id_iomem_e20);
1066 }
c3d2689d
AZ		 1067}
1068
1069/* MPUI Control (Dummy) */
a8170e5e 1070static uint64_t omap_mpui_read(void *opaque, hwaddr addr,
4b3fedf3 1071 unsigned size)
c3d2689d
AZ		 1072{
1073 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
c3d2689d 1074
4b3fedf3
AK		 1075 if (size != 4) {
1076 return omap_badwidth_read32(opaque, addr);
1077 }
1078
8da3ff18 1079 switch (addr) {
c3d2689d
AZ		 1080 case 0x00: /* CTRL */
1081 return s->mpui_ctrl;
1082 case 0x04: /* DEBUG_ADDR */
1083 return 0x01ffffff;
1084 case 0x08: /* DEBUG_DATA */
1085 return 0xffffffff;
1086 case 0x0c: /* DEBUG_FLAG */
1087 return 0x00000800;
1088 case 0x10: /* STATUS */
1089 return 0x00000000;
1090
1091 /* Not in OMAP310 */
1092 case 0x14: /* DSP_STATUS */
1093 case 0x18: /* DSP_BOOT_CONFIG */
1094 return 0x00000000;
1095 case 0x1c: /* DSP_MPUI_CONFIG */
1096 return 0x0000ffff;
1097 }
1098
1099 OMAP_BAD_REG(addr);
1100 return 0;
1101}
1102
a8170e5e 1103static void omap_mpui_write(void *opaque, hwaddr addr,
4b3fedf3 1104 uint64_t value, unsigned size)
c3d2689d
AZ		 1105{
1106 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
c3d2689d 1107
4b3fedf3 1108 if (size != 4) {
77a8257e
SW		 1109 omap_badwidth_write32(opaque, addr, value);
1110 return;
4b3fedf3
AK		 1111 }
1112
8da3ff18 1113 switch (addr) {
c3d2689d
AZ		 1114 case 0x00: /* CTRL */
1115 s->mpui_ctrl = value & 0x007fffff;
1116 break;
1117
1118 case 0x04: /* DEBUG_ADDR */
1119 case 0x08: /* DEBUG_DATA */
1120 case 0x0c: /* DEBUG_FLAG */
1121 case 0x10: /* STATUS */
1122 /* Not in OMAP310 */
1123 case 0x14: /* DSP_STATUS */
1124 OMAP_RO_REG(addr);
139bd956 1125 break;
c3d2689d
AZ		 1126 case 0x18: /* DSP_BOOT_CONFIG */
1127 case 0x1c: /* DSP_MPUI_CONFIG */
1128 break;
1129
1130 default:
1131 OMAP_BAD_REG(addr);
1132 }
1133}
1134
4b3fedf3
AK		 1135static const MemoryRegionOps omap_mpui_ops = {
1136 .read = omap_mpui_read,
1137 .write = omap_mpui_write,
1138 .endianness = DEVICE_NATIVE_ENDIAN,
c3d2689d
AZ		 1139};
1140
1141static void omap_mpui_reset(struct omap_mpu_state_s *s)
1142{
1143 s->mpui_ctrl = 0x0003ff1b;
1144}
1145
a8170e5e 1146static void omap_mpui_init(MemoryRegion *memory, hwaddr base,
c3d2689d
AZ		 1147 struct omap_mpu_state_s *mpu)
1148{
2c9b15ca 1149 memory_region_init_io(&mpu->mpui_iomem, NULL, &omap_mpui_ops, mpu,
4b3fedf3
AK		 1150 "omap-mpui", 0x100);
1151 memory_region_add_subregion(memory, base, &mpu->mpui_iomem);
c3d2689d
AZ		 1152
1153 omap_mpui_reset(mpu);
1154}
1155
1156/* TIPB Bridges */
1157struct omap_tipb_bridge_s {
c3d2689d 1158 qemu_irq abort;
4b3fedf3 1159 MemoryRegion iomem;
c3d2689d
AZ		 1160
1161 int width_intr;
1162 uint16_t control;
1163 uint16_t alloc;
1164 uint16_t buffer;
1165 uint16_t enh_control;
1166};
1167
a8170e5e 1168static uint64_t omap_tipb_bridge_read(void *opaque, hwaddr addr,
4b3fedf3 1169 unsigned size)
c3d2689d
AZ		 1170{
1171 struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *) opaque;
c3d2689d 1172
4b3fedf3
AK		 1173 if (size < 2) {
1174 return omap_badwidth_read16(opaque, addr);
1175 }
1176
8da3ff18 1177 switch (addr) {
c3d2689d
AZ		 1178 case 0x00: /* TIPB_CNTL */
1179 return s->control;
1180 case 0x04: /* TIPB_BUS_ALLOC */
1181 return s->alloc;
1182 case 0x08: /* MPU_TIPB_CNTL */
1183 return s->buffer;
1184 case 0x0c: /* ENHANCED_TIPB_CNTL */
1185 return s->enh_control;
1186 case 0x10: /* ADDRESS_DBG */
1187 case 0x14: /* DATA_DEBUG_LOW */
1188 case 0x18: /* DATA_DEBUG_HIGH */
1189 return 0xffff;
1190 case 0x1c: /* DEBUG_CNTR_SIG */
1191 return 0x00f8;
1192 }
1193
1194 OMAP_BAD_REG(addr);
1195 return 0;
1196}
1197
a8170e5e 1198static void omap_tipb_bridge_write(void *opaque, hwaddr addr,
4b3fedf3 1199 uint64_t value, unsigned size)
c3d2689d
AZ		 1200{
1201 struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *) opaque;
c3d2689d 1202
4b3fedf3 1203 if (size < 2) {
77a8257e
SW		 1204 omap_badwidth_write16(opaque, addr, value);
1205 return;
4b3fedf3
AK		 1206 }
1207
8da3ff18 1208 switch (addr) {
c3d2689d
AZ		 1209 case 0x00: /* TIPB_CNTL */
1210 s->control = value & 0xffff;
1211 break;
1212
1213 case 0x04: /* TIPB_BUS_ALLOC */
1214 s->alloc = value & 0x003f;
1215 break;
1216
1217 case 0x08: /* MPU_TIPB_CNTL */
1218 s->buffer = value & 0x0003;
1219 break;
1220
1221 case 0x0c: /* ENHANCED_TIPB_CNTL */
1222 s->width_intr = !(value & 2);
1223 s->enh_control = value & 0x000f;
1224 break;
1225
1226 case 0x10: /* ADDRESS_DBG */
1227 case 0x14: /* DATA_DEBUG_LOW */
1228 case 0x18: /* DATA_DEBUG_HIGH */
1229 case 0x1c: /* DEBUG_CNTR_SIG */
1230 OMAP_RO_REG(addr);
1231 break;
1232
1233 default:
1234 OMAP_BAD_REG(addr);
1235 }
1236}
1237
4b3fedf3
AK		 1238static const MemoryRegionOps omap_tipb_bridge_ops = {
1239 .read = omap_tipb_bridge_read,
1240 .write = omap_tipb_bridge_write,
1241 .endianness = DEVICE_NATIVE_ENDIAN,
c3d2689d
AZ		 1242};
1243
1244static void omap_tipb_bridge_reset(struct omap_tipb_bridge_s *s)
1245{
1246 s->control = 0xffff;
1247 s->alloc = 0x0009;
1248 s->buffer = 0x0000;
1249 s->enh_control = 0x000f;
1250}
1251
4b3fedf3 1252static struct omap_tipb_bridge_s *omap_tipb_bridge_init(
a8170e5e 1253 MemoryRegion *memory, hwaddr base,
4b3fedf3 1254 qemu_irq abort_irq, omap_clk clk)
c3d2689d 1255{
b45c03f5 1256 struct omap_tipb_bridge_s *s = g_new0(struct omap_tipb_bridge_s, 1);
c3d2689d
AZ		 1257
1258 s->abort = abort_irq;
c3d2689d
AZ		 1259 omap_tipb_bridge_reset(s);
1260
2c9b15ca 1261 memory_region_init_io(&s->iomem, NULL, &omap_tipb_bridge_ops, s,
4b3fedf3
AK		 1262 "omap-tipb-bridge", 0x100);
1263 memory_region_add_subregion(memory, base, &s->iomem);
c3d2689d
AZ		 1264
1265 return s;
1266}
1267
1268/* Dummy Traffic Controller's Memory Interface */
a8170e5e 1269static uint64_t omap_tcmi_read(void *opaque, hwaddr addr,
e7aa0ae0 1270 unsigned size)
c3d2689d
AZ		 1271{
1272 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
c3d2689d
AZ		 1273 uint32_t ret;
1274
e7aa0ae0
AK		 1275 if (size != 4) {
1276 return omap_badwidth_read32(opaque, addr);
1277 }
1278
8da3ff18 1279 switch (addr) {
d8f699cb
AZ		 1280 case 0x00: /* IMIF_PRIO */
1281 case 0x04: /* EMIFS_PRIO */
1282 case 0x08: /* EMIFF_PRIO */
1283 case 0x0c: /* EMIFS_CONFIG */
1284 case 0x10: /* EMIFS_CS0_CONFIG */
1285 case 0x14: /* EMIFS_CS1_CONFIG */
1286 case 0x18: /* EMIFS_CS2_CONFIG */
1287 case 0x1c: /* EMIFS_CS3_CONFIG */
1288 case 0x24: /* EMIFF_MRS */
1289 case 0x28: /* TIMEOUT1 */
1290 case 0x2c: /* TIMEOUT2 */
1291 case 0x30: /* TIMEOUT3 */
1292 case 0x3c: /* EMIFF_SDRAM_CONFIG_2 */
1293 case 0x40: /* EMIFS_CFG_DYN_WAIT */
8da3ff18 1294 return s->tcmi_regs[addr >> 2];
c3d2689d 1295
d8f699cb 1296 case 0x20: /* EMIFF_SDRAM_CONFIG */
8da3ff18
PB		 1297 ret = s->tcmi_regs[addr >> 2];
1298 s->tcmi_regs[addr >> 2] &= ~1; /* XXX: Clear SLRF on SDRAM access */
c3d2689d
AZ		 1299 /* XXX: We can try using the VGA_DIRTY flag for this */
1300 return ret;
1301 }
1302
1303 OMAP_BAD_REG(addr);
1304 return 0;
1305}
1306
a8170e5e 1307static void omap_tcmi_write(void *opaque, hwaddr addr,
e7aa0ae0 1308 uint64_t value, unsigned size)
c3d2689d
AZ		 1309{
1310 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
c3d2689d 1311
e7aa0ae0 1312 if (size != 4) {
77a8257e
SW		 1313 omap_badwidth_write32(opaque, addr, value);
1314 return;
e7aa0ae0
AK		 1315 }
1316
8da3ff18 1317 switch (addr) {
d8f699cb
AZ		 1318 case 0x00: /* IMIF_PRIO */
1319 case 0x04: /* EMIFS_PRIO */
1320 case 0x08: /* EMIFF_PRIO */
1321 case 0x10: /* EMIFS_CS0_CONFIG */
1322 case 0x14: /* EMIFS_CS1_CONFIG */
1323 case 0x18: /* EMIFS_CS2_CONFIG */
1324 case 0x1c: /* EMIFS_CS3_CONFIG */
1325 case 0x20: /* EMIFF_SDRAM_CONFIG */
1326 case 0x24: /* EMIFF_MRS */
1327 case 0x28: /* TIMEOUT1 */
1328 case 0x2c: /* TIMEOUT2 */
1329 case 0x30: /* TIMEOUT3 */
1330 case 0x3c: /* EMIFF_SDRAM_CONFIG_2 */
1331 case 0x40: /* EMIFS_CFG_DYN_WAIT */
8da3ff18 1332 s->tcmi_regs[addr >> 2] = value;
c3d2689d 1333 break;
d8f699cb 1334 case 0x0c: /* EMIFS_CONFIG */
8da3ff18 1335 s->tcmi_regs[addr >> 2] = (value & 0xf) | (1 << 4);
c3d2689d
AZ		 1336 break;
1337
1338 default:
1339 OMAP_BAD_REG(addr);
1340 }
1341}
1342
e7aa0ae0
AK		 1343static const MemoryRegionOps omap_tcmi_ops = {
1344 .read = omap_tcmi_read,
1345 .write = omap_tcmi_write,
1346 .endianness = DEVICE_NATIVE_ENDIAN,
c3d2689d
AZ		 1347};
1348
1349static void omap_tcmi_reset(struct omap_mpu_state_s *mpu)
1350{
1351 mpu->tcmi_regs[0x00 >> 2] = 0x00000000;
1352 mpu->tcmi_regs[0x04 >> 2] = 0x00000000;
1353 mpu->tcmi_regs[0x08 >> 2] = 0x00000000;
1354 mpu->tcmi_regs[0x0c >> 2] = 0x00000010;
1355 mpu->tcmi_regs[0x10 >> 2] = 0x0010fffb;
1356 mpu->tcmi_regs[0x14 >> 2] = 0x0010fffb;
1357 mpu->tcmi_regs[0x18 >> 2] = 0x0010fffb;
1358 mpu->tcmi_regs[0x1c >> 2] = 0x0010fffb;
1359 mpu->tcmi_regs[0x20 >> 2] = 0x00618800;
1360 mpu->tcmi_regs[0x24 >> 2] = 0x00000037;
1361 mpu->tcmi_regs[0x28 >> 2] = 0x00000000;
1362 mpu->tcmi_regs[0x2c >> 2] = 0x00000000;
1363 mpu->tcmi_regs[0x30 >> 2] = 0x00000000;
1364 mpu->tcmi_regs[0x3c >> 2] = 0x00000003;
1365 mpu->tcmi_regs[0x40 >> 2] = 0x00000000;
1366}
1367
a8170e5e 1368static void omap_tcmi_init(MemoryRegion *memory, hwaddr base,
c3d2689d
AZ		 1369 struct omap_mpu_state_s *mpu)
1370{
2c9b15ca 1371 memory_region_init_io(&mpu->tcmi_iomem, NULL, &omap_tcmi_ops, mpu,
e7aa0ae0
AK		 1372 "omap-tcmi", 0x100);
1373 memory_region_add_subregion(memory, base, &mpu->tcmi_iomem);
c3d2689d
AZ		 1374 omap_tcmi_reset(mpu);
1375}
1376
1377/* Digital phase-locked loops control */
b9f7bc40
JR		 1378struct dpll_ctl_s {
1379 MemoryRegion iomem;
1380 uint16_t mode;
1381 omap_clk dpll;
1382};
1383
a8170e5e 1384static uint64_t omap_dpll_read(void *opaque, hwaddr addr,
e7aa0ae0 1385 unsigned size)
c3d2689d
AZ		 1386{
1387 struct dpll_ctl_s *s = (struct dpll_ctl_s *) opaque;
c3d2689d 1388
e7aa0ae0
AK		 1389 if (size != 2) {
1390 return omap_badwidth_read16(opaque, addr);
1391 }
1392
8da3ff18 1393 if (addr == 0x00) /* CTL_REG */
c3d2689d
AZ		 1394 return s->mode;
1395
1396 OMAP_BAD_REG(addr);
1397 return 0;
1398}
1399
a8170e5e 1400static void omap_dpll_write(void *opaque, hwaddr addr,
e7aa0ae0 1401 uint64_t value, unsigned size)
c3d2689d
AZ		 1402{
1403 struct dpll_ctl_s *s = (struct dpll_ctl_s *) opaque;
1404 uint16_t diff;
c3d2689d
AZ		 1405 static const int bypass_div[4] = { 1, 2, 4, 4 };
1406 int div, mult;
1407
e7aa0ae0 1408 if (size != 2) {
77a8257e
SW		 1409 omap_badwidth_write16(opaque, addr, value);
1410 return;
e7aa0ae0
AK		 1411 }
1412
8da3ff18 1413 if (addr == 0x00) { /* CTL_REG */
c3d2689d
AZ		 1414 /* See omap_ulpd_pm_write() too */
1415 diff = s->mode & value;
1416 s->mode = value & 0x2fff;
1417 if (diff & (0x3ff << 2)) {
1418 if (value & (1 << 4)) { /* PLL_ENABLE */
1419 div = ((value >> 5) & 3) + 1; /* PLL_DIV */
1420 mult = MIN((value >> 7) & 0x1f, 1); /* PLL_MULT */
1421 } else {
1422 div = bypass_div[((value >> 2) & 3)]; /* BYPASS_DIV */
1423 mult = 1;
1424 }
1425 omap_clk_setrate(s->dpll, div, mult);
1426 }
1427
1428 /* Enter the desired mode. */
1429 s->mode = (s->mode & 0xfffe) | ((s->mode >> 4) & 1);
1430
1431 /* Act as if the lock is restored. */
1432 s->mode |= 2;
1433 } else {
1434 OMAP_BAD_REG(addr);
1435 }
1436}
1437
e7aa0ae0
AK		 1438static const MemoryRegionOps omap_dpll_ops = {
1439 .read = omap_dpll_read,
1440 .write = omap_dpll_write,
1441 .endianness = DEVICE_NATIVE_ENDIAN,
c3d2689d
AZ		 1442};
1443
1444static void omap_dpll_reset(struct dpll_ctl_s *s)
1445{
1446 s->mode = 0x2002;
1447 omap_clk_setrate(s->dpll, 1, 1);
1448}
1449
b9f7bc40 1450static struct dpll_ctl_s *omap_dpll_init(MemoryRegion *memory,
a8170e5e 1451 hwaddr base, omap_clk clk)
c3d2689d 1452{
b9f7bc40 1453 struct dpll_ctl_s *s = g_malloc0(sizeof(*s));
2c9b15ca 1454 memory_region_init_io(&s->iomem, NULL, &omap_dpll_ops, s, "omap-dpll", 0x100);
c3d2689d 1455
c3d2689d
AZ		 1456 s->dpll = clk;
1457 omap_dpll_reset(s);
1458
e7aa0ae0 1459 memory_region_add_subregion(memory, base, &s->iomem);
b9f7bc40 1460 return s;
c3d2689d
AZ		 1461}
1462
c3d2689d 1463/* MPU Clock/Reset/Power Mode Control */
a8170e5e 1464static uint64_t omap_clkm_read(void *opaque, hwaddr addr,
e7aa0ae0 1465 unsigned size)
c3d2689d
AZ		 1466{
1467 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
c3d2689d 1468
e7aa0ae0
AK		 1469 if (size != 2) {
1470 return omap_badwidth_read16(opaque, addr);
1471 }
1472
8da3ff18 1473 switch (addr) {
c3d2689d
AZ		 1474 case 0x00: /* ARM_CKCTL */
1475 return s->clkm.arm_ckctl;
1476
1477 case 0x04: /* ARM_IDLECT1 */
1478 return s->clkm.arm_idlect1;
1479
1480 case 0x08: /* ARM_IDLECT2 */
1481 return s->clkm.arm_idlect2;
1482
1483 case 0x0c: /* ARM_EWUPCT */
1484 return s->clkm.arm_ewupct;
1485
1486 case 0x10: /* ARM_RSTCT1 */
1487 return s->clkm.arm_rstct1;
1488
1489 case 0x14: /* ARM_RSTCT2 */
1490 return s->clkm.arm_rstct2;
1491
1492 case 0x18: /* ARM_SYSST */
d8f699cb 1493 return (s->clkm.clocking_scheme << 11) | s->clkm.cold_start;
c3d2689d
AZ		 1494
1495 case 0x1c: /* ARM_CKOUT1 */
1496 return s->clkm.arm_ckout1;
1497
1498 case 0x20: /* ARM_CKOUT2 */
1499 break;
1500 }
1501
1502 OMAP_BAD_REG(addr);
1503 return 0;
1504}
1505
1506static inline void omap_clkm_ckctl_update(struct omap_mpu_state_s *s,
1507 uint16_t diff, uint16_t value)
1508{
1509 omap_clk clk;
1510
1511 if (diff & (1 << 14)) { /* ARM_INTHCK_SEL */
1512 if (value & (1 << 14))
1513 /* Reserved */;
1514 else {
1515 clk = omap_findclk(s, "arminth_ck");
1516 omap_clk_reparent(clk, omap_findclk(s, "tc_ck"));
1517 }
1518 }
1519 if (diff & (1 << 12)) { /* ARM_TIMXO */
1520 clk = omap_findclk(s, "armtim_ck");
1521 if (value & (1 << 12))
1522 omap_clk_reparent(clk, omap_findclk(s, "clkin"));
1523 else
1524 omap_clk_reparent(clk, omap_findclk(s, "ck_gen1"));
1525 }
1526 /* XXX: en_dspck */
1527 if (diff & (3 << 10)) { /* DSPMMUDIV */
1528 clk = omap_findclk(s, "dspmmu_ck");
1529 omap_clk_setrate(clk, 1 << ((value >> 10) & 3), 1);
1530 }
1531 if (diff & (3 << 8)) { /* TCDIV */
1532 clk = omap_findclk(s, "tc_ck");
1533 omap_clk_setrate(clk, 1 << ((value >> 8) & 3), 1);
1534 }
1535 if (diff & (3 << 6)) { /* DSPDIV */
1536 clk = omap_findclk(s, "dsp_ck");
1537 omap_clk_setrate(clk, 1 << ((value >> 6) & 3), 1);
1538 }
1539 if (diff & (3 << 4)) { /* ARMDIV */
1540 clk = omap_findclk(s, "arm_ck");
1541 omap_clk_setrate(clk, 1 << ((value >> 4) & 3), 1);
1542 }
1543 if (diff & (3 << 2)) { /* LCDDIV */
1544 clk = omap_findclk(s, "lcd_ck");
1545 omap_clk_setrate(clk, 1 << ((value >> 2) & 3), 1);
1546 }
1547 if (diff & (3 << 0)) { /* PERDIV */
1548 clk = omap_findclk(s, "armper_ck");
1549 omap_clk_setrate(clk, 1 << ((value >> 0) & 3), 1);
1550 }
1551}
1552
1553static inline void omap_clkm_idlect1_update(struct omap_mpu_state_s *s,
1554 uint16_t diff, uint16_t value)
1555{
1556 omap_clk clk;
1557
5f4ef08b 1558 if (value & (1 << 11)) { /* SETARM_IDLE */
c3affe56 1559 cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_HALT);
5f4ef08b 1560 }
cf83f140
EB		 1561 if (!(value & (1 << 10))) { /* WKUP_MODE */
1562 /* XXX: disable wakeup from IRQ */
1563 qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
1564 }
c3d2689d
AZ		 1565
1566#define SET_CANIDLE(clock, bit) \
1567 if (diff & (1 << bit)) { \
1568 clk = omap_findclk(s, clock); \
1569 omap_clk_canidle(clk, (value >> bit) & 1); \
1570 }
1571 SET_CANIDLE("mpuwd_ck", 0) /* IDLWDT_ARM */
1572 SET_CANIDLE("armxor_ck", 1) /* IDLXORP_ARM */
1573 SET_CANIDLE("mpuper_ck", 2) /* IDLPER_ARM */
1574 SET_CANIDLE("lcd_ck", 3) /* IDLLCD_ARM */
1575 SET_CANIDLE("lb_ck", 4) /* IDLLB_ARM */
1576 SET_CANIDLE("hsab_ck", 5) /* IDLHSAB_ARM */
1577 SET_CANIDLE("tipb_ck", 6) /* IDLIF_ARM */
1578 SET_CANIDLE("dma_ck", 6) /* IDLIF_ARM */
1579 SET_CANIDLE("tc_ck", 6) /* IDLIF_ARM */
1580 SET_CANIDLE("dpll1", 7) /* IDLDPLL_ARM */
1581 SET_CANIDLE("dpll2", 7) /* IDLDPLL_ARM */
1582 SET_CANIDLE("dpll3", 7) /* IDLDPLL_ARM */
1583 SET_CANIDLE("mpui_ck", 8) /* IDLAPI_ARM */
1584 SET_CANIDLE("armtim_ck", 9) /* IDLTIM_ARM */
1585}
1586
1587static inline void omap_clkm_idlect2_update(struct omap_mpu_state_s *s,
1588 uint16_t diff, uint16_t value)
1589{
1590 omap_clk clk;
1591
1592#define SET_ONOFF(clock, bit) \
1593 if (diff & (1 << bit)) { \
1594 clk = omap_findclk(s, clock); \
1595 omap_clk_onoff(clk, (value >> bit) & 1); \
1596 }
1597 SET_ONOFF("mpuwd_ck", 0) /* EN_WDTCK */
1598 SET_ONOFF("armxor_ck", 1) /* EN_XORPCK */
1599 SET_ONOFF("mpuper_ck", 2) /* EN_PERCK */
1600 SET_ONOFF("lcd_ck", 3) /* EN_LCDCK */
1601 SET_ONOFF("lb_ck", 4) /* EN_LBCK */
1602 SET_ONOFF("hsab_ck", 5) /* EN_HSABCK */
1603 SET_ONOFF("mpui_ck", 6) /* EN_APICK */
1604 SET_ONOFF("armtim_ck", 7) /* EN_TIMCK */
1605 SET_CANIDLE("dma_ck", 8) /* DMACK_REQ */
1606 SET_ONOFF("arm_gpio_ck", 9) /* EN_GPIOCK */
1607 SET_ONOFF("lbfree_ck", 10) /* EN_LBFREECK */
1608}
1609
1610static inline void omap_clkm_ckout1_update(struct omap_mpu_state_s *s,
1611 uint16_t diff, uint16_t value)
1612{
1613 omap_clk clk;
1614
1615 if (diff & (3 << 4)) { /* TCLKOUT */
1616 clk = omap_findclk(s, "tclk_out");
1617 switch ((value >> 4) & 3) {
1618 case 1:
1619 omap_clk_reparent(clk, omap_findclk(s, "ck_gen3"));
1620 omap_clk_onoff(clk, 1);
1621 break;
1622 case 2:
1623 omap_clk_reparent(clk, omap_findclk(s, "tc_ck"));
1624 omap_clk_onoff(clk, 1);
1625 break;
1626 default:
1627 omap_clk_onoff(clk, 0);
1628 }
1629 }
1630 if (diff & (3 << 2)) { /* DCLKOUT */
1631 clk = omap_findclk(s, "dclk_out");
1632 switch ((value >> 2) & 3) {
1633 case 0:
1634 omap_clk_reparent(clk, omap_findclk(s, "dspmmu_ck"));
1635 break;
1636 case 1:
1637 omap_clk_reparent(clk, omap_findclk(s, "ck_gen2"));
1638 break;
1639 case 2:
1640 omap_clk_reparent(clk, omap_findclk(s, "dsp_ck"));
1641 break;
1642 case 3:
1643 omap_clk_reparent(clk, omap_findclk(s, "ck_ref14"));
1644 break;
1645 }
1646 }
1647 if (diff & (3 << 0)) { /* ACLKOUT */
1648 clk = omap_findclk(s, "aclk_out");
1649 switch ((value >> 0) & 3) {
1650 case 1:
1651 omap_clk_reparent(clk, omap_findclk(s, "ck_gen1"));
1652 omap_clk_onoff(clk, 1);
1653 break;
1654 case 2:
1655 omap_clk_reparent(clk, omap_findclk(s, "arm_ck"));
1656 omap_clk_onoff(clk, 1);
1657 break;
1658 case 3:
1659 omap_clk_reparent(clk, omap_findclk(s, "ck_ref14"));
1660 omap_clk_onoff(clk, 1);
1661 break;
1662 default:
1663 omap_clk_onoff(clk, 0);
1664 }
1665 }
1666}
1667
a8170e5e 1668static void omap_clkm_write(void *opaque, hwaddr addr,
e7aa0ae0 1669 uint64_t value, unsigned size)
c3d2689d
AZ		 1670{
1671 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
c3d2689d
AZ		 1672 uint16_t diff;
1673 omap_clk clk;
1674 static const char *clkschemename[8] = {
1675 "fully synchronous", "fully asynchronous", "synchronous scalable",
1676 "mix mode 1", "mix mode 2", "bypass mode", "mix mode 3", "mix mode 4",
1677 };
1678
e7aa0ae0 1679 if (size != 2) {
77a8257e
SW		 1680 omap_badwidth_write16(opaque, addr, value);
1681 return;
e7aa0ae0
AK		 1682 }
1683
8da3ff18 1684 switch (addr) {
c3d2689d
AZ		 1685 case 0x00: /* ARM_CKCTL */
1686 diff = s->clkm.arm_ckctl ^ value;
1687 s->clkm.arm_ckctl = value & 0x7fff;
1688 omap_clkm_ckctl_update(s, diff, value);
1689 return;
1690
1691 case 0x04: /* ARM_IDLECT1 */
1692 diff = s->clkm.arm_idlect1 ^ value;
1693 s->clkm.arm_idlect1 = value & 0x0fff;
1694 omap_clkm_idlect1_update(s, diff, value);
1695 return;
1696
1697 case 0x08: /* ARM_IDLECT2 */
1698 diff = s->clkm.arm_idlect2 ^ value;
1699 s->clkm.arm_idlect2 = value & 0x07ff;
1700 omap_clkm_idlect2_update(s, diff, value);
1701 return;
1702
1703 case 0x0c: /* ARM_EWUPCT */
c3d2689d
AZ		 1704 s->clkm.arm_ewupct = value & 0x003f;
1705 return;
1706
1707 case 0x10: /* ARM_RSTCT1 */
1708 diff = s->clkm.arm_rstct1 ^ value;
1709 s->clkm.arm_rstct1 = value & 0x0007;
1710 if (value & 9) {
cf83f140 1711 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
c3d2689d
AZ		 1712 s->clkm.cold_start = 0xa;
1713 }
1714 if (diff & ~value & 4) { /* DSP_RST */
1715 omap_mpui_reset(s);
1716 omap_tipb_bridge_reset(s->private_tipb);
1717 omap_tipb_bridge_reset(s->public_tipb);
1718 }
1719 if (diff & 2) { /* DSP_EN */
1720 clk = omap_findclk(s, "dsp_ck");
1721 omap_clk_canidle(clk, (~value >> 1) & 1);
1722 }
1723 return;
1724
1725 case 0x14: /* ARM_RSTCT2 */
1726 s->clkm.arm_rstct2 = value & 0x0001;
1727 return;
1728
1729 case 0x18: /* ARM_SYSST */
1730 if ((s->clkm.clocking_scheme ^ (value >> 11)) & 7) {
1731 s->clkm.clocking_scheme = (value >> 11) & 7;
a89f364a 1732 printf("%s: clocking scheme set to %s\n", __func__,
c94a60cb 1733 clkschemename[s->clkm.clocking_scheme]);
c3d2689d
AZ		 1734 }
1735 s->clkm.cold_start &= value & 0x3f;
1736 return;
1737
1738 case 0x1c: /* ARM_CKOUT1 */
1739 diff = s->clkm.arm_ckout1 ^ value;
1740 s->clkm.arm_ckout1 = value & 0x003f;
1741 omap_clkm_ckout1_update(s, diff, value);
1742 return;
1743
1744 case 0x20: /* ARM_CKOUT2 */
1745 default:
1746 OMAP_BAD_REG(addr);
1747 }
1748}
1749
e7aa0ae0
AK		 1750static const MemoryRegionOps omap_clkm_ops = {
1751 .read = omap_clkm_read,
1752 .write = omap_clkm_write,
1753 .endianness = DEVICE_NATIVE_ENDIAN,
c3d2689d
AZ		 1754};
1755
a8170e5e 1756static uint64_t omap_clkdsp_read(void *opaque, hwaddr addr,
e7aa0ae0 1757 unsigned size)
c3d2689d
AZ		 1758{
1759 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
259186a7 1760 CPUState *cpu = CPU(s->cpu);
c3d2689d 1761
e7aa0ae0
AK		 1762 if (size != 2) {
1763 return omap_badwidth_read16(opaque, addr);
1764 }
1765
8da3ff18 1766 switch (addr) {
c3d2689d
AZ		 1767 case 0x04: /* DSP_IDLECT1 */
1768 return s->clkm.dsp_idlect1;
1769
1770 case 0x08: /* DSP_IDLECT2 */
1771 return s->clkm.dsp_idlect2;
1772
1773 case 0x14: /* DSP_RSTCT2 */
1774 return s->clkm.dsp_rstct2;
1775
1776 case 0x18: /* DSP_SYSST */
d8f699cb 1777 return (s->clkm.clocking_scheme << 11) | s->clkm.cold_start |
259186a7 1778 (cpu->halted << 6); /* Quite useless... */
c3d2689d
AZ		 1779 }
1780
1781 OMAP_BAD_REG(addr);
1782 return 0;
1783}
1784
1785static inline void omap_clkdsp_idlect1_update(struct omap_mpu_state_s *s,
1786 uint16_t diff, uint16_t value)
1787{
1788 omap_clk clk;
1789
1790 SET_CANIDLE("dspxor_ck", 1); /* IDLXORP_DSP */
1791}
1792
1793static inline void omap_clkdsp_idlect2_update(struct omap_mpu_state_s *s,
1794 uint16_t diff, uint16_t value)
1795{
1796 omap_clk clk;
1797
1798 SET_ONOFF("dspxor_ck", 1); /* EN_XORPCK */
1799}
1800
a8170e5e 1801static void omap_clkdsp_write(void *opaque, hwaddr addr,
e7aa0ae0 1802 uint64_t value, unsigned size)
c3d2689d
AZ		 1803{
1804 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
c3d2689d
AZ		 1805 uint16_t diff;
1806
e7aa0ae0 1807 if (size != 2) {
77a8257e
SW		 1808 omap_badwidth_write16(opaque, addr, value);
1809 return;
e7aa0ae0
AK		 1810 }
1811
8da3ff18 1812 switch (addr) {
c3d2689d
AZ		 1813 case 0x04: /* DSP_IDLECT1 */
1814 diff = s->clkm.dsp_idlect1 ^ value;
1815 s->clkm.dsp_idlect1 = value & 0x01f7;
1816 omap_clkdsp_idlect1_update(s, diff, value);
1817 break;
1818
1819 case 0x08: /* DSP_IDLECT2 */
1820 s->clkm.dsp_idlect2 = value & 0x0037;
1821 diff = s->clkm.dsp_idlect1 ^ value;
1822 omap_clkdsp_idlect2_update(s, diff, value);
1823 break;
1824
1825 case 0x14: /* DSP_RSTCT2 */
1826 s->clkm.dsp_rstct2 = value & 0x0001;
1827 break;
1828
1829 case 0x18: /* DSP_SYSST */
1830 s->clkm.cold_start &= value & 0x3f;
1831 break;
1832
1833 default:
1834 OMAP_BAD_REG(addr);
1835 }
1836}
1837
e7aa0ae0
AK		 1838static const MemoryRegionOps omap_clkdsp_ops = {
1839 .read = omap_clkdsp_read,
1840 .write = omap_clkdsp_write,
1841 .endianness = DEVICE_NATIVE_ENDIAN,
c3d2689d
AZ		 1842};
1843
1844static void omap_clkm_reset(struct omap_mpu_state_s *s)
1845{
1846 if (s->wdt && s->wdt->reset)
1847 s->clkm.cold_start = 0x6;
1848 s->clkm.clocking_scheme = 0;
1849 omap_clkm_ckctl_update(s, ~0, 0x3000);
1850 s->clkm.arm_ckctl = 0x3000;
d8f699cb 1851 omap_clkm_idlect1_update(s, s->clkm.arm_idlect1 ^ 0x0400, 0x0400);
c3d2689d 1852 s->clkm.arm_idlect1 = 0x0400;
d8f699cb 1853 omap_clkm_idlect2_update(s, s->clkm.arm_idlect2 ^ 0x0100, 0x0100);
c3d2689d
AZ		 1854 s->clkm.arm_idlect2 = 0x0100;
1855 s->clkm.arm_ewupct = 0x003f;
1856 s->clkm.arm_rstct1 = 0x0000;
1857 s->clkm.arm_rstct2 = 0x0000;
1858 s->clkm.arm_ckout1 = 0x0015;
1859 s->clkm.dpll1_mode = 0x2002;
1860 omap_clkdsp_idlect1_update(s, s->clkm.dsp_idlect1 ^ 0x0040, 0x0040);
1861 s->clkm.dsp_idlect1 = 0x0040;
1862 omap_clkdsp_idlect2_update(s, ~0, 0x0000);
1863 s->clkm.dsp_idlect2 = 0x0000;
1864 s->clkm.dsp_rstct2 = 0x0000;
1865}
1866
a8170e5e
AK		 1867static void omap_clkm_init(MemoryRegion *memory, hwaddr mpu_base,
1868 hwaddr dsp_base, struct omap_mpu_state_s *s)
c3d2689d 1869{
2c9b15ca 1870 memory_region_init_io(&s->clkm_iomem, NULL, &omap_clkm_ops, s,
e7aa0ae0 1871 "omap-clkm", 0x100);
2c9b15ca 1872 memory_region_init_io(&s->clkdsp_iomem, NULL, &omap_clkdsp_ops, s,
e7aa0ae0 1873 "omap-clkdsp", 0x1000);
c3d2689d 1874
d8f699cb
AZ		 1875 s->clkm.arm_idlect1 = 0x03ff;
1876 s->clkm.arm_idlect2 = 0x0100;
1877 s->clkm.dsp_idlect1 = 0x0002;
c3d2689d 1878 omap_clkm_reset(s);
d8f699cb 1879 s->clkm.cold_start = 0x3a;
c3d2689d 1880
e7aa0ae0
AK		 1881 memory_region_add_subregion(memory, mpu_base, &s->clkm_iomem);
1882 memory_region_add_subregion(memory, dsp_base, &s->clkdsp_iomem);
c3d2689d
AZ		 1883}
1884
fe71e81a
AZ		 1885/* MPU I/O */
1886struct omap_mpuio_s {
fe71e81a
AZ		 1887 qemu_irq irq;
1888 qemu_irq kbd_irq;
1889 qemu_irq *in;
1890 qemu_irq handler[16];
1891 qemu_irq wakeup;
e7aa0ae0 1892 MemoryRegion iomem;
fe71e81a
AZ		 1893
1894 uint16_t inputs;
1895 uint16_t outputs;
1896 uint16_t dir;
1897 uint16_t edge;
1898 uint16_t mask;
1899 uint16_t ints;
1900
1901 uint16_t debounce;
1902 uint16_t latch;
1903 uint8_t event;
1904
1905 uint8_t buttons[5];
1906 uint8_t row_latch;
1907 uint8_t cols;
1908 int kbd_mask;
1909 int clk;
1910};
1911
1912static void omap_mpuio_set(void *opaque, int line, int level)
1913{
1914 struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque;
1915 uint16_t prev = s->inputs;
1916
1917 if (level)
1918 s->inputs |= 1 << line;
1919 else
1920 s->inputs &= ~(1 << line);
1921
1922 if (((1 << line) & s->dir & ~s->mask) && s->clk) {
1923 if ((s->edge & s->inputs & ~prev) | (~s->edge & ~s->inputs & prev)) {
1924 s->ints |= 1 << line;
1925 qemu_irq_raise(s->irq);
1926 /* TODO: wakeup */
1927 }
1928 if ((s->event & (1 << 0)) && /* SET_GPIO_EVENT_MODE */
1929 (s->event >> 1) == line) /* PIN_SELECT */
1930 s->latch = s->inputs;
1931 }
1932}
1933
1934static void omap_mpuio_kbd_update(struct omap_mpuio_s *s)
1935{
1936 int i;
1937 uint8_t *row, rows = 0, cols = ~s->cols;
1938
38a34e1d 1939 for (row = s->buttons + 4, i = 1 << 4; i; row --, i >>= 1)
fe71e81a 1940 if (*row & cols)
38a34e1d 1941 rows |= i;
fe71e81a 1942
cf6d9118
AZ		 1943 qemu_set_irq(s->kbd_irq, rows && !s->kbd_mask && s->clk);
1944 s->row_latch = ~rows;
fe71e81a
AZ		 1945}
1946
a8170e5e 1947static uint64_t omap_mpuio_read(void *opaque, hwaddr addr,
e7aa0ae0 1948 unsigned size)
fe71e81a
AZ		 1949{
1950 struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque;
cf965d24 1951 int offset = addr & OMAP_MPUI_REG_MASK;
fe71e81a
AZ		 1952 uint16_t ret;
1953
e7aa0ae0
AK		 1954 if (size != 2) {
1955 return omap_badwidth_read16(opaque, addr);
1956 }
1957
fe71e81a
AZ		 1958 switch (offset) {
1959 case 0x00: /* INPUT_LATCH */
1960 return s->inputs;
1961
1962 case 0x04: /* OUTPUT_REG */
1963 return s->outputs;
1964
1965 case 0x08: /* IO_CNTL */
1966 return s->dir;
1967
1968 case 0x10: /* KBR_LATCH */
1969 return s->row_latch;
1970
1971 case 0x14: /* KBC_REG */
1972 return s->cols;
1973
1974 case 0x18: /* GPIO_EVENT_MODE_REG */
1975 return s->event;
1976
1977 case 0x1c: /* GPIO_INT_EDGE_REG */
1978 return s->edge;
1979
1980 case 0x20: /* KBD_INT */
cf6d9118 1981 return (~s->row_latch & 0x1f) && !s->kbd_mask;
fe71e81a
AZ		 1982
1983 case 0x24: /* GPIO_INT */
1984 ret = s->ints;
8e129e07
AZ		 1985 s->ints &= s->mask;
1986 if (ret)
1987 qemu_irq_lower(s->irq);
fe71e81a
AZ		 1988 return ret;
1989
1990 case 0x28: /* KBD_MASKIT */
1991 return s->kbd_mask;
1992
1993 case 0x2c: /* GPIO_MASKIT */
1994 return s->mask;
1995
1996 case 0x30: /* GPIO_DEBOUNCING_REG */
1997 return s->debounce;
1998
1999 case 0x34: /* GPIO_LATCH_REG */
2000 return s->latch;
2001 }
2002
2003 OMAP_BAD_REG(addr);
2004 return 0;
2005}
2006
a8170e5e 2007static void omap_mpuio_write(void *opaque, hwaddr addr,
e7aa0ae0 2008 uint64_t value, unsigned size)
fe71e81a
AZ		 2009{
2010 struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque;
cf965d24 2011 int offset = addr & OMAP_MPUI_REG_MASK;
fe71e81a
AZ		 2012 uint16_t diff;
2013 int ln;
2014
e7aa0ae0 2015 if (size != 2) {
77a8257e
SW		 2016 omap_badwidth_write16(opaque, addr, value);
2017 return;
e7aa0ae0
AK		 2018 }
2019
fe71e81a
AZ		 2020 switch (offset) {
2021 case 0x04: /* OUTPUT_REG */
d8f699cb 2022 diff = (s->outputs ^ value) & ~s->dir;
fe71e81a 2023 s->outputs = value;
bd2a8884 2024 while ((ln = ctz32(diff)) != 32) {
fe71e81a
AZ		 2025 if (s->handler[ln])
2026 qemu_set_irq(s->handler[ln], (value >> ln) & 1);
2027 diff &= ~(1 << ln);
2028 }
2029 break;
2030
2031 case 0x08: /* IO_CNTL */
2032 diff = s->outputs & (s->dir ^ value);
2033 s->dir = value;
2034
2035 value = s->outputs & ~s->dir;
bd2a8884 2036 while ((ln = ctz32(diff)) != 32) {
fe71e81a
AZ		 2037 if (s->handler[ln])
2038 qemu_set_irq(s->handler[ln], (value >> ln) & 1);
2039 diff &= ~(1 << ln);
2040 }
2041 break;
2042
2043 case 0x14: /* KBC_REG */
2044 s->cols = value;
2045 omap_mpuio_kbd_update(s);
2046 break;
2047
2048 case 0x18: /* GPIO_EVENT_MODE_REG */
2049 s->event = value & 0x1f;
2050 break;
2051
2052 case 0x1c: /* GPIO_INT_EDGE_REG */
2053 s->edge = value;
2054 break;
2055
2056 case 0x28: /* KBD_MASKIT */
2057 s->kbd_mask = value & 1;
2058 omap_mpuio_kbd_update(s);
2059 break;
2060
2061 case 0x2c: /* GPIO_MASKIT */
2062 s->mask = value;
2063 break;
2064
2065 case 0x30: /* GPIO_DEBOUNCING_REG */
2066 s->debounce = value & 0x1ff;
2067 break;
2068
2069 case 0x00: /* INPUT_LATCH */
2070 case 0x10: /* KBR_LATCH */
2071 case 0x20: /* KBD_INT */
2072 case 0x24: /* GPIO_INT */
2073 case 0x34: /* GPIO_LATCH_REG */
2074 OMAP_RO_REG(addr);
2075 return;
2076
2077 default:
2078 OMAP_BAD_REG(addr);
2079 return;
2080 }
2081}
2082
e7aa0ae0
AK		 2083static const MemoryRegionOps omap_mpuio_ops = {
2084 .read = omap_mpuio_read,
2085 .write = omap_mpuio_write,
2086 .endianness = DEVICE_NATIVE_ENDIAN,
fe71e81a
AZ		 2087};
2088
9596ebb7 2089static void omap_mpuio_reset(struct omap_mpuio_s *s)
fe71e81a
AZ		 2090{
2091 s->inputs = 0;
2092 s->outputs = 0;
2093 s->dir = ~0;
2094 s->event = 0;
2095 s->edge = 0;
2096 s->kbd_mask = 0;
2097 s->mask = 0;
2098 s->debounce = 0;
2099 s->latch = 0;
2100 s->ints = 0;
2101 s->row_latch = 0x1f;
38a34e1d 2102 s->clk = 1;
fe71e81a
AZ		 2103}
2104
2105static void omap_mpuio_onoff(void *opaque, int line, int on)
2106{
2107 struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque;
2108
2109 s->clk = on;
2110 if (on)
2111 omap_mpuio_kbd_update(s);
2112}
2113
3b204c81 2114static struct omap_mpuio_s *omap_mpuio_init(MemoryRegion *memory,
a8170e5e 2115 hwaddr base,
fe71e81a
AZ		 2116 qemu_irq kbd_int, qemu_irq gpio_int, qemu_irq wakeup,
2117 omap_clk clk)
2118{
b45c03f5 2119 struct omap_mpuio_s *s = g_new0(struct omap_mpuio_s, 1);
fe71e81a 2120
fe71e81a
AZ		 2121 s->irq = gpio_int;
2122 s->kbd_irq = kbd_int;
2123 s->wakeup = wakeup;
2124 s->in = qemu_allocate_irqs(omap_mpuio_set, s, 16);
2125 omap_mpuio_reset(s);
2126
2c9b15ca 2127 memory_region_init_io(&s->iomem, NULL, &omap_mpuio_ops, s,
e7aa0ae0
AK		 2128 "omap-mpuio", 0x800);
2129 memory_region_add_subregion(memory, base, &s->iomem);
fe71e81a 2130
f3c7d038 2131 omap_clk_adduser(clk, qemu_allocate_irq(omap_mpuio_onoff, s, 0));
fe71e81a
AZ		 2132
2133 return s;
2134}
2135
2136qemu_irq *omap_mpuio_in_get(struct omap_mpuio_s *s)
2137{
2138 return s->in;
2139}
2140
2141void omap_mpuio_out_set(struct omap_mpuio_s *s, int line, qemu_irq handler)
2142{
2143 if (line >= 16 || line < 0)
a89f364a 2144 hw_error("%s: No GPIO line %i\n", __func__, line);
fe71e81a
AZ		 2145 s->handler[line] = handler;
2146}
2147
2148void omap_mpuio_key(struct omap_mpuio_s *s, int row, int col, int down)
2149{
2150 if (row >= 5 || row < 0)
a89f364a 2151 hw_error("%s: No key %i-%i\n", __func__, col, row);
fe71e81a
AZ		 2152
2153 if (down)
38a34e1d 2154 s->buttons[row] |= 1 << col;
fe71e81a 2155 else
38a34e1d 2156 s->buttons[row] &= ~(1 << col);
fe71e81a
AZ		 2157
2158 omap_mpuio_kbd_update(s);
2159}
2160
d951f6ff
AZ		 2161/* MicroWire Interface */
2162struct omap_uwire_s {
a4ebbd18 2163 MemoryRegion iomem;
d951f6ff
AZ		 2164 qemu_irq txirq;
2165 qemu_irq rxirq;
2166 qemu_irq txdrq;
2167
2168 uint16_t txbuf;
2169 uint16_t rxbuf;
2170 uint16_t control;
2171 uint16_t setup[5];
2172
bc24a225 2173 uWireSlave *chip[4];
d951f6ff
AZ		 2174};
2175
2176static void omap_uwire_transfer_start(struct omap_uwire_s *s)
2177{
2178 int chipselect = (s->control >> 10) & 3; /* INDEX */
bc24a225 2179 uWireSlave *slave = s->chip[chipselect];
d951f6ff
AZ		 2180
2181 if ((s->control >> 5) & 0x1f) { /* NB_BITS_WR */
2182 if (s->control & (1 << 12)) /* CS_CMD */
2183 if (slave && slave->send)
2184 slave->send(slave->opaque,
2185 s->txbuf >> (16 - ((s->control >> 5) & 0x1f)));
2186 s->control &= ~(1 << 14); /* CSRB */
2187 /* TODO: depending on s->setup[4] bits [1:0] assert an IRQ or
2188 * a DRQ. When is the level IRQ supposed to be reset? */
2189 }
2190
2191 if ((s->control >> 0) & 0x1f) { /* NB_BITS_RD */
2192 if (s->control & (1 << 12)) /* CS_CMD */
2193 if (slave && slave->receive)
2194 s->rxbuf = slave->receive(slave->opaque);
2195 s->control |= 1 << 15; /* RDRB */
2196 /* TODO: depending on s->setup[4] bits [1:0] assert an IRQ or
2197 * a DRQ. When is the level IRQ supposed to be reset? */
2198 }
2199}
2200
a8170e5e 2201static uint64_t omap_uwire_read(void *opaque, hwaddr addr,
a4ebbd18 2202 unsigned size)
d951f6ff
AZ		 2203{
2204 struct omap_uwire_s *s = (struct omap_uwire_s *) opaque;
cf965d24 2205 int offset = addr & OMAP_MPUI_REG_MASK;
d951f6ff 2206
a4ebbd18
AK		 2207 if (size != 2) {
2208 return omap_badwidth_read16(opaque, addr);
2209 }
2210
d951f6ff
AZ		 2211 switch (offset) {
2212 case 0x00: /* RDR */
2213 s->control &= ~(1 << 15); /* RDRB */
2214 return s->rxbuf;
2215
2216 case 0x04: /* CSR */
2217 return s->control;
2218
2219 case 0x08: /* SR1 */
2220 return s->setup[0];
2221 case 0x0c: /* SR2 */
2222 return s->setup[1];
2223 case 0x10: /* SR3 */
2224 return s->setup[2];
2225 case 0x14: /* SR4 */
2226 return s->setup[3];
2227 case 0x18: /* SR5 */
2228 return s->setup[4];
2229 }
2230
2231 OMAP_BAD_REG(addr);
2232 return 0;
2233}
2234
a8170e5e 2235static void omap_uwire_write(void *opaque, hwaddr addr,
a4ebbd18 2236 uint64_t value, unsigned size)
d951f6ff
AZ		 2237{
2238 struct omap_uwire_s *s = (struct omap_uwire_s *) opaque;
cf965d24 2239 int offset = addr & OMAP_MPUI_REG_MASK;
d951f6ff 2240
a4ebbd18 2241 if (size != 2) {
77a8257e
SW		 2242 omap_badwidth_write16(opaque, addr, value);
2243 return;
a4ebbd18
AK		 2244 }
2245
d951f6ff
AZ		 2246 switch (offset) {
2247 case 0x00: /* TDR */
2248 s->txbuf = value; /* TD */
d951f6ff
AZ		 2249 if ((s->setup[4] & (1 << 2)) && /* AUTO_TX_EN */
2250 ((s->setup[4] & (1 << 3)) || /* CS_TOGGLE_TX_EN */
cf965d24
AZ		 2251 (s->control & (1 << 12)))) { /* CS_CMD */
2252 s->control |= 1 << 14; /* CSRB */
d951f6ff 2253 omap_uwire_transfer_start(s);
cf965d24 2254 }
d951f6ff
AZ		 2255 break;
2256
2257 case 0x04: /* CSR */
2258 s->control = value & 0x1fff;
2259 if (value & (1 << 13)) /* START */
2260 omap_uwire_transfer_start(s);
2261 break;
2262
2263 case 0x08: /* SR1 */
2264 s->setup[0] = value & 0x003f;
2265 break;
2266
2267 case 0x0c: /* SR2 */
2268 s->setup[1] = value & 0x0fc0;
2269 break;
2270
2271 case 0x10: /* SR3 */
2272 s->setup[2] = value & 0x0003;
2273 break;
2274
2275 case 0x14: /* SR4 */
2276 s->setup[3] = value & 0x0001;
2277 break;
2278
2279 case 0x18: /* SR5 */
2280 s->setup[4] = value & 0x000f;
2281 break;
2282
2283 default:
2284 OMAP_BAD_REG(addr);
2285 return;
2286 }
2287}
2288
a4ebbd18
AK		 2289static const MemoryRegionOps omap_uwire_ops = {
2290 .read = omap_uwire_read,
2291 .write = omap_uwire_write,
2292 .endianness = DEVICE_NATIVE_ENDIAN,
d951f6ff
AZ		 2293};
2294
9596ebb7 2295static void omap_uwire_reset(struct omap_uwire_s *s)
d951f6ff 2296{
66450b15 2297 s->control = 0;
d951f6ff
AZ		 2298 s->setup[0] = 0;
2299 s->setup[1] = 0;
2300 s->setup[2] = 0;
2301 s->setup[3] = 0;
2302 s->setup[4] = 0;
2303}
2304
0919ac78 2305static struct omap_uwire_s *omap_uwire_init(MemoryRegion *system_memory,
a8170e5e 2306 hwaddr base,
0919ac78
PM		 2307 qemu_irq txirq, qemu_irq rxirq,
2308 qemu_irq dma,
2309 omap_clk clk)
d951f6ff 2310{
b45c03f5 2311 struct omap_uwire_s *s = g_new0(struct omap_uwire_s, 1);
d951f6ff 2312
0919ac78
PM		 2313 s->txirq = txirq;
2314 s->rxirq = rxirq;
d951f6ff
AZ		 2315 s->txdrq = dma;
2316 omap_uwire_reset(s);
2317
2c9b15ca 2318 memory_region_init_io(&s->iomem, NULL, &omap_uwire_ops, s, "omap-uwire", 0x800);
a4ebbd18 2319 memory_region_add_subregion(system_memory, base, &s->iomem);
d951f6ff
AZ		 2320
2321 return s;
2322}
2323
2324void omap_uwire_attach(struct omap_uwire_s *s,
bc24a225 2325 uWireSlave *slave, int chipselect)
d951f6ff 2326{
827df9f3 2327 if (chipselect < 0 || chipselect > 3) {
c0dbca36 2328 error_report("%s: Bad chipselect %i", __func__, chipselect);
827df9f3
AZ		 2329 exit(-1);
2330 }
d951f6ff
AZ		 2331
2332 s->chip[chipselect] = slave;
2333}
2334
66450b15 2335/* Pseudonoise Pulse-Width Light Modulator */
8717d88a
JR		 2336struct omap_pwl_s {
2337 MemoryRegion iomem;
2338 uint8_t output;
2339 uint8_t level;
2340 uint8_t enable;
2341 int clk;
2342};
2343
2344static void omap_pwl_update(struct omap_pwl_s *s)
66450b15 2345{
8717d88a 2346 int output = (s->clk && s->enable) ? s->level : 0;
66450b15 2347
8717d88a
JR		 2348 if (output != s->output) {
2349 s->output = output;
a89f364a 2350 printf("%s: Backlight now at %i/256\n", __func__, output);
66450b15
AZ		 2351 }
2352}
2353
a8170e5e 2354static uint64_t omap_pwl_read(void *opaque, hwaddr addr,
a4ebbd18 2355 unsigned size)
66450b15 2356{
8717d88a 2357 struct omap_pwl_s *s = (struct omap_pwl_s *) opaque;
cf965d24 2358 int offset = addr & OMAP_MPUI_REG_MASK;
66450b15 2359
a4ebbd18
AK		 2360 if (size != 1) {
2361 return omap_badwidth_read8(opaque, addr);
2362 }
2363
66450b15
AZ		 2364 switch (offset) {
2365 case 0x00: /* PWL_LEVEL */
8717d88a 2366 return s->level;
66450b15 2367 case 0x04: /* PWL_CTRL */
8717d88a 2368 return s->enable;
66450b15
AZ		 2369 }
2370 OMAP_BAD_REG(addr);
2371 return 0;
2372}
2373
a8170e5e 2374static void omap_pwl_write(void *opaque, hwaddr addr,
a4ebbd18 2375 uint64_t value, unsigned size)
66450b15 2376{
8717d88a 2377 struct omap_pwl_s *s = (struct omap_pwl_s *) opaque;
cf965d24 2378 int offset = addr & OMAP_MPUI_REG_MASK;
66450b15 2379
a4ebbd18 2380 if (size != 1) {
77a8257e
SW		 2381 omap_badwidth_write8(opaque, addr, value);
2382 return;
a4ebbd18
AK		 2383 }
2384
66450b15
AZ		 2385 switch (offset) {
2386 case 0x00: /* PWL_LEVEL */
8717d88a 2387 s->level = value;
66450b15
AZ		 2388 omap_pwl_update(s);
2389 break;
2390 case 0x04: /* PWL_CTRL */
8717d88a 2391 s->enable = value & 1;
66450b15
AZ		 2392 omap_pwl_update(s);
2393 break;
2394 default:
2395 OMAP_BAD_REG(addr);
2396 return;
2397 }
2398}
2399
a4ebbd18
AK		 2400static const MemoryRegionOps omap_pwl_ops = {
2401 .read = omap_pwl_read,
2402 .write = omap_pwl_write,
2403 .endianness = DEVICE_NATIVE_ENDIAN,
66450b15
AZ		 2404};
2405
8717d88a 2406static void omap_pwl_reset(struct omap_pwl_s *s)
66450b15 2407{
8717d88a
JR		 2408 s->output = 0;
2409 s->level = 0;
2410 s->enable = 0;
2411 s->clk = 1;
66450b15
AZ		 2412 omap_pwl_update(s);
2413}
2414
2415static void omap_pwl_clk_update(void *opaque, int line, int on)
2416{
8717d88a 2417 struct omap_pwl_s *s = (struct omap_pwl_s *) opaque;
66450b15 2418
8717d88a 2419 s->clk = on;
66450b15
AZ		 2420 omap_pwl_update(s);
2421}
2422
8717d88a 2423static struct omap_pwl_s *omap_pwl_init(MemoryRegion *system_memory,
a8170e5e 2424 hwaddr base,
8717d88a 2425 omap_clk clk)
66450b15 2426{
8717d88a
JR		 2427 struct omap_pwl_s *s = g_malloc0(sizeof(*s));
2428
66450b15
AZ		 2429 omap_pwl_reset(s);
2430
2c9b15ca 2431 memory_region_init_io(&s->iomem, NULL, &omap_pwl_ops, s,
a4ebbd18 2432 "omap-pwl", 0x800);
8717d88a 2433 memory_region_add_subregion(system_memory, base, &s->iomem);
66450b15 2434
f3c7d038 2435 omap_clk_adduser(clk, qemu_allocate_irq(omap_pwl_clk_update, s, 0));
8717d88a 2436 return s;
66450b15
AZ		 2437}
2438
f34c417b 2439/* Pulse-Width Tone module */
03759534
JR		 2440struct omap_pwt_s {
2441 MemoryRegion iomem;
2442 uint8_t frc;
2443 uint8_t vrc;
2444 uint8_t gcr;
2445 omap_clk clk;
2446};
2447
a8170e5e 2448static uint64_t omap_pwt_read(void *opaque, hwaddr addr,
a4ebbd18 2449 unsigned size)
f34c417b 2450{
03759534 2451 struct omap_pwt_s *s = (struct omap_pwt_s *) opaque;
cf965d24 2452 int offset = addr & OMAP_MPUI_REG_MASK;
f34c417b 2453
a4ebbd18
AK		 2454 if (size != 1) {
2455 return omap_badwidth_read8(opaque, addr);
2456 }
2457
f34c417b
AZ		 2458 switch (offset) {
2459 case 0x00: /* FRC */
03759534 2460 return s->frc;
f34c417b 2461 case 0x04: /* VCR */
03759534 2462 return s->vrc;
f34c417b 2463 case 0x08: /* GCR */
03759534 2464 return s->gcr;
f34c417b
AZ		 2465 }
2466 OMAP_BAD_REG(addr);
2467 return 0;
2468}
2469
a8170e5e 2470static void omap_pwt_write(void *opaque, hwaddr addr,
a4ebbd18 2471 uint64_t value, unsigned size)
f34c417b 2472{
03759534 2473 struct omap_pwt_s *s = (struct omap_pwt_s *) opaque;
cf965d24 2474 int offset = addr & OMAP_MPUI_REG_MASK;
f34c417b 2475
a4ebbd18 2476 if (size != 1) {
77a8257e
SW		 2477 omap_badwidth_write8(opaque, addr, value);
2478 return;
a4ebbd18
AK		 2479 }
2480
f34c417b
AZ		 2481 switch (offset) {
2482 case 0x00: /* FRC */
03759534 2483 s->frc = value & 0x3f;
f34c417b
AZ		 2484 break;
2485 case 0x04: /* VRC */
03759534 2486 if ((value ^ s->vrc) & 1) {
f34c417b 2487 if (value & 1)
a89f364a 2488 printf("%s: %iHz buzz on\n", __func__, (int)
f34c417b 2489 /* 1.5 MHz from a 12-MHz or 13-MHz PWT_CLK */
03759534 2490 ((omap_clk_getrate(s->clk) >> 3) /
f34c417b 2491 /* Pre-multiplexer divider */
03759534 2492 ((s->gcr & 2) ? 1 : 154) /
f34c417b
AZ		 2493 /* Octave multiplexer */
2494 (2 << (value & 3)) *
2495 /* 101/107 divider */
2496 ((value & (1 << 2)) ? 101 : 107) *
2497 /* 49/55 divider */
2498 ((value & (1 << 3)) ? 49 : 55) *
2499 /* 50/63 divider */
2500 ((value & (1 << 4)) ? 50 : 63) *
2501 /* 80/127 divider */
2502 ((value & (1 << 5)) ? 80 : 127) /
2503 (107 * 55 * 63 * 127)));
2504 else
a89f364a 2505 printf("%s: silence!\n", __func__);
f34c417b 2506 }
03759534 2507 s->vrc = value & 0x7f;
f34c417b
AZ		 2508 break;
2509 case 0x08: /* GCR */
03759534 2510 s->gcr = value & 3;
f34c417b
AZ		 2511 break;
2512 default:
2513 OMAP_BAD_REG(addr);
2514 return;
2515 }
2516}
2517
a4ebbd18
AK		 2518static const MemoryRegionOps omap_pwt_ops = {
2519 .read =omap_pwt_read,
2520 .write = omap_pwt_write,
2521 .endianness = DEVICE_NATIVE_ENDIAN,
f34c417b
AZ		 2522};
2523
03759534 2524static void omap_pwt_reset(struct omap_pwt_s *s)
f34c417b 2525{
03759534
JR		 2526 s->frc = 0;
2527 s->vrc = 0;
2528 s->gcr = 0;
f34c417b
AZ		 2529}
2530
03759534 2531static struct omap_pwt_s *omap_pwt_init(MemoryRegion *system_memory,
a8170e5e 2532 hwaddr base,
03759534 2533 omap_clk clk)
f34c417b 2534{
03759534
JR		 2535 struct omap_pwt_s *s = g_malloc0(sizeof(*s));
2536 s->clk = clk;
f34c417b
AZ		 2537 omap_pwt_reset(s);
2538
2c9b15ca 2539 memory_region_init_io(&s->iomem, NULL, &omap_pwt_ops, s,
a4ebbd18 2540 "omap-pwt", 0x800);
03759534
JR		 2541 memory_region_add_subregion(system_memory, base, &s->iomem);
2542 return s;
f34c417b
AZ		 2543}
2544
5c1c390f
AZ		 2545/* Real-time Clock module */
2546struct omap_rtc_s {
a4ebbd18 2547 MemoryRegion iomem;
5c1c390f
AZ		 2548 qemu_irq irq;
2549 qemu_irq alarm;
2550 QEMUTimer *clk;
2551
2552 uint8_t interrupts;
2553 uint8_t status;
2554 int16_t comp_reg;
2555 int running;
2556 int pm_am;
2557 int auto_comp;
2558 int round;
5c1c390f
AZ		 2559 struct tm alarm_tm;
2560 time_t alarm_ti;
2561
2562 struct tm current_tm;
2563 time_t ti;
2564 uint64_t tick;
2565};
2566
2567static void omap_rtc_interrupts_update(struct omap_rtc_s *s)
2568{
106627d0 2569 /* s->alarm is level-triggered */
5c1c390f
AZ		 2570 qemu_set_irq(s->alarm, (s->status >> 6) & 1);
2571}
2572
2573static void omap_rtc_alarm_update(struct omap_rtc_s *s)
2574{
0cd2df75 2575 s->alarm_ti = mktimegm(&s->alarm_tm);
5c1c390f 2576 if (s->alarm_ti == -1)
a89f364a 2577 printf("%s: conversion failed\n", __func__);
5c1c390f
AZ		 2578}
2579
a8170e5e 2580static uint64_t omap_rtc_read(void *opaque, hwaddr addr,
a4ebbd18 2581 unsigned size)
5c1c390f
AZ		 2582{
2583 struct omap_rtc_s *s = (struct omap_rtc_s *) opaque;
cf965d24 2584 int offset = addr & OMAP_MPUI_REG_MASK;
5c1c390f
AZ		 2585 uint8_t i;
2586
a4ebbd18
AK		 2587 if (size != 1) {
2588 return omap_badwidth_read8(opaque, addr);
2589 }
2590
5c1c390f
AZ		 2591 switch (offset) {
2592 case 0x00: /* SECONDS_REG */
abd0c6bd 2593 return to_bcd(s->current_tm.tm_sec);
5c1c390f
AZ		 2594
2595 case 0x04: /* MINUTES_REG */
abd0c6bd 2596 return to_bcd(s->current_tm.tm_min);
5c1c390f
AZ		 2597
2598 case 0x08: /* HOURS_REG */
2599 if (s->pm_am)
2600 return ((s->current_tm.tm_hour > 11) << 7) |
abd0c6bd 2601 to_bcd(((s->current_tm.tm_hour - 1) % 12) + 1);
5c1c390f 2602 else
abd0c6bd 2603 return to_bcd(s->current_tm.tm_hour);
5c1c390f
AZ		 2604
2605 case 0x0c: /* DAYS_REG */
abd0c6bd 2606 return to_bcd(s->current_tm.tm_mday);
5c1c390f
AZ		 2607
2608 case 0x10: /* MONTHS_REG */
abd0c6bd 2609 return to_bcd(s->current_tm.tm_mon + 1);
5c1c390f
AZ		 2610
2611 case 0x14: /* YEARS_REG */
abd0c6bd 2612 return to_bcd(s->current_tm.tm_year % 100);
5c1c390f
AZ		 2613
2614 case 0x18: /* WEEK_REG */
2615 return s->current_tm.tm_wday;
2616
2617 case 0x20: /* ALARM_SECONDS_REG */
abd0c6bd 2618 return to_bcd(s->alarm_tm.tm_sec);
5c1c390f
AZ		 2619
2620 case 0x24: /* ALARM_MINUTES_REG */
abd0c6bd 2621 return to_bcd(s->alarm_tm.tm_min);
5c1c390f
AZ		 2622
2623 case 0x28: /* ALARM_HOURS_REG */
2624 if (s->pm_am)
2625 return ((s->alarm_tm.tm_hour > 11) << 7) |
abd0c6bd 2626 to_bcd(((s->alarm_tm.tm_hour - 1) % 12) + 1);
5c1c390f 2627 else
abd0c6bd 2628 return to_bcd(s->alarm_tm.tm_hour);
5c1c390f
AZ		 2629
2630 case 0x2c: /* ALARM_DAYS_REG */
abd0c6bd 2631 return to_bcd(s->alarm_tm.tm_mday);
5c1c390f
AZ		 2632
2633 case 0x30: /* ALARM_MONTHS_REG */
abd0c6bd 2634 return to_bcd(s->alarm_tm.tm_mon + 1);
5c1c390f
AZ		 2635
2636 case 0x34: /* ALARM_YEARS_REG */
abd0c6bd 2637 return to_bcd(s->alarm_tm.tm_year % 100);
5c1c390f
AZ		 2638
2639 case 0x40: /* RTC_CTRL_REG */
2640 return (s->pm_am << 3) | (s->auto_comp << 2) |
2641 (s->round << 1) | s->running;
2642
2643 case 0x44: /* RTC_STATUS_REG */
2644 i = s->status;
2645 s->status &= ~0x3d;
2646 return i;
2647
2648 case 0x48: /* RTC_INTERRUPTS_REG */
2649 return s->interrupts;
2650
2651 case 0x4c: /* RTC_COMP_LSB_REG */
2652 return ((uint16_t) s->comp_reg) & 0xff;
2653
2654 case 0x50: /* RTC_COMP_MSB_REG */
2655 return ((uint16_t) s->comp_reg) >> 8;
2656 }
2657
2658 OMAP_BAD_REG(addr);
2659 return 0;
2660}
2661
a8170e5e 2662static void omap_rtc_write(void *opaque, hwaddr addr,
a4ebbd18 2663 uint64_t value, unsigned size)
5c1c390f
AZ		 2664{
2665 struct omap_rtc_s *s = (struct omap_rtc_s *) opaque;
cf965d24 2666 int offset = addr & OMAP_MPUI_REG_MASK;
5c1c390f
AZ		 2667 struct tm new_tm;
2668 time_t ti[2];
2669
a4ebbd18 2670 if (size != 1) {
77a8257e
SW		 2671 omap_badwidth_write8(opaque, addr, value);
2672 return;
a4ebbd18
AK		 2673 }
2674
5c1c390f
AZ		 2675 switch (offset) {
2676 case 0x00: /* SECONDS_REG */
eb38c52c 2677#ifdef ALMDEBUG
5c1c390f
AZ		 2678 printf("RTC SEC_REG <-- %02x\n", value);
2679#endif
2680 s->ti -= s->current_tm.tm_sec;
abd0c6bd 2681 s->ti += from_bcd(value);
5c1c390f
AZ		 2682 return;
2683
2684 case 0x04: /* MINUTES_REG */
eb38c52c 2685#ifdef ALMDEBUG
5c1c390f
AZ		 2686 printf("RTC MIN_REG <-- %02x\n", value);
2687#endif
2688 s->ti -= s->current_tm.tm_min * 60;
abd0c6bd 2689 s->ti += from_bcd(value) * 60;
5c1c390f
AZ		 2690 return;
2691
2692 case 0x08: /* HOURS_REG */
eb38c52c 2693#ifdef ALMDEBUG
5c1c390f
AZ		 2694 printf("RTC HRS_REG <-- %02x\n", value);
2695#endif
2696 s->ti -= s->current_tm.tm_hour * 3600;
2697 if (s->pm_am) {
abd0c6bd 2698 s->ti += (from_bcd(value & 0x3f) & 12) * 3600;
5c1c390f
AZ		 2699 s->ti += ((value >> 7) & 1) * 43200;
2700 } else
abd0c6bd 2701 s->ti += from_bcd(value & 0x3f) * 3600;
5c1c390f
AZ		 2702 return;
2703
2704 case 0x0c: /* DAYS_REG */
eb38c52c 2705#ifdef ALMDEBUG
5c1c390f
AZ		 2706 printf("RTC DAY_REG <-- %02x\n", value);
2707#endif
2708 s->ti -= s->current_tm.tm_mday * 86400;
abd0c6bd 2709 s->ti += from_bcd(value) * 86400;
5c1c390f
AZ		 2710 return;
2711
2712 case 0x10: /* MONTHS_REG */
eb38c52c 2713#ifdef ALMDEBUG
5c1c390f
AZ		 2714 printf("RTC MTH_REG <-- %02x\n", value);
2715#endif
2716 memcpy(&new_tm, &s->current_tm, sizeof(new_tm));
abd0c6bd 2717 new_tm.tm_mon = from_bcd(value);
0cd2df75
AJ		 2718 ti[0] = mktimegm(&s->current_tm);
2719 ti[1] = mktimegm(&new_tm);
5c1c390f
AZ		 2720
2721 if (ti[0] != -1 && ti[1] != -1) {
2722 s->ti -= ti[0];
2723 s->ti += ti[1];
2724 } else {
2725 /* A less accurate version */
2726 s->ti -= s->current_tm.tm_mon * 2592000;
abd0c6bd 2727 s->ti += from_bcd(value) * 2592000;
5c1c390f
AZ		 2728 }
2729 return;
2730
2731 case 0x14: /* YEARS_REG */
eb38c52c 2732#ifdef ALMDEBUG
5c1c390f
AZ		 2733 printf("RTC YRS_REG <-- %02x\n", value);
2734#endif
2735 memcpy(&new_tm, &s->current_tm, sizeof(new_tm));
abd0c6bd 2736 new_tm.tm_year += from_bcd(value) - (new_tm.tm_year % 100);
0cd2df75
AJ		 2737 ti[0] = mktimegm(&s->current_tm);
2738 ti[1] = mktimegm(&new_tm);
5c1c390f
AZ		 2739
2740 if (ti[0] != -1 && ti[1] != -1) {
2741 s->ti -= ti[0];
2742 s->ti += ti[1];
2743 } else {
2744 /* A less accurate version */
7e7e5858
PM		 2745 s->ti -= (time_t)(s->current_tm.tm_year % 100) * 31536000;
2746 s->ti += (time_t)from_bcd(value) * 31536000;
5c1c390f
AZ		 2747 }
2748 return;
2749
2750 case 0x18: /* WEEK_REG */
2751 return; /* Ignored */
2752
2753 case 0x20: /* ALARM_SECONDS_REG */
eb38c52c 2754#ifdef ALMDEBUG
5c1c390f
AZ		 2755 printf("ALM SEC_REG <-- %02x\n", value);
2756#endif
abd0c6bd 2757 s->alarm_tm.tm_sec = from_bcd(value);
5c1c390f
AZ		 2758 omap_rtc_alarm_update(s);
2759 return;
2760
2761 case 0x24: /* ALARM_MINUTES_REG */
eb38c52c 2762#ifdef ALMDEBUG
5c1c390f
AZ		 2763 printf("ALM MIN_REG <-- %02x\n", value);
2764#endif
abd0c6bd 2765 s->alarm_tm.tm_min = from_bcd(value);
5c1c390f
AZ		 2766 omap_rtc_alarm_update(s);
2767 return;
2768
2769 case 0x28: /* ALARM_HOURS_REG */
eb38c52c 2770#ifdef ALMDEBUG
5c1c390f
AZ		 2771 printf("ALM HRS_REG <-- %02x\n", value);
2772#endif
2773 if (s->pm_am)
2774 s->alarm_tm.tm_hour =
abd0c6bd 2775 ((from_bcd(value & 0x3f)) % 12) +
5c1c390f
AZ		 2776 ((value >> 7) & 1) * 12;
2777 else
abd0c6bd 2778 s->alarm_tm.tm_hour = from_bcd(value);
5c1c390f
AZ		 2779 omap_rtc_alarm_update(s);
2780 return;
2781
2782 case 0x2c: /* ALARM_DAYS_REG */
eb38c52c 2783#ifdef ALMDEBUG
5c1c390f
AZ		 2784 printf("ALM DAY_REG <-- %02x\n", value);
2785#endif
abd0c6bd 2786 s->alarm_tm.tm_mday = from_bcd(value);
5c1c390f
AZ		 2787 omap_rtc_alarm_update(s);
2788 return;
2789
2790 case 0x30: /* ALARM_MONTHS_REG */
eb38c52c 2791#ifdef ALMDEBUG
5c1c390f
AZ		 2792 printf("ALM MON_REG <-- %02x\n", value);
2793#endif
abd0c6bd 2794 s->alarm_tm.tm_mon = from_bcd(value);
5c1c390f
AZ		 2795 omap_rtc_alarm_update(s);
2796 return;
2797
2798 case 0x34: /* ALARM_YEARS_REG */
eb38c52c 2799#ifdef ALMDEBUG
5c1c390f
AZ		 2800 printf("ALM YRS_REG <-- %02x\n", value);
2801#endif
abd0c6bd 2802 s->alarm_tm.tm_year = from_bcd(value);
5c1c390f
AZ		 2803 omap_rtc_alarm_update(s);
2804 return;
2805
2806 case 0x40: /* RTC_CTRL_REG */
eb38c52c 2807#ifdef ALMDEBUG
5c1c390f
AZ		 2808 printf("RTC CONTROL <-- %02x\n", value);
2809#endif
2810 s->pm_am = (value >> 3) & 1;
2811 s->auto_comp = (value >> 2) & 1;
2812 s->round = (value >> 1) & 1;
2813 s->running = value & 1;
2814 s->status &= 0xfd;
2815 s->status |= s->running << 1;
2816 return;
2817
2818 case 0x44: /* RTC_STATUS_REG */
eb38c52c 2819#ifdef ALMDEBUG
5c1c390f
AZ		 2820 printf("RTC STATUSL <-- %02x\n", value);
2821#endif
2822 s->status &= ~((value & 0xc0) ^ 0x80);
2823 omap_rtc_interrupts_update(s);
2824 return;
2825
2826 case 0x48: /* RTC_INTERRUPTS_REG */
eb38c52c 2827#ifdef ALMDEBUG
5c1c390f
AZ		 2828 printf("RTC INTRS <-- %02x\n", value);
2829#endif
2830 s->interrupts = value;
2831 return;
2832
2833 case 0x4c: /* RTC_COMP_LSB_REG */
eb38c52c 2834#ifdef ALMDEBUG
5c1c390f
AZ		 2835 printf("RTC COMPLSB <-- %02x\n", value);
2836#endif
2837 s->comp_reg &= 0xff00;
2838 s->comp_reg |= 0x00ff & value;
2839 return;
2840
2841 case 0x50: /* RTC_COMP_MSB_REG */
eb38c52c 2842#ifdef ALMDEBUG
5c1c390f
AZ		 2843 printf("RTC COMPMSB <-- %02x\n", value);
2844#endif
2845 s->comp_reg &= 0x00ff;
2846 s->comp_reg |= 0xff00 & (value << 8);
2847 return;
2848
2849 default:
2850 OMAP_BAD_REG(addr);
2851 return;
2852 }
2853}
2854
a4ebbd18
AK		 2855static const MemoryRegionOps omap_rtc_ops = {
2856 .read = omap_rtc_read,
2857 .write = omap_rtc_write,
2858 .endianness = DEVICE_NATIVE_ENDIAN,
5c1c390f
AZ		 2859};
2860
2861static void omap_rtc_tick(void *opaque)
2862{
2863 struct omap_rtc_s *s = opaque;
2864
2865 if (s->round) {
2866 /* Round to nearest full minute. */
2867 if (s->current_tm.tm_sec < 30)
2868 s->ti -= s->current_tm.tm_sec;
2869 else
2870 s->ti += 60 - s->current_tm.tm_sec;
2871
2872 s->round = 0;
2873 }
2874
eb7ff6fb 2875 localtime_r(&s->ti, &s->current_tm);
5c1c390f
AZ		 2876
2877 if ((s->interrupts & 0x08) && s->ti == s->alarm_ti) {
2878 s->status |= 0x40;
2879 omap_rtc_interrupts_update(s);
2880 }
2881
2882 if (s->interrupts & 0x04)
2883 switch (s->interrupts & 3) {
2884 case 0:
2885 s->status |= 0x04;
106627d0 2886 qemu_irq_pulse(s->irq);
5c1c390f
AZ		 2887 break;
2888 case 1:
2889 if (s->current_tm.tm_sec)
2890 break;
2891 s->status |= 0x08;
106627d0 2892 qemu_irq_pulse(s->irq);
5c1c390f
AZ		 2893 break;
2894 case 2:
2895 if (s->current_tm.tm_sec || s->current_tm.tm_min)
2896 break;
2897 s->status |= 0x10;
106627d0 2898 qemu_irq_pulse(s->irq);
5c1c390f
AZ		 2899 break;
2900 case 3:
2901 if (s->current_tm.tm_sec ||
2902 s->current_tm.tm_min || s->current_tm.tm_hour)
2903 break;
2904 s->status |= 0x20;
106627d0 2905 qemu_irq_pulse(s->irq);
5c1c390f
AZ		 2906 break;
2907 }
2908
2909 /* Move on */
2910 if (s->running)
2911 s->ti ++;
2912 s->tick += 1000;
2913
2914 /*
2915 * Every full hour add a rough approximation of the compensation
2916 * register to the 32kHz Timer (which drives the RTC) value.
2917 */
2918 if (s->auto_comp && !s->current_tm.tm_sec && !s->current_tm.tm_min)
2919 s->tick += s->comp_reg * 1000 / 32768;
2920
bc72ad67 2921 timer_mod(s->clk, s->tick);
5c1c390f
AZ		 2922}
2923
9596ebb7 2924static void omap_rtc_reset(struct omap_rtc_s *s)
5c1c390f 2925{
f6503059
AZ		 2926 struct tm tm;
2927
5c1c390f
AZ		 2928 s->interrupts = 0;
2929 s->comp_reg = 0;
2930 s->running = 0;
2931 s->pm_am = 0;
2932 s->auto_comp = 0;
2933 s->round = 0;
884f17c2 2934 s->tick = qemu_clock_get_ms(rtc_clock);
5c1c390f
AZ		 2935 memset(&s->alarm_tm, 0, sizeof(s->alarm_tm));
2936 s->alarm_tm.tm_mday = 0x01;
2937 s->status = 1 << 7;
f6503059 2938 qemu_get_timedate(&tm, 0);
0cd2df75 2939 s->ti = mktimegm(&tm);
5c1c390f
AZ		 2940
2941 omap_rtc_alarm_update(s);
2942 omap_rtc_tick(s);
2943}
2944
a4ebbd18 2945static struct omap_rtc_s *omap_rtc_init(MemoryRegion *system_memory,
a8170e5e 2946 hwaddr base,
0919ac78
PM		 2947 qemu_irq timerirq, qemu_irq alarmirq,
2948 omap_clk clk)
5c1c390f 2949{
b45c03f5 2950 struct omap_rtc_s *s = g_new0(struct omap_rtc_s, 1);
5c1c390f 2951
0919ac78
PM		 2952 s->irq = timerirq;
2953 s->alarm = alarmirq;
884f17c2 2954 s->clk = timer_new_ms(rtc_clock, omap_rtc_tick, s);
5c1c390f
AZ		 2955
2956 omap_rtc_reset(s);
2957
2c9b15ca 2958 memory_region_init_io(&s->iomem, NULL, &omap_rtc_ops, s,
a4ebbd18
AK		 2959 "omap-rtc", 0x800);
2960 memory_region_add_subregion(system_memory, base, &s->iomem);
5c1c390f
AZ		 2961
2962 return s;
2963}
2964
d8f699cb
AZ		 2965/* Multi-channel Buffered Serial Port interfaces */
2966struct omap_mcbsp_s {
a4ebbd18 2967 MemoryRegion iomem;
d8f699cb
AZ		 2968 qemu_irq txirq;
2969 qemu_irq rxirq;
2970 qemu_irq txdrq;
2971 qemu_irq rxdrq;
2972
2973 uint16_t spcr[2];
2974 uint16_t rcr[2];
2975 uint16_t xcr[2];
2976 uint16_t srgr[2];
2977 uint16_t mcr[2];
2978 uint16_t pcr;
2979 uint16_t rcer[8];
2980 uint16_t xcer[8];
2981 int tx_rate;
2982 int rx_rate;
2983 int tx_req;
73560bc8 2984 int rx_req;
d8f699cb 2985
bc24a225 2986 I2SCodec *codec;
73560bc8
AZ		 2987 QEMUTimer *source_timer;
2988 QEMUTimer *sink_timer;
d8f699cb
AZ		 2989};
2990
2991static void omap_mcbsp_intr_update(struct omap_mcbsp_s *s)
2992{
2993 int irq;
2994
2995 switch ((s->spcr[0] >> 4) & 3) { /* RINTM */
2996 case 0:
2997 irq = (s->spcr[0] >> 1) & 1; /* RRDY */
2998 break;
2999 case 3:
3000 irq = (s->spcr[0] >> 3) & 1; /* RSYNCERR */
3001 break;
3002 default:
3003 irq = 0;
3004 break;
3005 }
3006
106627d0
AZ		 3007 if (irq)
3008 qemu_irq_pulse(s->rxirq);
d8f699cb
AZ		 3009
3010 switch ((s->spcr[1] >> 4) & 3) { /* XINTM */
3011 case 0:
3012 irq = (s->spcr[1] >> 1) & 1; /* XRDY */
3013 break;
3014 case 3:
3015 irq = (s->spcr[1] >> 3) & 1; /* XSYNCERR */
3016 break;
3017 default:
3018 irq = 0;
3019 break;
3020 }
3021
106627d0
AZ		 3022 if (irq)
3023 qemu_irq_pulse(s->txirq);
d8f699cb
AZ		 3024}
3025
73560bc8 3026static void omap_mcbsp_rx_newdata(struct omap_mcbsp_s *s)
d8f699cb 3027{
73560bc8
AZ		 3028 if ((s->spcr[0] >> 1) & 1) /* RRDY */
3029 s->spcr[0] |= 1 << 2; /* RFULL */
3030 s->spcr[0] |= 1 << 1; /* RRDY */
3031 qemu_irq_raise(s->rxdrq);
3032 omap_mcbsp_intr_update(s);
d8f699cb
AZ		 3033}
3034
73560bc8 3035static void omap_mcbsp_source_tick(void *opaque)
d8f699cb 3036{
73560bc8
AZ		 3037 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
3038 static const int bps[8] = { 0, 1, 1, 2, 2, 2, -255, -255 };
3039
3040 if (!s->rx_rate)
d8f699cb 3041 return;
73560bc8 3042 if (s->rx_req)
a89f364a 3043 printf("%s: Rx FIFO overrun\n", __func__);
d8f699cb 3044
73560bc8 3045 s->rx_req = s->rx_rate << bps[(s->rcr[0] >> 5) & 7];
d8f699cb 3046
73560bc8 3047 omap_mcbsp_rx_newdata(s);
bc72ad67 3048 timer_mod(s->source_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
73bcb24d 3049 NANOSECONDS_PER_SECOND);
d8f699cb
AZ		 3050}
3051
3052static void omap_mcbsp_rx_start(struct omap_mcbsp_s *s)
3053{
73560bc8
AZ		 3054 if (!s->codec || !s->codec->rts)
3055 omap_mcbsp_source_tick(s);
3056 else if (s->codec->in.len) {
3057 s->rx_req = s->codec->in.len;
3058 omap_mcbsp_rx_newdata(s);
d8f699cb 3059 }
d8f699cb
AZ		 3060}
3061
3062static void omap_mcbsp_rx_stop(struct omap_mcbsp_s *s)
73560bc8 3063{
bc72ad67 3064 timer_del(s->source_timer);
73560bc8
AZ		 3065}
3066
3067static void omap_mcbsp_rx_done(struct omap_mcbsp_s *s)
d8f699cb
AZ		 3068{
3069 s->spcr[0] &= ~(1 << 1); /* RRDY */
3070 qemu_irq_lower(s->rxdrq);
3071 omap_mcbsp_intr_update(s);
3072}
3073
73560bc8
AZ		 3074static void omap_mcbsp_tx_newdata(struct omap_mcbsp_s *s)
3075{
3076 s->spcr[1] |= 1 << 1; /* XRDY */
3077 qemu_irq_raise(s->txdrq);
3078 omap_mcbsp_intr_update(s);
3079}
3080
3081static void omap_mcbsp_sink_tick(void *opaque)
d8f699cb 3082{
73560bc8
AZ		 3083 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
3084 static const int bps[8] = { 0, 1, 1, 2, 2, 2, -255, -255 };
3085
3086 if (!s->tx_rate)
d8f699cb 3087 return;
73560bc8 3088 if (s->tx_req)
a89f364a 3089 printf("%s: Tx FIFO underrun\n", __func__);
73560bc8
AZ		 3090
3091 s->tx_req = s->tx_rate << bps[(s->xcr[0] >> 5) & 7];
3092
3093 omap_mcbsp_tx_newdata(s);
bc72ad67 3094 timer_mod(s->sink_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
73bcb24d 3095 NANOSECONDS_PER_SECOND);
73560bc8
AZ		 3096}
3097
3098static void omap_mcbsp_tx_start(struct omap_mcbsp_s *s)
3099{
3100 if (!s->codec || !s->codec->cts)
3101 omap_mcbsp_sink_tick(s);
3102 else if (s->codec->out.size) {
3103 s->tx_req = s->codec->out.size;
3104 omap_mcbsp_tx_newdata(s);
3105 }
3106}
3107
3108static void omap_mcbsp_tx_done(struct omap_mcbsp_s *s)
3109{
3110 s->spcr[1] &= ~(1 << 1); /* XRDY */
3111 qemu_irq_lower(s->txdrq);
3112 omap_mcbsp_intr_update(s);
3113 if (s->codec && s->codec->cts)
3114 s->codec->tx_swallow(s->codec->opaque);
d8f699cb
AZ		 3115}
3116
3117static void omap_mcbsp_tx_stop(struct omap_mcbsp_s *s)
3118{
73560bc8
AZ		 3119 s->tx_req = 0;
3120 omap_mcbsp_tx_done(s);
bc72ad67 3121 timer_del(s->sink_timer);
73560bc8
AZ		 3122}
3123
3124static void omap_mcbsp_req_update(struct omap_mcbsp_s *s)
3125{
3126 int prev_rx_rate, prev_tx_rate;
3127 int rx_rate = 0, tx_rate = 0;
3128 int cpu_rate = 1500000; /* XXX */
3129
3130 /* TODO: check CLKSTP bit */
3131 if (s->spcr[1] & (1 << 6)) { /* GRST */
3132 if (s->spcr[0] & (1 << 0)) { /* RRST */
3133 if ((s->srgr[1] & (1 << 13)) && /* CLKSM */
3134 (s->pcr & (1 << 8))) { /* CLKRM */
3135 if (~s->pcr & (1 << 7)) /* SCLKME */
3136 rx_rate = cpu_rate /
3137 ((s->srgr[0] & 0xff) + 1); /* CLKGDV */
3138 } else
3139 if (s->codec)
3140 rx_rate = s->codec->rx_rate;
3141 }
3142
3143 if (s->spcr[1] & (1 << 0)) { /* XRST */
3144 if ((s->srgr[1] & (1 << 13)) && /* CLKSM */
3145 (s->pcr & (1 << 9))) { /* CLKXM */
3146 if (~s->pcr & (1 << 7)) /* SCLKME */
3147 tx_rate = cpu_rate /
3148 ((s->srgr[0] & 0xff) + 1); /* CLKGDV */
3149 } else
3150 if (s->codec)
3151 tx_rate = s->codec->tx_rate;
3152 }
3153 }
3154 prev_tx_rate = s->tx_rate;
3155 prev_rx_rate = s->rx_rate;
3156 s->tx_rate = tx_rate;
3157 s->rx_rate = rx_rate;
3158
3159 if (s->codec)
3160 s->codec->set_rate(s->codec->opaque, rx_rate, tx_rate);
3161
3162 if (!prev_tx_rate && tx_rate)
3163 omap_mcbsp_tx_start(s);
3164 else if (s->tx_rate && !tx_rate)
3165 omap_mcbsp_tx_stop(s);
3166
3167 if (!prev_rx_rate && rx_rate)
3168 omap_mcbsp_rx_start(s);
3169 else if (prev_tx_rate && !tx_rate)
3170 omap_mcbsp_rx_stop(s);
d8f699cb
AZ		 3171}
3172
a8170e5e 3173static uint64_t omap_mcbsp_read(void *opaque, hwaddr addr,
a4ebbd18 3174 unsigned size)
d8f699cb
AZ		 3175{
3176 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
3177 int offset = addr & OMAP_MPUI_REG_MASK;
3178 uint16_t ret;
3179
a4ebbd18
AK		 3180 if (size != 2) {
3181 return omap_badwidth_read16(opaque, addr);
3182 }
3183
d8f699cb
AZ		 3184 switch (offset) {
3185 case 0x00: /* DRR2 */
3186 if (((s->rcr[0] >> 5) & 7) < 3) /* RWDLEN1 */
3187 return 0x0000;
3188 /* Fall through. */
3189 case 0x02: /* DRR1 */
73560bc8 3190 if (s->rx_req < 2) {
a89f364a 3191 printf("%s: Rx FIFO underrun\n", __func__);
73560bc8 3192 omap_mcbsp_rx_done(s);
d8f699cb 3193 } else {
73560bc8
AZ		 3194 s->tx_req -= 2;
3195 if (s->codec && s->codec->in.len >= 2) {
3196 ret = s->codec->in.fifo[s->codec->in.start ++] << 8;
3197 ret |= s->codec->in.fifo[s->codec->in.start ++];
3198 s->codec->in.len -= 2;
3199 } else
3200 ret = 0x0000;
3201 if (!s->tx_req)
3202 omap_mcbsp_rx_done(s);
d8f699cb
AZ		 3203 return ret;
3204 }
3205 return 0x0000;
3206
3207 case 0x04: /* DXR2 */
3208 case 0x06: /* DXR1 */
3209 return 0x0000;
3210
3211 case 0x08: /* SPCR2 */
3212 return s->spcr[1];
3213 case 0x0a: /* SPCR1 */
3214 return s->spcr[0];
3215 case 0x0c: /* RCR2 */
3216 return s->rcr[1];
3217 case 0x0e: /* RCR1 */
3218 return s->rcr[0];
3219 case 0x10: /* XCR2 */
3220 return s->xcr[1];
3221 case 0x12: /* XCR1 */
3222 return s->xcr[0];
3223 case 0x14: /* SRGR2 */
3224 return s->srgr[1];
3225 case 0x16: /* SRGR1 */
3226 return s->srgr[0];
3227 case 0x18: /* MCR2 */
3228 return s->mcr[1];
3229 case 0x1a: /* MCR1 */
3230 return s->mcr[0];
3231 case 0x1c: /* RCERA */
3232 return s->rcer[0];
3233 case 0x1e: /* RCERB */
3234 return s->rcer[1];
3235 case 0x20: /* XCERA */
3236 return s->xcer[0];
3237 case 0x22: /* XCERB */
3238 return s->xcer[1];
3239 case 0x24: /* PCR0 */
3240 return s->pcr;
3241 case 0x26: /* RCERC */
3242 return s->rcer[2];
3243 case 0x28: /* RCERD */
3244 return s->rcer[3];
3245 case 0x2a: /* XCERC */
3246 return s->xcer[2];
3247 case 0x2c: /* XCERD */
3248 return s->xcer[3];
3249 case 0x2e: /* RCERE */
3250 return s->rcer[4];
3251 case 0x30: /* RCERF */
3252 return s->rcer[5];
3253 case 0x32: /* XCERE */
3254 return s->xcer[4];
3255 case 0x34: /* XCERF */
3256 return s->xcer[5];
3257 case 0x36: /* RCERG */
3258 return s->rcer[6];
3259 case 0x38: /* RCERH */
3260 return s->rcer[7];
3261 case 0x3a: /* XCERG */
3262 return s->xcer[6];
3263 case 0x3c: /* XCERH */
3264 return s->xcer[7];
3265 }
3266
3267 OMAP_BAD_REG(addr);
3268 return 0;
3269}
3270
a8170e5e 3271static void omap_mcbsp_writeh(void *opaque, hwaddr addr,
d8f699cb
AZ		 3272 uint32_t value)
3273{
3274 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
3275 int offset = addr & OMAP_MPUI_REG_MASK;
3276
3277 switch (offset) {
3278 case 0x00: /* DRR2 */
3279 case 0x02: /* DRR1 */
3280 OMAP_RO_REG(addr);
3281 return;
3282
3283 case 0x04: /* DXR2 */
3284 if (((s->xcr[0] >> 5) & 7) < 3) /* XWDLEN1 */
3285 return;
3286 /* Fall through. */
3287 case 0x06: /* DXR1 */
73560bc8
AZ		 3288 if (s->tx_req > 1) {
3289 s->tx_req -= 2;
3290 if (s->codec && s->codec->cts) {
d8f699cb
AZ		 3291 s->codec->out.fifo[s->codec->out.len ++] = (value >> 8) & 0xff;
3292 s->codec->out.fifo[s->codec->out.len ++] = (value >> 0) & 0xff;
d8f699cb 3293 }
73560bc8
AZ		 3294 if (s->tx_req < 2)
3295 omap_mcbsp_tx_done(s);
d8f699cb 3296 } else
a89f364a 3297 printf("%s: Tx FIFO overrun\n", __func__);
d8f699cb
AZ		 3298 return;
3299
3300 case 0x08: /* SPCR2 */
3301 s->spcr[1] &= 0x0002;
3302 s->spcr[1] |= 0x03f9 & value;
3303 s->spcr[1] |= 0x0004 & (value << 2); /* XEMPTY := XRST */
73560bc8 3304 if (~value & 1) /* XRST */
d8f699cb 3305 s->spcr[1] &= ~6;
d8f699cb
AZ		 3306 omap_mcbsp_req_update(s);
3307 return;
3308 case 0x0a: /* SPCR1 */
3309 s->spcr[0] &= 0x0006;
3310 s->spcr[0] |= 0xf8f9 & value;
3311 if (value & (1 << 15)) /* DLB */
a89f364a 3312 printf("%s: Digital Loopback mode enable attempt\n", __func__);
d8f699cb
AZ		 3313 if (~value & 1) { /* RRST */
3314 s->spcr[0] &= ~6;
73560bc8
AZ		 3315 s->rx_req = 0;
3316 omap_mcbsp_rx_done(s);
d8f699cb 3317 }
d8f699cb
AZ		 3318 omap_mcbsp_req_update(s);
3319 return;
3320
3321 case 0x0c: /* RCR2 */
3322 s->rcr[1] = value & 0xffff;
3323 return;
3324 case 0x0e: /* RCR1 */
3325 s->rcr[0] = value & 0x7fe0;
3326 return;
3327 case 0x10: /* XCR2 */
3328 s->xcr[1] = value & 0xffff;
3329 return;
3330 case 0x12: /* XCR1 */
3331 s->xcr[0] = value & 0x7fe0;
3332 return;
3333 case 0x14: /* SRGR2 */
3334 s->srgr[1] = value & 0xffff;
73560bc8 3335 omap_mcbsp_req_update(s);
d8f699cb
AZ		 3336 return;
3337 case 0x16: /* SRGR1 */
3338 s->srgr[0] = value & 0xffff;
73560bc8 3339 omap_mcbsp_req_update(s);
d8f699cb
AZ		 3340 return;
3341 case 0x18: /* MCR2 */
3342 s->mcr[1] = value & 0x03e3;
3343 if (value & 3) /* XMCM */
c94a60cb 3344 printf("%s: Tx channel selection mode enable attempt\n", __func__);
d8f699cb
AZ		 3345 return;
3346 case 0x1a: /* MCR1 */
3347 s->mcr[0] = value & 0x03e1;
3348 if (value & 1) /* RMCM */
c94a60cb 3349 printf("%s: Rx channel selection mode enable attempt\n", __func__);
d8f699cb
AZ		 3350 return;
3351 case 0x1c: /* RCERA */
3352 s->rcer[0] = value & 0xffff;
3353 return;
3354 case 0x1e: /* RCERB */
3355 s->rcer[1] = value & 0xffff;
3356 return;
3357 case 0x20: /* XCERA */
3358 s->xcer[0] = value & 0xffff;
3359 return;
3360 case 0x22: /* XCERB */
3361 s->xcer[1] = value & 0xffff;
3362 return;
3363 case 0x24: /* PCR0 */
3364 s->pcr = value & 0x7faf;
3365 return;
3366 case 0x26: /* RCERC */
3367 s->rcer[2] = value & 0xffff;
3368 return;
3369 case 0x28: /* RCERD */
3370 s->rcer[3] = value & 0xffff;
3371 return;
3372 case 0x2a: /* XCERC */
3373 s->xcer[2] = value & 0xffff;
3374 return;
3375 case 0x2c: /* XCERD */
3376 s->xcer[3] = value & 0xffff;
3377 return;
3378 case 0x2e: /* RCERE */
3379 s->rcer[4] = value & 0xffff;
3380 return;
3381 case 0x30: /* RCERF */
3382 s->rcer[5] = value & 0xffff;
3383 return;
3384 case 0x32: /* XCERE */
3385 s->xcer[4] = value & 0xffff;
3386 return;
3387 case 0x34: /* XCERF */
3388 s->xcer[5] = value & 0xffff;
3389 return;
3390 case 0x36: /* RCERG */
3391 s->rcer[6] = value & 0xffff;
3392 return;
3393 case 0x38: /* RCERH */
3394 s->rcer[7] = value & 0xffff;
3395 return;
3396 case 0x3a: /* XCERG */
3397 s->xcer[6] = value & 0xffff;
3398 return;
3399 case 0x3c: /* XCERH */
3400 s->xcer[7] = value & 0xffff;
3401 return;
3402 }
3403
3404 OMAP_BAD_REG(addr);
3405}
3406
a8170e5e 3407static void omap_mcbsp_writew(void *opaque, hwaddr addr,
73560bc8
AZ		 3408 uint32_t value)
3409{
3410 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
3411 int offset = addr & OMAP_MPUI_REG_MASK;
3412
3413 if (offset == 0x04) { /* DXR */
3414 if (((s->xcr[0] >> 5) & 7) < 3) /* XWDLEN1 */
3415 return;
3416 if (s->tx_req > 3) {
3417 s->tx_req -= 4;
3418 if (s->codec && s->codec->cts) {
3419 s->codec->out.fifo[s->codec->out.len ++] =
3420 (value >> 24) & 0xff;
3421 s->codec->out.fifo[s->codec->out.len ++] =
3422 (value >> 16) & 0xff;
3423 s->codec->out.fifo[s->codec->out.len ++] =
3424 (value >> 8) & 0xff;
3425 s->codec->out.fifo[s->codec->out.len ++] =
3426 (value >> 0) & 0xff;
3427 }
3428 if (s->tx_req < 4)
3429 omap_mcbsp_tx_done(s);
3430 } else
a89f364a 3431 printf("%s: Tx FIFO overrun\n", __func__);
73560bc8
AZ		 3432 return;
3433 }
3434
3435 omap_badwidth_write16(opaque, addr, value);
3436}
3437
a8170e5e 3438static void omap_mcbsp_write(void *opaque, hwaddr addr,
a4ebbd18
AK		 3439 uint64_t value, unsigned size)
3440{
3441 switch (size) {
77a8257e
SW		 3442 case 2:
3443 omap_mcbsp_writeh(opaque, addr, value);
3444 break;
3445 case 4:
3446 omap_mcbsp_writew(opaque, addr, value);
3447 break;
3448 default:
3449 omap_badwidth_write16(opaque, addr, value);
a4ebbd18
AK		 3450 }
3451}
d8f699cb 3452
a4ebbd18
AK		 3453static const MemoryRegionOps omap_mcbsp_ops = {
3454 .read = omap_mcbsp_read,
3455 .write = omap_mcbsp_write,
3456 .endianness = DEVICE_NATIVE_ENDIAN,
d8f699cb
AZ		 3457};
3458
3459static void omap_mcbsp_reset(struct omap_mcbsp_s *s)
3460{
3461 memset(&s->spcr, 0, sizeof(s->spcr));
3462 memset(&s->rcr, 0, sizeof(s->rcr));
3463 memset(&s->xcr, 0, sizeof(s->xcr));
3464 s->srgr[0] = 0x0001;
3465 s->srgr[1] = 0x2000;
3466 memset(&s->mcr, 0, sizeof(s->mcr));
3467 memset(&s->pcr, 0, sizeof(s->pcr));
3468 memset(&s->rcer, 0, sizeof(s->rcer));
3469 memset(&s->xcer, 0, sizeof(s->xcer));
3470 s->tx_req = 0;
73560bc8 3471 s->rx_req = 0;
d8f699cb
AZ		 3472 s->tx_rate = 0;
3473 s->rx_rate = 0;
bc72ad67
AB		 3474 timer_del(s->source_timer);
3475 timer_del(s->sink_timer);
d8f699cb
AZ		 3476}
3477
0919ac78 3478static struct omap_mcbsp_s *omap_mcbsp_init(MemoryRegion *system_memory,
a8170e5e 3479 hwaddr base,
0919ac78
PM		 3480 qemu_irq txirq, qemu_irq rxirq,
3481 qemu_irq *dma, omap_clk clk)
d8f699cb 3482{
b45c03f5 3483 struct omap_mcbsp_s *s = g_new0(struct omap_mcbsp_s, 1);
d8f699cb 3484
0919ac78
PM		 3485 s->txirq = txirq;
3486 s->rxirq = rxirq;
d8f699cb
AZ		 3487 s->txdrq = dma[0];
3488 s->rxdrq = dma[1];
bc72ad67
AB		 3489 s->sink_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, omap_mcbsp_sink_tick, s);
3490 s->source_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, omap_mcbsp_source_tick, s);
d8f699cb
AZ		 3491 omap_mcbsp_reset(s);
3492
2c9b15ca 3493 memory_region_init_io(&s->iomem, NULL, &omap_mcbsp_ops, s, "omap-mcbsp", 0x800);
a4ebbd18 3494 memory_region_add_subregion(system_memory, base, &s->iomem);
d8f699cb
AZ		 3495
3496 return s;
3497}
3498
9596ebb7 3499static void omap_mcbsp_i2s_swallow(void *opaque, int line, int level)
d8f699cb
AZ		 3500{
3501 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
3502
73560bc8
AZ		 3503 if (s->rx_rate) {
3504 s->rx_req = s->codec->in.len;
3505 omap_mcbsp_rx_newdata(s);
3506 }
d8f699cb
AZ		 3507}
3508
9596ebb7 3509static void omap_mcbsp_i2s_start(void *opaque, int line, int level)
d8f699cb
AZ		 3510{
3511 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
3512
73560bc8
AZ		 3513 if (s->tx_rate) {
3514 s->tx_req = s->codec->out.size;
3515 omap_mcbsp_tx_newdata(s);
3516 }
d8f699cb
AZ		 3517}
3518
bc24a225 3519void omap_mcbsp_i2s_attach(struct omap_mcbsp_s *s, I2SCodec *slave)
d8f699cb
AZ		 3520{
3521 s->codec = slave;
f3c7d038
AF		 3522 slave->rx_swallow = qemu_allocate_irq(omap_mcbsp_i2s_swallow, s, 0);
3523 slave->tx_start = qemu_allocate_irq(omap_mcbsp_i2s_start, s, 0);
d8f699cb
AZ		 3524}
3525
f9d43072
AZ		 3526/* LED Pulse Generators */
3527struct omap_lpg_s {
60fe76e3 3528 MemoryRegion iomem;
f9d43072
AZ		 3529 QEMUTimer *tm;
3530
3531 uint8_t control;
3532 uint8_t power;
3533 int64_t on;
3534 int64_t period;
3535 int clk;
3536 int cycle;
3537};
3538
3539static void omap_lpg_tick(void *opaque)
3540{
3541 struct omap_lpg_s *s = opaque;
3542
3543 if (s->cycle)
bc72ad67 3544 timer_mod(s->tm, qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + s->period - s->on);
f9d43072 3545 else
bc72ad67 3546 timer_mod(s->tm, qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + s->on);
f9d43072
AZ		 3547
3548 s->cycle = !s->cycle;
a89f364a 3549 printf("%s: LED is %s\n", __func__, s->cycle ? "on" : "off");
f9d43072
AZ		 3550}
3551
3552static void omap_lpg_update(struct omap_lpg_s *s)
3553{
3554 int64_t on, period = 1, ticks = 1000;
3555 static const int per[8] = { 1, 2, 4, 8, 12, 16, 20, 24 };
3556
3557 if (~s->control & (1 << 6)) /* LPGRES */
3558 on = 0;
3559 else if (s->control & (1 << 7)) /* PERM_ON */
3560 on = period;
3561 else {
3562 period = muldiv64(ticks, per[s->control & 7], /* PERCTRL */
3563 256 / 32);
3564 on = (s->clk && s->power) ? muldiv64(ticks,
3565 per[(s->control >> 3) & 7], 256) : 0; /* ONCTRL */
3566 }
3567
bc72ad67 3568 timer_del(s->tm);
f9d43072 3569 if (on == period && s->on < s->period)
a89f364a 3570 printf("%s: LED is on\n", __func__);
f9d43072 3571 else if (on == 0 && s->on)
a89f364a 3572 printf("%s: LED is off\n", __func__);
f9d43072
AZ		 3573 else if (on && (on != s->on || period != s->period)) {
3574 s->cycle = 0;
3575 s->on = on;
3576 s->period = period;
3577 omap_lpg_tick(s);
3578 return;
3579 }
3580
3581 s->on = on;
3582 s->period = period;
3583}
3584
3585static void omap_lpg_reset(struct omap_lpg_s *s)
3586{
3587 s->control = 0x00;
3588 s->power = 0x00;
3589 s->clk = 1;
3590 omap_lpg_update(s);
3591}
3592
a8170e5e 3593static uint64_t omap_lpg_read(void *opaque, hwaddr addr,
60fe76e3 3594 unsigned size)
f9d43072
AZ		 3595{
3596 struct omap_lpg_s *s = (struct omap_lpg_s *) opaque;
3597 int offset = addr & OMAP_MPUI_REG_MASK;
3598
60fe76e3
AK		 3599 if (size != 1) {
3600 return omap_badwidth_read8(opaque, addr);
3601 }
3602
f9d43072
AZ		 3603 switch (offset) {
3604 case 0x00: /* LCR */
3605 return s->control;
3606
3607 case 0x04: /* PMR */
3608 return s->power;
3609 }
3610
3611 OMAP_BAD_REG(addr);
3612 return 0;
3613}
3614
a8170e5e 3615static void omap_lpg_write(void *opaque, hwaddr addr,
60fe76e3 3616 uint64_t value, unsigned size)
f9d43072
AZ		 3617{
3618 struct omap_lpg_s *s = (struct omap_lpg_s *) opaque;
3619 int offset = addr & OMAP_MPUI_REG_MASK;
3620
60fe76e3 3621 if (size != 1) {
77a8257e
SW		 3622 omap_badwidth_write8(opaque, addr, value);
3623 return;
60fe76e3
AK		 3624 }
3625
f9d43072
AZ		 3626 switch (offset) {
3627 case 0x00: /* LCR */
3628 if (~value & (1 << 6)) /* LPGRES */
3629 omap_lpg_reset(s);
3630 s->control = value & 0xff;
3631 omap_lpg_update(s);
3632 return;
3633
3634 case 0x04: /* PMR */
3635 s->power = value & 0x01;
3636 omap_lpg_update(s);
3637 return;
3638
3639 default:
3640 OMAP_BAD_REG(addr);
3641 return;
3642 }
3643}
3644
60fe76e3
AK		 3645static const MemoryRegionOps omap_lpg_ops = {
3646 .read = omap_lpg_read,
3647 .write = omap_lpg_write,
3648 .endianness = DEVICE_NATIVE_ENDIAN,
f9d43072
AZ		 3649};
3650
3651static void omap_lpg_clk_update(void *opaque, int line, int on)
3652{
3653 struct omap_lpg_s *s = (struct omap_lpg_s *) opaque;
3654
3655 s->clk = on;
3656 omap_lpg_update(s);
3657}
3658
60fe76e3 3659static struct omap_lpg_s *omap_lpg_init(MemoryRegion *system_memory,
a8170e5e 3660 hwaddr base, omap_clk clk)
f9d43072 3661{
b45c03f5 3662 struct omap_lpg_s *s = g_new0(struct omap_lpg_s, 1);
f9d43072 3663
bc72ad67 3664 s->tm = timer_new_ms(QEMU_CLOCK_VIRTUAL, omap_lpg_tick, s);
f9d43072
AZ		 3665
3666 omap_lpg_reset(s);
3667
2c9b15ca 3668 memory_region_init_io(&s->iomem, NULL, &omap_lpg_ops, s, "omap-lpg", 0x800);
60fe76e3 3669 memory_region_add_subregion(system_memory, base, &s->iomem);
f9d43072 3670
f3c7d038 3671 omap_clk_adduser(clk, qemu_allocate_irq(omap_lpg_clk_update, s, 0));
f9d43072
AZ		 3672
3673 return s;
3674}
3675
3676/* MPUI Peripheral Bridge configuration */
a8170e5e 3677static uint64_t omap_mpui_io_read(void *opaque, hwaddr addr,
60fe76e3 3678 unsigned size)
f9d43072 3679{
60fe76e3
AK		 3680 if (size != 2) {
3681 return omap_badwidth_read16(opaque, addr);
3682 }
3683
f9d43072
AZ		 3684 if (addr == OMAP_MPUI_BASE) /* CMR */
3685 return 0xfe4d;
3686
3687 OMAP_BAD_REG(addr);
3688 return 0;
3689}
3690
a8170e5e 3691static void omap_mpui_io_write(void *opaque, hwaddr addr,
60fe76e3
AK		 3692 uint64_t value, unsigned size)
3693{
3694 /* FIXME: infinite loop */
3695 omap_badwidth_write16(opaque, addr, value);
3696}
f9d43072 3697
60fe76e3
AK		 3698static const MemoryRegionOps omap_mpui_io_ops = {
3699 .read = omap_mpui_io_read,
3700 .write = omap_mpui_io_write,
3701 .endianness = DEVICE_NATIVE_ENDIAN,
f9d43072
AZ		 3702};
3703
60fe76e3
AK		 3704static void omap_setup_mpui_io(MemoryRegion *system_memory,
3705 struct omap_mpu_state_s *mpu)
f9d43072 3706{
2c9b15ca 3707 memory_region_init_io(&mpu->mpui_io_iomem, NULL, &omap_mpui_io_ops, mpu,
60fe76e3
AK		 3708 "omap-mpui-io", 0x7fff);
3709 memory_region_add_subregion(system_memory, OMAP_MPUI_BASE,
3710 &mpu->mpui_io_iomem);
f9d43072
AZ		 3711}
3712
c3d2689d 3713/* General chip reset */
827df9f3 3714static void omap1_mpu_reset(void *opaque)
c3d2689d
AZ		 3715{
3716 struct omap_mpu_state_s *mpu = (struct omap_mpu_state_s *) opaque;
3717
c3d2689d
AZ		 3718 omap_dma_reset(mpu->dma);
3719 omap_mpu_timer_reset(mpu->timer[0]);
3720 omap_mpu_timer_reset(mpu->timer[1]);
3721 omap_mpu_timer_reset(mpu->timer[2]);
3722 omap_wd_timer_reset(mpu->wdt);
3723 omap_os_timer_reset(mpu->os_timer);
3724 omap_lcdc_reset(mpu->lcd);
3725 omap_ulpd_pm_reset(mpu);
3726 omap_pin_cfg_reset(mpu);
3727 omap_mpui_reset(mpu);
3728 omap_tipb_bridge_reset(mpu->private_tipb);
3729 omap_tipb_bridge_reset(mpu->public_tipb);
b9f7bc40
JR		 3730 omap_dpll_reset(mpu->dpll[0]);
3731 omap_dpll_reset(mpu->dpll[1]);
3732 omap_dpll_reset(mpu->dpll[2]);
d951f6ff
AZ		 3733 omap_uart_reset(mpu->uart[0]);
3734 omap_uart_reset(mpu->uart[1]);
3735 omap_uart_reset(mpu->uart[2]);
b30bb3a2 3736 omap_mmc_reset(mpu->mmc);
fe71e81a 3737 omap_mpuio_reset(mpu->mpuio);
d951f6ff 3738 omap_uwire_reset(mpu->microwire);
8717d88a 3739 omap_pwl_reset(mpu->pwl);
03759534 3740 omap_pwt_reset(mpu->pwt);
5c1c390f 3741 omap_rtc_reset(mpu->rtc);
d8f699cb
AZ		 3742 omap_mcbsp_reset(mpu->mcbsp1);
3743 omap_mcbsp_reset(mpu->mcbsp2);
3744 omap_mcbsp_reset(mpu->mcbsp3);
f9d43072
AZ		 3745 omap_lpg_reset(mpu->led[0]);
3746 omap_lpg_reset(mpu->led[1]);
8ef6367e 3747 omap_clkm_reset(mpu);
5f4ef08b 3748 cpu_reset(CPU(mpu->cpu));
c3d2689d
AZ		 3749}
3750
cf965d24 3751static const struct omap_map_s {
a8170e5e
AK		 3752 hwaddr phys_dsp;
3753 hwaddr phys_mpu;
cf965d24
AZ		 3754 uint32_t size;
3755 const char *name;
3756} omap15xx_dsp_mm[] = {
3757 /* Strobe 0 */
3758 { 0xe1010000, 0xfffb0000, 0x800, "UART1 BT" }, /* CS0 */
3759 { 0xe1010800, 0xfffb0800, 0x800, "UART2 COM" }, /* CS1 */
3760 { 0xe1011800, 0xfffb1800, 0x800, "McBSP1 audio" }, /* CS3 */
3761 { 0xe1012000, 0xfffb2000, 0x800, "MCSI2 communication" }, /* CS4 */
3762 { 0xe1012800, 0xfffb2800, 0x800, "MCSI1 BT u-Law" }, /* CS5 */
3763 { 0xe1013000, 0xfffb3000, 0x800, "uWire" }, /* CS6 */
3764 { 0xe1013800, 0xfffb3800, 0x800, "I^2C" }, /* CS7 */
3765 { 0xe1014000, 0xfffb4000, 0x800, "USB W2FC" }, /* CS8 */
3766 { 0xe1014800, 0xfffb4800, 0x800, "RTC" }, /* CS9 */
3767 { 0xe1015000, 0xfffb5000, 0x800, "MPUIO" }, /* CS10 */
3768 { 0xe1015800, 0xfffb5800, 0x800, "PWL" }, /* CS11 */
3769 { 0xe1016000, 0xfffb6000, 0x800, "PWT" }, /* CS12 */
3770 { 0xe1017000, 0xfffb7000, 0x800, "McBSP3" }, /* CS14 */
3771 { 0xe1017800, 0xfffb7800, 0x800, "MMC" }, /* CS15 */
3772 { 0xe1019000, 0xfffb9000, 0x800, "32-kHz timer" }, /* CS18 */
3773 { 0xe1019800, 0xfffb9800, 0x800, "UART3" }, /* CS19 */
3774 { 0xe101c800, 0xfffbc800, 0x800, "TIPB switches" }, /* CS25 */
3775 /* Strobe 1 */
3776 { 0xe101e000, 0xfffce000, 0x800, "GPIOs" }, /* CS28 */
3777
3778 { 0 }
3779};
3780
763b946c
AK		 3781static void omap_setup_dsp_mapping(MemoryRegion *system_memory,
3782 const struct omap_map_s *map)
cf965d24 3783{
763b946c 3784 MemoryRegion *io;
cf965d24
AZ		 3785
3786 for (; map->phys_dsp; map ++) {
763b946c 3787 io = g_new(MemoryRegion, 1);
2c9b15ca 3788 memory_region_init_alias(io, NULL, map->name,
763b946c
AK		 3789 system_memory, map->phys_mpu, map->size);
3790 memory_region_add_subregion(system_memory, map->phys_dsp, io);
cf965d24
AZ		 3791 }
3792}
3793
827df9f3 3794void omap_mpu_wakeup(void *opaque, int irq, int req)
c3d2689d
AZ		 3795{
3796 struct omap_mpu_state_s *mpu = (struct omap_mpu_state_s *) opaque;
259186a7 3797 CPUState *cpu = CPU(mpu->cpu);
c3d2689d 3798
259186a7 3799 if (cpu->halted) {
c3affe56 3800 cpu_interrupt(cpu, CPU_INTERRUPT_EXITTB);
5f4ef08b 3801 }
c3d2689d
AZ		 3802}
3803
827df9f3 3804static const struct dma_irq_map omap1_dma_irq_map[] = {
089b7c0a
AZ		 3805 { 0, OMAP_INT_DMA_CH0_6 },
3806 { 0, OMAP_INT_DMA_CH1_7 },
3807 { 0, OMAP_INT_DMA_CH2_8 },
3808 { 0, OMAP_INT_DMA_CH3 },
3809 { 0, OMAP_INT_DMA_CH4 },
3810 { 0, OMAP_INT_DMA_CH5 },
3811 { 1, OMAP_INT_1610_DMA_CH6 },
3812 { 1, OMAP_INT_1610_DMA_CH7 },
3813 { 1, OMAP_INT_1610_DMA_CH8 },
3814 { 1, OMAP_INT_1610_DMA_CH9 },
3815 { 1, OMAP_INT_1610_DMA_CH10 },
3816 { 1, OMAP_INT_1610_DMA_CH11 },
3817 { 1, OMAP_INT_1610_DMA_CH12 },
3818 { 1, OMAP_INT_1610_DMA_CH13 },
3819 { 1, OMAP_INT_1610_DMA_CH14 },
3820 { 1, OMAP_INT_1610_DMA_CH15 }
3821};
3822
b4e3104b
AZ		 3823/* DMA ports for OMAP1 */
3824static int omap_validate_emiff_addr(struct omap_mpu_state_s *s,
a8170e5e 3825 hwaddr addr)
b4e3104b 3826{
45416789 3827 return range_covers_byte(OMAP_EMIFF_BASE, s->sdram_size, addr);
b4e3104b
AZ		 3828}
3829
3830static int omap_validate_emifs_addr(struct omap_mpu_state_s *s,
a8170e5e 3831 hwaddr addr)
b4e3104b 3832{
45416789
BS		 3833 return range_covers_byte(OMAP_EMIFS_BASE, OMAP_EMIFF_BASE - OMAP_EMIFS_BASE,
3834 addr);
b4e3104b
AZ		 3835}
3836
3837static int omap_validate_imif_addr(struct omap_mpu_state_s *s,
a8170e5e 3838 hwaddr addr)
b4e3104b 3839{
45416789 3840 return range_covers_byte(OMAP_IMIF_BASE, s->sram_size, addr);
b4e3104b
AZ		 3841}
3842
3843static int omap_validate_tipb_addr(struct omap_mpu_state_s *s,
a8170e5e 3844 hwaddr addr)
b4e3104b 3845{
45416789 3846 return range_covers_byte(0xfffb0000, 0xffff0000 - 0xfffb0000, addr);
b4e3104b
AZ		 3847}
3848
3849static int omap_validate_local_addr(struct omap_mpu_state_s *s,
a8170e5e 3850 hwaddr addr)
b4e3104b 3851{
45416789 3852 return range_covers_byte(OMAP_LOCALBUS_BASE, 0x1000000, addr);
b4e3104b
AZ		 3853}
3854
3855static int omap_validate_tipb_mpui_addr(struct omap_mpu_state_s *s,
a8170e5e 3856 hwaddr addr)
b4e3104b 3857{
45416789 3858 return range_covers_byte(0xe1010000, 0xe1020004 - 0xe1010000, addr);
b4e3104b
AZ		 3859}
3860
4387b253 3861struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *dram,
ba1ba5cc 3862 const char *cpu_type)
c3d2689d 3863{
089b7c0a 3864 int i;
b45c03f5 3865 struct omap_mpu_state_s *s = g_new0(struct omap_mpu_state_s, 1);
089b7c0a 3866 qemu_irq dma_irqs[6];
751c6a17 3867 DriveInfo *dinfo;
0919ac78 3868 SysBusDevice *busdev;
4387b253 3869 MemoryRegion *system_memory = get_system_memory();
106627d0 3870
c3d2689d
AZ		 3871 /* Core */
3872 s->mpu_model = omap310;
ba1ba5cc 3873 s->cpu = ARM_CPU(cpu_create(cpu_type));
4387b253 3874 s->sdram_size = memory_region_size(dram);
c3d2689d
AZ		 3875 s->sram_size = OMAP15XX_SRAM_SIZE;
3876
f3c7d038 3877 s->wakeup = qemu_allocate_irq(omap_mpu_wakeup, s, 0);
fe71e81a 3878
c3d2689d
AZ		 3879 /* Clocks */
3880 omap_clk_init(s);
3881
3882 /* Memory-mapped stuff */
98a99ce0 3883 memory_region_init_ram(&s->imif_ram, NULL, "omap1.sram", s->sram_size,
f8ed85ac 3884 &error_fatal);
2654c962 3885 memory_region_add_subregion(system_memory, OMAP_IMIF_BASE, &s->imif_ram);
c3d2689d 3886
e7aa0ae0 3887 omap_clkm_init(system_memory, 0xfffece00, 0xe1008000, s);
c3d2689d 3888
3e80f690 3889 s->ih[0] = qdev_new("omap-intc");
0919ac78 3890 qdev_prop_set_uint32(s->ih[0], "size", 0x100);
bab592a2 3891 omap_intc_set_iclk(OMAP_INTC(s->ih[0]), omap_findclk(s, "arminth_ck"));
1356b98d 3892 busdev = SYS_BUS_DEVICE(s->ih[0]);
3c6ef471 3893 sysbus_realize_and_unref(busdev, &error_fatal);
437f0f10
PM		 3894 sysbus_connect_irq(busdev, 0,
3895 qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_IRQ));
3896 sysbus_connect_irq(busdev, 1,
3897 qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_FIQ));
0919ac78 3898 sysbus_mmio_map(busdev, 0, 0xfffecb00);
3e80f690 3899 s->ih[1] = qdev_new("omap-intc");
0919ac78 3900 qdev_prop_set_uint32(s->ih[1], "size", 0x800);
bab592a2 3901 omap_intc_set_iclk(OMAP_INTC(s->ih[1]), omap_findclk(s, "arminth_ck"));
1356b98d 3902 busdev = SYS_BUS_DEVICE(s->ih[1]);
3c6ef471 3903 sysbus_realize_and_unref(busdev, &error_fatal);
0919ac78
PM		 3904 sysbus_connect_irq(busdev, 0,
3905 qdev_get_gpio_in(s->ih[0], OMAP_INT_15XX_IH2_IRQ));
3906 /* The second interrupt controller's FIQ output is not wired up */
3907 sysbus_mmio_map(busdev, 0, 0xfffe0000);
3908
3909 for (i = 0; i < 6; i++) {
3910 dma_irqs[i] = qdev_get_gpio_in(s->ih[omap1_dma_irq_map[i].ih],
3911 omap1_dma_irq_map[i].intr);
3912 }
7405165e 3913 s->dma = omap_dma_init(0xfffed800, dma_irqs, system_memory,
0919ac78 3914 qdev_get_gpio_in(s->ih[0], OMAP_INT_DMA_LCD),
089b7c0a
AZ		 3915 s, omap_findclk(s, "dma_ck"), omap_dma_3_1);
3916
c3d2689d
AZ		 3917 s->port[emiff ].addr_valid = omap_validate_emiff_addr;
3918 s->port[emifs ].addr_valid = omap_validate_emifs_addr;
3919 s->port[imif ].addr_valid = omap_validate_imif_addr;
3920 s->port[tipb ].addr_valid = omap_validate_tipb_addr;
3921 s->port[local ].addr_valid = omap_validate_local_addr;
3922 s->port[tipb_mpui].addr_valid = omap_validate_tipb_mpui_addr;
3923
afbb5194 3924 /* Register SDRAM and SRAM DMA ports for fast transfers. */
4387b253 3925 soc_dma_port_add_mem(s->dma, memory_region_get_ram_ptr(dram),
2654c962
AK		 3926 OMAP_EMIFF_BASE, s->sdram_size);
3927 soc_dma_port_add_mem(s->dma, memory_region_get_ram_ptr(&s->imif_ram),
90aeba9d 3928 OMAP_IMIF_BASE, s->sram_size);
afbb5194 3929
4b3fedf3 3930 s->timer[0] = omap_mpu_timer_init(system_memory, 0xfffec500,
0919ac78 3931 qdev_get_gpio_in(s->ih[0], OMAP_INT_TIMER1),
c3d2689d 3932 omap_findclk(s, "mputim_ck"));
4b3fedf3 3933 s->timer[1] = omap_mpu_timer_init(system_memory, 0xfffec600,
0919ac78 3934 qdev_get_gpio_in(s->ih[0], OMAP_INT_TIMER2),
c3d2689d 3935 omap_findclk(s, "mputim_ck"));
4b3fedf3 3936 s->timer[2] = omap_mpu_timer_init(system_memory, 0xfffec700,
0919ac78 3937 qdev_get_gpio_in(s->ih[0], OMAP_INT_TIMER3),
c3d2689d
AZ		 3938 omap_findclk(s, "mputim_ck"));
3939
4b3fedf3 3940 s->wdt = omap_wd_timer_init(system_memory, 0xfffec800,
0919ac78 3941 qdev_get_gpio_in(s->ih[0], OMAP_INT_WD_TIMER),
c3d2689d
AZ		 3942 omap_findclk(s, "armwdt_ck"));
3943
4b3fedf3 3944 s->os_timer = omap_os_timer_init(system_memory, 0xfffb9000,
0919ac78 3945 qdev_get_gpio_in(s->ih[1], OMAP_INT_OS_TIMER),
c3d2689d
AZ		 3946 omap_findclk(s, "clk32-kHz"));
3947
30af1ec7 3948 s->lcd = omap_lcdc_init(system_memory, 0xfffec000,
0919ac78
PM		 3949 qdev_get_gpio_in(s->ih[0], OMAP_INT_LCD_CTRL),
3950 omap_dma_get_lcdch(s->dma),
3951 omap_findclk(s, "lcd_ck"));
c3d2689d 3952
4b3fedf3
AK		 3953 omap_ulpd_pm_init(system_memory, 0xfffe0800, s);
3954 omap_pin_cfg_init(system_memory, 0xfffe1000, s);
3955 omap_id_init(system_memory, s);
c3d2689d 3956
4b3fedf3 3957 omap_mpui_init(system_memory, 0xfffec900, s);
c3d2689d 3958
4b3fedf3 3959 s->private_tipb = omap_tipb_bridge_init(system_memory, 0xfffeca00,
0919ac78 3960 qdev_get_gpio_in(s->ih[0], OMAP_INT_BRIDGE_PRIV),
c3d2689d 3961 omap_findclk(s, "tipb_ck"));
4b3fedf3 3962 s->public_tipb = omap_tipb_bridge_init(system_memory, 0xfffed300,
0919ac78 3963 qdev_get_gpio_in(s->ih[0], OMAP_INT_BRIDGE_PUB),
c3d2689d
AZ		 3964 omap_findclk(s, "tipb_ck"));
3965
e7aa0ae0 3966 omap_tcmi_init(system_memory, 0xfffecc00, s);
c3d2689d 3967
0919ac78
PM		 3968 s->uart[0] = omap_uart_init(0xfffb0000,
3969 qdev_get_gpio_in(s->ih[1], OMAP_INT_UART1),
c3d2689d 3970 omap_findclk(s, "uart1_ck"),
827df9f3
AZ		 3971 omap_findclk(s, "uart1_ck"),
3972 s->drq[OMAP_DMA_UART1_TX], s->drq[OMAP_DMA_UART1_RX],
6a8aabd3 3973 "uart1",
9bca0edb 3974 serial_hd(0));
0919ac78
PM		 3975 s->uart[1] = omap_uart_init(0xfffb0800,
3976 qdev_get_gpio_in(s->ih[1], OMAP_INT_UART2),
c3d2689d 3977 omap_findclk(s, "uart2_ck"),
827df9f3
AZ		 3978 omap_findclk(s, "uart2_ck"),
3979 s->drq[OMAP_DMA_UART2_TX], s->drq[OMAP_DMA_UART2_RX],
6a8aabd3 3980 "uart2",
9bca0edb 3981 serial_hd(0) ? serial_hd(1) : NULL);
0919ac78
PM		 3982 s->uart[2] = omap_uart_init(0xfffb9800,
3983 qdev_get_gpio_in(s->ih[0], OMAP_INT_UART3),
c3d2689d 3984 omap_findclk(s, "uart3_ck"),
827df9f3
AZ		 3985 omap_findclk(s, "uart3_ck"),
3986 s->drq[OMAP_DMA_UART3_TX], s->drq[OMAP_DMA_UART3_RX],
6a8aabd3 3987 "uart3",
9bca0edb 3988 serial_hd(0) && serial_hd(1) ? serial_hd(2) : NULL);
c3d2689d 3989
b9f7bc40
JR		 3990 s->dpll[0] = omap_dpll_init(system_memory, 0xfffecf00,
3991 omap_findclk(s, "dpll1"));
3992 s->dpll[1] = omap_dpll_init(system_memory, 0xfffed000,
3993 omap_findclk(s, "dpll2"));
3994 s->dpll[2] = omap_dpll_init(system_memory, 0xfffed100,
3995 omap_findclk(s, "dpll3"));
c3d2689d 3996
751c6a17 3997 dinfo = drive_get(IF_SD, 0, 0);
a82929a2
TH		 3998 if (!dinfo && !qtest_enabled()) {
3999 warn_report("missing SecureDigital device");
e4bcb14c 4000 }
fa1d36df 4001 s->mmc = omap_mmc_init(0xfffb7800, system_memory,
a82929a2 4002 dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
0919ac78
PM		 4003 qdev_get_gpio_in(s->ih[1], OMAP_INT_OQN),
4004 &s->drq[OMAP_DMA_MMC_TX],
9d413d1d 4005 omap_findclk(s, "mmc_ck"));
b30bb3a2 4006
e7aa0ae0 4007 s->mpuio = omap_mpuio_init(system_memory, 0xfffb5000,
0919ac78
PM		 4008 qdev_get_gpio_in(s->ih[1], OMAP_INT_KEYBOARD),
4009 qdev_get_gpio_in(s->ih[1], OMAP_INT_MPUIO),
4010 s->wakeup, omap_findclk(s, "clk32-kHz"));
fe71e81a 4011
3e80f690 4012 s->gpio = qdev_new("omap-gpio");
77831c20 4013 qdev_prop_set_int32(s->gpio, "mpu_model", s->mpu_model);
ba2aba83 4014 omap_gpio_set_clk(OMAP1_GPIO(s->gpio), omap_findclk(s, "arm_gpio_ck"));
3c6ef471 4015 sysbus_realize_and_unref(SYS_BUS_DEVICE(s->gpio), &error_fatal);
1356b98d 4016 sysbus_connect_irq(SYS_BUS_DEVICE(s->gpio), 0,
0919ac78 4017 qdev_get_gpio_in(s->ih[0], OMAP_INT_GPIO_BANK1));
1356b98d 4018 sysbus_mmio_map(SYS_BUS_DEVICE(s->gpio), 0, 0xfffce000);
64330148 4019
0919ac78
PM		 4020 s->microwire = omap_uwire_init(system_memory, 0xfffb3000,
4021 qdev_get_gpio_in(s->ih[1], OMAP_INT_uWireTX),
4022 qdev_get_gpio_in(s->ih[1], OMAP_INT_uWireRX),
d951f6ff
AZ		 4023 s->drq[OMAP_DMA_UWIRE_TX], omap_findclk(s, "mpuper_ck"));
4024
8717d88a
JR		 4025 s->pwl = omap_pwl_init(system_memory, 0xfffb5800,
4026 omap_findclk(s, "armxor_ck"));
03759534
JR		 4027 s->pwt = omap_pwt_init(system_memory, 0xfffb6000,
4028 omap_findclk(s, "armxor_ck"));
66450b15 4029
3e80f690 4030 s->i2c[0] = qdev_new("omap_i2c");
54e17933 4031 qdev_prop_set_uint8(s->i2c[0], "revision", 0x11);
0fd20c53 4032 omap_i2c_set_fclk(OMAP_I2C(s->i2c[0]), omap_findclk(s, "mpuper_ck"));
1356b98d 4033 busdev = SYS_BUS_DEVICE(s->i2c[0]);
3c6ef471 4034 sysbus_realize_and_unref(busdev, &error_fatal);
54e17933
JR		 4035 sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(s->ih[1], OMAP_INT_I2C));
4036 sysbus_connect_irq(busdev, 1, s->drq[OMAP_DMA_I2C_TX]);
4037 sysbus_connect_irq(busdev, 2, s->drq[OMAP_DMA_I2C_RX]);
4038 sysbus_mmio_map(busdev, 0, 0xfffb3800);
4a2c8ac2 4039
a4ebbd18 4040 s->rtc = omap_rtc_init(system_memory, 0xfffb4800,
0919ac78
PM		 4041 qdev_get_gpio_in(s->ih[1], OMAP_INT_RTC_TIMER),
4042 qdev_get_gpio_in(s->ih[1], OMAP_INT_RTC_ALARM),
5c1c390f 4043 omap_findclk(s, "clk32-kHz"));
02645926 4044
0919ac78
PM		 4045 s->mcbsp1 = omap_mcbsp_init(system_memory, 0xfffb1800,
4046 qdev_get_gpio_in(s->ih[1], OMAP_INT_McBSP1TX),
4047 qdev_get_gpio_in(s->ih[1], OMAP_INT_McBSP1RX),
d8f699cb 4048 &s->drq[OMAP_DMA_MCBSP1_TX], omap_findclk(s, "dspxor_ck"));
0919ac78
PM		 4049 s->mcbsp2 = omap_mcbsp_init(system_memory, 0xfffb1000,
4050 qdev_get_gpio_in(s->ih[0],
4051 OMAP_INT_310_McBSP2_TX),
4052 qdev_get_gpio_in(s->ih[0],
4053 OMAP_INT_310_McBSP2_RX),
d8f699cb 4054 &s->drq[OMAP_DMA_MCBSP2_TX], omap_findclk(s, "mpuper_ck"));
0919ac78
PM		 4055 s->mcbsp3 = omap_mcbsp_init(system_memory, 0xfffb7000,
4056 qdev_get_gpio_in(s->ih[1], OMAP_INT_McBSP3TX),
4057 qdev_get_gpio_in(s->ih[1], OMAP_INT_McBSP3RX),
d8f699cb
AZ		 4058 &s->drq[OMAP_DMA_MCBSP3_TX], omap_findclk(s, "dspxor_ck"));
4059
60fe76e3
AK		 4060 s->led[0] = omap_lpg_init(system_memory,
4061 0xfffbd000, omap_findclk(s, "clk32-kHz"));
4062 s->led[1] = omap_lpg_init(system_memory,
4063 0xfffbd800, omap_findclk(s, "clk32-kHz"));
f9d43072 4064
02645926 4065 /* Register mappings not currenlty implemented:
02645926
AZ		 4066 * MCSI2 Comm fffb2000 - fffb27ff (not mapped on OMAP310)
4067 * MCSI1 Bluetooth fffb2800 - fffb2fff (not mapped on OMAP310)
4068 * USB W2FC fffb4000 - fffb47ff
4069 * Camera Interface fffb6800 - fffb6fff
02645926
AZ		 4070 * USB Host fffba000 - fffba7ff
4071 * FAC fffba800 - fffbafff
4072 * HDQ/1-Wire fffbc000 - fffbc7ff
b854bc19 4073 * TIPB switches fffbc800 - fffbcfff
02645926
AZ		 4074 * Mailbox fffcf000 - fffcf7ff
4075 * Local bus IF fffec100 - fffec1ff
4076 * Local bus MMU fffec200 - fffec2ff
4077 * DSP MMU fffed200 - fffed2ff
4078 */
4079
763b946c 4080 omap_setup_dsp_mapping(system_memory, omap15xx_dsp_mm);
60fe76e3 4081 omap_setup_mpui_io(system_memory, s);
cf965d24 4082
a08d4367 4083 qemu_register_reset(omap1_mpu_reset, s);
c3d2689d
AZ		 4084
4085 return s;
4086}
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