[qemu.git] / hw / timer / exynos4210_rtc.c

/*
 * Samsung exynos4210 Real Time Clock
 *
 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
 *  Ogurtsov Oleg <[email protected]>
 *
 *  This program is free software; you can redistribute it and/or modify it
 *  under the terms of the GNU General Public License as published by the
 *  Free Software Foundation; either version 2 of the License, or
 *  (at your option) any later version.
 *
 *  This program is distributed in the hope that it will be useful, but WITHOUT
 *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 *  FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
 *  for more details.
 *
 *  You should have received a copy of the GNU General Public License along
 *  with this program; if not, see <http://www.gnu.org/licenses/>.
 *
 */

/* Description:
 * Register RTCCON:
 *  CLKSEL Bit[1] not used
 *  CLKOUTEN Bit[9] not used
 */

#include "qemu/osdep.h"
#include "qemu/log.h"
#include "hw/sysbus.h"
#include "qemu/timer.h"
#include "qemu-common.h"
#include "qemu/bcd.h"
#include "hw/ptimer.h"

#include "hw/hw.h"
#include "sysemu/sysemu.h"

#include "hw/arm/exynos4210.h"

#define DEBUG_RTC 0

#if DEBUG_RTC
#define DPRINTF(fmt, ...) \
        do { fprintf(stdout, "RTC: [%24s:%5d] " fmt, __func__, __LINE__, \
                ## __VA_ARGS__); } while (0)
#else
#define DPRINTF(fmt, ...) do {} while (0)
#endif

#define     EXYNOS4210_RTC_REG_MEM_SIZE     0x0100

#define     INTP            0x0030
#define     RTCCON          0x0040
#define     TICCNT          0x0044
#define     RTCALM          0x0050
#define     ALMSEC          0x0054
#define     ALMMIN          0x0058
#define     ALMHOUR         0x005C
#define     ALMDAY          0x0060
#define     ALMMON          0x0064
#define     ALMYEAR         0x0068
#define     BCDSEC          0x0070
#define     BCDMIN          0x0074
#define     BCDHOUR         0x0078
#define     BCDDAY          0x007C
#define     BCDDAYWEEK      0x0080
#define     BCDMON          0x0084
#define     BCDYEAR         0x0088
#define     CURTICNT        0x0090

#define     TICK_TIMER_ENABLE   0x0100
#define     TICNT_THRESHOLD     2


#define     RTC_ENABLE          0x0001

#define     INTP_TICK_ENABLE    0x0001
#define     INTP_ALM_ENABLE     0x0002

#define     ALARM_INT_ENABLE    0x0040

#define     RTC_BASE_FREQ       32768

#define TYPE_EXYNOS4210_RTC "exynos4210.rtc"
#define EXYNOS4210_RTC(obj) \
    OBJECT_CHECK(Exynos4210RTCState, (obj), TYPE_EXYNOS4210_RTC)

typedef struct Exynos4210RTCState {
    SysBusDevice parent_obj;

    MemoryRegion iomem;

    /* registers */
    uint32_t    reg_intp;
    uint32_t    reg_rtccon;
    uint32_t    reg_ticcnt;
    uint32_t    reg_rtcalm;
    uint32_t    reg_almsec;
    uint32_t    reg_almmin;
    uint32_t    reg_almhour;
    uint32_t    reg_almday;
    uint32_t    reg_almmon;
    uint32_t    reg_almyear;
    uint32_t    reg_curticcnt;

    ptimer_state    *ptimer;        /* tick timer */
    ptimer_state    *ptimer_1Hz;    /* clock timer */
    uint32_t        freq;

    qemu_irq        tick_irq;   /* Time Tick Generator irq */
    qemu_irq        alm_irq;    /* alarm irq */

    struct tm   current_tm;     /* current time */
} Exynos4210RTCState;

#define TICCKSEL(value) ((value & (0x0F << 4)) >> 4)

/*** VMState ***/
static const VMStateDescription vmstate_exynos4210_rtc_state = {
    .name = "exynos4210.rtc",
    .version_id = 1,
    .minimum_version_id = 1,
    .fields = (VMStateField[]) {
        VMSTATE_UINT32(reg_intp, Exynos4210RTCState),
        VMSTATE_UINT32(reg_rtccon, Exynos4210RTCState),
        VMSTATE_UINT32(reg_ticcnt, Exynos4210RTCState),
        VMSTATE_UINT32(reg_rtcalm, Exynos4210RTCState),
        VMSTATE_UINT32(reg_almsec, Exynos4210RTCState),
        VMSTATE_UINT32(reg_almmin, Exynos4210RTCState),
        VMSTATE_UINT32(reg_almhour, Exynos4210RTCState),
        VMSTATE_UINT32(reg_almday, Exynos4210RTCState),
        VMSTATE_UINT32(reg_almmon, Exynos4210RTCState),
        VMSTATE_UINT32(reg_almyear, Exynos4210RTCState),
        VMSTATE_UINT32(reg_curticcnt, Exynos4210RTCState),
        VMSTATE_PTIMER(ptimer, Exynos4210RTCState),
        VMSTATE_PTIMER(ptimer_1Hz, Exynos4210RTCState),
        VMSTATE_UINT32(freq, Exynos4210RTCState),
        VMSTATE_INT32(current_tm.tm_sec, Exynos4210RTCState),
        VMSTATE_INT32(current_tm.tm_min, Exynos4210RTCState),
        VMSTATE_INT32(current_tm.tm_hour, Exynos4210RTCState),
        VMSTATE_INT32(current_tm.tm_wday, Exynos4210RTCState),
        VMSTATE_INT32(current_tm.tm_mday, Exynos4210RTCState),
        VMSTATE_INT32(current_tm.tm_mon, Exynos4210RTCState),
        VMSTATE_INT32(current_tm.tm_year, Exynos4210RTCState),
        VMSTATE_END_OF_LIST()
    }
};

#define BCD3DIGITS(x) \
    ((uint32_t)to_bcd((uint8_t)(x % 100)) + \
    ((uint32_t)to_bcd((uint8_t)((x % 1000) / 100)) << 8))

static void check_alarm_raise(Exynos4210RTCState *s)
{
    unsigned int alarm_raise = 0;
    struct tm stm = s->current_tm;

    if ((s->reg_rtcalm & 0x01) &&
        (to_bcd((uint8_t)stm.tm_sec) == (uint8_t)s->reg_almsec)) {
        alarm_raise = 1;
    }
    if ((s->reg_rtcalm & 0x02) &&
        (to_bcd((uint8_t)stm.tm_min) == (uint8_t)s->reg_almmin)) {
        alarm_raise = 1;
    }
    if ((s->reg_rtcalm & 0x04) &&
        (to_bcd((uint8_t)stm.tm_hour) == (uint8_t)s->reg_almhour)) {
        alarm_raise = 1;
    }
    if ((s->reg_rtcalm & 0x08) &&
        (to_bcd((uint8_t)stm.tm_mday) == (uint8_t)s->reg_almday)) {
        alarm_raise = 1;
    }
    if ((s->reg_rtcalm & 0x10) &&
         (to_bcd((uint8_t)stm.tm_mon) == (uint8_t)s->reg_almmon)) {
        alarm_raise = 1;
    }
    if ((s->reg_rtcalm & 0x20) &&
        (BCD3DIGITS(stm.tm_year) == s->reg_almyear)) {
        alarm_raise = 1;
    }

    if (alarm_raise) {
        DPRINTF("ALARM IRQ\n");
        /* set irq status */
        s->reg_intp |= INTP_ALM_ENABLE;
        qemu_irq_raise(s->alm_irq);
    }
}

/*
 * RTC update frequency
 * Parameters:
 *     reg_value - current RTCCON register or his new value
 */
static void exynos4210_rtc_update_freq(Exynos4210RTCState *s,
                                       uint32_t reg_value)
{
    uint32_t freq;

    freq = s->freq;
    /* set frequncy for time generator */
    s->freq = RTC_BASE_FREQ / (1 << TICCKSEL(reg_value));

    if (freq != s->freq) {
        ptimer_set_freq(s->ptimer, s->freq);
        DPRINTF("freq=%dHz\n", s->freq);
    }
}

/* month is between 0 and 11. */
static int get_days_in_month(int month, int year)
{
    static const int days_tab[12] = {
        31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31
    };
    int d;
    if ((unsigned)month >= 12) {
        return 31;
    }
    d = days_tab[month];
    if (month == 1) {
        if ((year % 4) == 0 && ((year % 100) != 0 || (year % 400) == 0)) {
            d++;
        }
    }
    return d;
}

/* update 'tm' to the next second */
static void rtc_next_second(struct tm *tm)
{
    int days_in_month;

    tm->tm_sec++;
    if ((unsigned)tm->tm_sec >= 60) {
        tm->tm_sec = 0;
        tm->tm_min++;
        if ((unsigned)tm->tm_min >= 60) {
            tm->tm_min = 0;
            tm->tm_hour++;
            if ((unsigned)tm->tm_hour >= 24) {
                tm->tm_hour = 0;
                /* next day */
                tm->tm_wday++;
                if ((unsigned)tm->tm_wday >= 7) {
                    tm->tm_wday = 0;
                }
                days_in_month = get_days_in_month(tm->tm_mon,
                                                  tm->tm_year + 1900);
                tm->tm_mday++;
                if (tm->tm_mday < 1) {
                    tm->tm_mday = 1;
                } else if (tm->tm_mday > days_in_month) {
                    tm->tm_mday = 1;
                    tm->tm_mon++;
                    if (tm->tm_mon >= 12) {
                        tm->tm_mon = 0;
                        tm->tm_year++;
                    }
                }
            }
        }
    }
}

/*
 * tick handler
 */
static void exynos4210_rtc_tick(void *opaque)
{
    Exynos4210RTCState *s = (Exynos4210RTCState *)opaque;

    DPRINTF("TICK IRQ\n");
    /* set irq status */
    s->reg_intp |= INTP_TICK_ENABLE;
    /* raise IRQ */
    qemu_irq_raise(s->tick_irq);

    /* restart timer */
    ptimer_set_count(s->ptimer, s->reg_ticcnt);
    ptimer_run(s->ptimer, 1);
}

/*
 * 1Hz clock handler
 */
static void exynos4210_rtc_1Hz_tick(void *opaque)
{
    Exynos4210RTCState *s = (Exynos4210RTCState *)opaque;

    rtc_next_second(&s->current_tm);
    /* DPRINTF("1Hz tick\n"); */

    /* raise IRQ */
    if (s->reg_rtcalm & ALARM_INT_ENABLE) {
        check_alarm_raise(s);
    }

    ptimer_set_count(s->ptimer_1Hz, RTC_BASE_FREQ);
    ptimer_run(s->ptimer_1Hz, 1);
}

/*
 * RTC Read
 */
static uint64_t exynos4210_rtc_read(void *opaque, hwaddr offset,
        unsigned size)
{
    uint32_t value = 0;
    Exynos4210RTCState *s = (Exynos4210RTCState *)opaque;

    switch (offset) {
    case INTP:
        value = s->reg_intp;
        break;
    case RTCCON:
        value = s->reg_rtccon;
        break;
    case TICCNT:
        value = s->reg_ticcnt;
        break;
    case RTCALM:
        value = s->reg_rtcalm;
        break;
    case ALMSEC:
        value = s->reg_almsec;
        break;
    case ALMMIN:
        value = s->reg_almmin;
        break;
    case ALMHOUR:
        value = s->reg_almhour;
        break;
    case ALMDAY:
        value = s->reg_almday;
        break;
    case ALMMON:
        value = s->reg_almmon;
        break;
    case ALMYEAR:
        value = s->reg_almyear;
        break;

    case BCDSEC:
        value = (uint32_t)to_bcd((uint8_t)s->current_tm.tm_sec);
        break;
    case BCDMIN:
        value = (uint32_t)to_bcd((uint8_t)s->current_tm.tm_min);
        break;
    case BCDHOUR:
        value = (uint32_t)to_bcd((uint8_t)s->current_tm.tm_hour);
        break;
    case BCDDAYWEEK:
        value = (uint32_t)to_bcd((uint8_t)s->current_tm.tm_wday);
        break;
    case BCDDAY:
        value = (uint32_t)to_bcd((uint8_t)s->current_tm.tm_mday);
        break;
    case BCDMON:
        value = (uint32_t)to_bcd((uint8_t)s->current_tm.tm_mon + 1);
        break;
    case BCDYEAR:
        value = BCD3DIGITS(s->current_tm.tm_year);
        break;

    case CURTICNT:
        s->reg_curticcnt = ptimer_get_count(s->ptimer);
        value = s->reg_curticcnt;
        break;

    default:
        qemu_log_mask(LOG_GUEST_ERROR,
                      "exynos4210.rtc: bad read offset " TARGET_FMT_plx,
                      offset);
        break;
    }
    return value;
}

/*
 * RTC Write
 */
static void exynos4210_rtc_write(void *opaque, hwaddr offset,
        uint64_t value, unsigned size)
{
    Exynos4210RTCState *s = (Exynos4210RTCState *)opaque;

    switch (offset) {
    case INTP:
        if (value & INTP_ALM_ENABLE) {
            qemu_irq_lower(s->alm_irq);
            s->reg_intp &= (~INTP_ALM_ENABLE);
        }
        if (value & INTP_TICK_ENABLE) {
            qemu_irq_lower(s->tick_irq);
            s->reg_intp &= (~INTP_TICK_ENABLE);
        }
        break;
    case RTCCON:
        if (value & RTC_ENABLE) {
            exynos4210_rtc_update_freq(s, value);
        }
        if ((value & RTC_ENABLE) > (s->reg_rtccon & RTC_ENABLE)) {
            /* clock timer */
            ptimer_set_count(s->ptimer_1Hz, RTC_BASE_FREQ);
            ptimer_run(s->ptimer_1Hz, 1);
            DPRINTF("run clock timer\n");
        }
        if ((value & RTC_ENABLE) < (s->reg_rtccon & RTC_ENABLE)) {
            /* tick timer */
            ptimer_stop(s->ptimer);
            /* clock timer */
            ptimer_stop(s->ptimer_1Hz);
            DPRINTF("stop all timers\n");
        }
        if (value & RTC_ENABLE) {
            if ((value & TICK_TIMER_ENABLE) >
                (s->reg_rtccon & TICK_TIMER_ENABLE) &&
                (s->reg_ticcnt)) {
                ptimer_set_count(s->ptimer, s->reg_ticcnt);
                ptimer_run(s->ptimer, 1);
                DPRINTF("run tick timer\n");
            }
            if ((value & TICK_TIMER_ENABLE) <
                (s->reg_rtccon & TICK_TIMER_ENABLE)) {
                ptimer_stop(s->ptimer);
            }
        }
        s->reg_rtccon = value;
        break;
    case TICCNT:
        if (value > TICNT_THRESHOLD) {
            s->reg_ticcnt = value;
        } else {
            qemu_log_mask(LOG_GUEST_ERROR,
                          "exynos4210.rtc: bad TICNT value %u",
                          (uint32_t)value);
        }
        break;

    case RTCALM:
        s->reg_rtcalm = value;
        break;
    case ALMSEC:
        s->reg_almsec = (value & 0x7f);
        break;
    case ALMMIN:
        s->reg_almmin = (value & 0x7f);
        break;
    case ALMHOUR:
        s->reg_almhour = (value & 0x3f);
        break;
    case ALMDAY:
        s->reg_almday = (value & 0x3f);
        break;
    case ALMMON:
        s->reg_almmon = (value & 0x1f);
        break;
    case ALMYEAR:
        s->reg_almyear = (value & 0x0fff);
        break;

    case BCDSEC:
        if (s->reg_rtccon & RTC_ENABLE) {
            s->current_tm.tm_sec = (int)from_bcd((uint8_t)value);
        }
        break;
    case BCDMIN:
        if (s->reg_rtccon & RTC_ENABLE) {
            s->current_tm.tm_min = (int)from_bcd((uint8_t)value);
        }
        break;
    case BCDHOUR:
        if (s->reg_rtccon & RTC_ENABLE) {
            s->current_tm.tm_hour = (int)from_bcd((uint8_t)value);
        }
        break;
    case BCDDAYWEEK:
        if (s->reg_rtccon & RTC_ENABLE) {
            s->current_tm.tm_wday = (int)from_bcd((uint8_t)value);
        }
        break;
    case BCDDAY:
        if (s->reg_rtccon & RTC_ENABLE) {
            s->current_tm.tm_mday = (int)from_bcd((uint8_t)value);
        }
        break;
    case BCDMON:
        if (s->reg_rtccon & RTC_ENABLE) {
            s->current_tm.tm_mon = (int)from_bcd((uint8_t)value) - 1;
        }
        break;
    case BCDYEAR:
        if (s->reg_rtccon & RTC_ENABLE) {
            /* 3 digits */
            s->current_tm.tm_year = (int)from_bcd((uint8_t)value) +
                    (int)from_bcd((uint8_t)((value >> 8) & 0x0f)) * 100;
        }
        break;

    default:
        qemu_log_mask(LOG_GUEST_ERROR,
                      "exynos4210.rtc: bad write offset " TARGET_FMT_plx,
                      offset);
        break;

    }
}

/*
 * Set default values to timer fields and registers
 */
static void exynos4210_rtc_reset(DeviceState *d)
{
    Exynos4210RTCState *s = EXYNOS4210_RTC(d);

    qemu_get_timedate(&s->current_tm, 0);

    DPRINTF("Get time from host: %d-%d-%d %2d:%02d:%02d\n",
            s->current_tm.tm_year, s->current_tm.tm_mon, s->current_tm.tm_mday,
            s->current_tm.tm_hour, s->current_tm.tm_min, s->current_tm.tm_sec);

    s->reg_intp = 0;
    s->reg_rtccon = 0;
    s->reg_ticcnt = 0;
    s->reg_rtcalm = 0;
    s->reg_almsec = 0;
    s->reg_almmin = 0;
    s->reg_almhour = 0;
    s->reg_almday = 0;
    s->reg_almmon = 0;
    s->reg_almyear = 0;

    s->reg_curticcnt = 0;

    exynos4210_rtc_update_freq(s, s->reg_rtccon);
    ptimer_stop(s->ptimer);
    ptimer_stop(s->ptimer_1Hz);
}

static const MemoryRegionOps exynos4210_rtc_ops = {
    .read = exynos4210_rtc_read,
    .write = exynos4210_rtc_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
};

/*
 * RTC timer initialization
 */
static void exynos4210_rtc_init(Object *obj)
{
    Exynos4210RTCState *s = EXYNOS4210_RTC(obj);
    SysBusDevice *dev = SYS_BUS_DEVICE(obj);
    QEMUBH *bh;

    bh = qemu_bh_new(exynos4210_rtc_tick, s);
    s->ptimer = ptimer_init(bh, PTIMER_POLICY_DEFAULT);
    ptimer_set_freq(s->ptimer, RTC_BASE_FREQ);
    exynos4210_rtc_update_freq(s, 0);

    bh = qemu_bh_new(exynos4210_rtc_1Hz_tick, s);
    s->ptimer_1Hz = ptimer_init(bh, PTIMER_POLICY_DEFAULT);
    ptimer_set_freq(s->ptimer_1Hz, RTC_BASE_FREQ);

    sysbus_init_irq(dev, &s->alm_irq);
    sysbus_init_irq(dev, &s->tick_irq);

    memory_region_init_io(&s->iomem, obj, &exynos4210_rtc_ops, s,
                          "exynos4210-rtc", EXYNOS4210_RTC_REG_MEM_SIZE);
    sysbus_init_mmio(dev, &s->iomem);
}

static void exynos4210_rtc_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);

    dc->reset = exynos4210_rtc_reset;
    dc->vmsd = &vmstate_exynos4210_rtc_state;
}

static const TypeInfo exynos4210_rtc_info = {
    .name          = TYPE_EXYNOS4210_RTC,
    .parent        = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(Exynos4210RTCState),
    .instance_init = exynos4210_rtc_init,
    .class_init    = exynos4210_rtc_class_init,
};

static void exynos4210_rtc_register_types(void)
{
    type_register_static(&exynos4210_rtc_info);
}

type_init(exynos4210_rtc_register_types)
Commit	Line	Data
7bdf43a7 OO	1	/*
	2	* Samsung exynos4210 Real Time Clock
	3	*
	4	* Copyright (c) 2012 Samsung Electronics Co., Ltd.
	5	* Ogurtsov Oleg <[email protected]>
	6	*
	7	* This program is free software; you can redistribute it and/or modify it
	8	* under the terms of the GNU General Public License as published by the
	9	* Free Software Foundation; either version 2 of the License, or
	10	* (at your option) any later version.
	11	*
	12	* This program is distributed in the hope that it will be useful, but WITHOUT
	13	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	14	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
	15	* for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License along
	18	* with this program; if not, see <http://www.gnu.org/licenses/>.
	19	*
	20	*/
	21
	22	/* Description:
	23	* Register RTCCON:
	24	* CLKSEL Bit[1] not used
	25	* CLKOUTEN Bit[9] not used
	26	*/
	27
8ef94f0b	28	#include "qemu/osdep.h"
f2ad5140	29	#include "qemu/log.h"
83c9f4ca	30	#include "hw/sysbus.h"
1de7afc9	31	#include "qemu/timer.h"
7bdf43a7	32	#include "qemu-common.h"
f348b6d1	33	#include "qemu/bcd.h"
83c9f4ca	34	#include "hw/ptimer.h"
7bdf43a7	35
83c9f4ca	36	#include "hw/hw.h"
9c17d615	37	#include "sysemu/sysemu.h"
7bdf43a7	38
0d09e41a	39	#include "hw/arm/exynos4210.h"
7bdf43a7 OO	40
	41	#define DEBUG_RTC 0
	42
	43	#if DEBUG_RTC
	44	#define DPRINTF(fmt, ...) \
	45	do { fprintf(stdout, "RTC: [%24s:%5d] " fmt, __func__, __LINE__, \
	46	## __VA_ARGS__); } while (0)
	47	#else
	48	#define DPRINTF(fmt, ...) do {} while (0)
	49	#endif
	50
	51	#define EXYNOS4210_RTC_REG_MEM_SIZE 0x0100
	52
	53	#define INTP 0x0030
	54	#define RTCCON 0x0040
	55	#define TICCNT 0x0044
	56	#define RTCALM 0x0050
	57	#define ALMSEC 0x0054
	58	#define ALMMIN 0x0058
	59	#define ALMHOUR 0x005C
	60	#define ALMDAY 0x0060
	61	#define ALMMON 0x0064
	62	#define ALMYEAR 0x0068
	63	#define BCDSEC 0x0070
	64	#define BCDMIN 0x0074
	65	#define BCDHOUR 0x0078
	66	#define BCDDAY 0x007C
	67	#define BCDDAYWEEK 0x0080
	68	#define BCDMON 0x0084
	69	#define BCDYEAR 0x0088
	70	#define CURTICNT 0x0090
	71
	72	#define TICK_TIMER_ENABLE 0x0100
4c293dc6	73	#define TICNT_THRESHOLD 2
7bdf43a7 OO	74
	75
	76	#define RTC_ENABLE 0x0001
	77
	78	#define INTP_TICK_ENABLE 0x0001
	79	#define INTP_ALM_ENABLE 0x0002
	80
	81	#define ALARM_INT_ENABLE 0x0040
	82
	83	#define RTC_BASE_FREQ 32768
	84
3ddacf27 AF	85	#define TYPE_EXYNOS4210_RTC "exynos4210.rtc"
	86	#define EXYNOS4210_RTC(obj) \
	87	OBJECT_CHECK(Exynos4210RTCState, (obj), TYPE_EXYNOS4210_RTC)
	88
7bdf43a7	89	typedef struct Exynos4210RTCState {
3ddacf27 AF	90	SysBusDevice parent_obj;
3ddacf27 AF	91
7bdf43a7 OO	92	MemoryRegion iomem;
	93
	94	/* registers */
	95	uint32_t reg_intp;
	96	uint32_t reg_rtccon;
	97	uint32_t reg_ticcnt;
	98	uint32_t reg_rtcalm;
	99	uint32_t reg_almsec;
	100	uint32_t reg_almmin;
	101	uint32_t reg_almhour;
	102	uint32_t reg_almday;
	103	uint32_t reg_almmon;
	104	uint32_t reg_almyear;
	105	uint32_t reg_curticcnt;
	106
	107	ptimer_state ptimer; / tick timer */
	108	ptimer_state ptimer_1Hz; / clock timer */
	109	uint32_t freq;
	110
	111	qemu_irq tick_irq; /* Time Tick Generator irq */
	112	qemu_irq alm_irq; /* alarm irq */
	113
	114	struct tm current_tm; /* current time */
	115	} Exynos4210RTCState;
	116
	117	#define TICCKSEL(value) ((value & (0x0F << 4)) >> 4)
	118
	119	/* VMState */
	120	static const VMStateDescription vmstate_exynos4210_rtc_state = {
	121	.name = "exynos4210.rtc",
	122	.version_id = 1,
	123	.minimum_version_id = 1,
7bdf43a7 OO	124	.fields = (VMStateField[]) {
	125	VMSTATE_UINT32(reg_intp, Exynos4210RTCState),
	126	VMSTATE_UINT32(reg_rtccon, Exynos4210RTCState),
	127	VMSTATE_UINT32(reg_ticcnt, Exynos4210RTCState),
	128	VMSTATE_UINT32(reg_rtcalm, Exynos4210RTCState),
	129	VMSTATE_UINT32(reg_almsec, Exynos4210RTCState),
	130	VMSTATE_UINT32(reg_almmin, Exynos4210RTCState),
	131	VMSTATE_UINT32(reg_almhour, Exynos4210RTCState),
	132	VMSTATE_UINT32(reg_almday, Exynos4210RTCState),
	133	VMSTATE_UINT32(reg_almmon, Exynos4210RTCState),
	134	VMSTATE_UINT32(reg_almyear, Exynos4210RTCState),
	135	VMSTATE_UINT32(reg_curticcnt, Exynos4210RTCState),
	136	VMSTATE_PTIMER(ptimer, Exynos4210RTCState),
	137	VMSTATE_PTIMER(ptimer_1Hz, Exynos4210RTCState),
	138	VMSTATE_UINT32(freq, Exynos4210RTCState),
	139	VMSTATE_INT32(current_tm.tm_sec, Exynos4210RTCState),
	140	VMSTATE_INT32(current_tm.tm_min, Exynos4210RTCState),
	141	VMSTATE_INT32(current_tm.tm_hour, Exynos4210RTCState),
	142	VMSTATE_INT32(current_tm.tm_wday, Exynos4210RTCState),
	143	VMSTATE_INT32(current_tm.tm_mday, Exynos4210RTCState),
	144	VMSTATE_INT32(current_tm.tm_mon, Exynos4210RTCState),
	145	VMSTATE_INT32(current_tm.tm_year, Exynos4210RTCState),
	146	VMSTATE_END_OF_LIST()
	147	}
	148	};
	149
	150	#define BCD3DIGITS(x) \
64de1ecf	151	((uint32_t)to_bcd((uint8_t)(x % 100)) + \
7bdf43a7 OO	152	((uint32_t)to_bcd((uint8_t)((x % 1000) / 100)) << 8))
	153
	154	static void check_alarm_raise(Exynos4210RTCState *s)
	155	{
	156	unsigned int alarm_raise = 0;
	157	struct tm stm = s->current_tm;
	158
	159	if ((s->reg_rtcalm & 0x01) &&
	160	(to_bcd((uint8_t)stm.tm_sec) == (uint8_t)s->reg_almsec)) {
	161	alarm_raise = 1;
	162	}
	163	if ((s->reg_rtcalm & 0x02) &&
	164	(to_bcd((uint8_t)stm.tm_min) == (uint8_t)s->reg_almmin)) {
	165	alarm_raise = 1;
	166	}
	167	if ((s->reg_rtcalm & 0x04) &&
	168	(to_bcd((uint8_t)stm.tm_hour) == (uint8_t)s->reg_almhour)) {
	169	alarm_raise = 1;
	170	}
	171	if ((s->reg_rtcalm & 0x08) &&
	172	(to_bcd((uint8_t)stm.tm_mday) == (uint8_t)s->reg_almday)) {
	173	alarm_raise = 1;
	174	}
	175	if ((s->reg_rtcalm & 0x10) &&
	176	(to_bcd((uint8_t)stm.tm_mon) == (uint8_t)s->reg_almmon)) {
	177	alarm_raise = 1;
	178	}
	179	if ((s->reg_rtcalm & 0x20) &&
	180	(BCD3DIGITS(stm.tm_year) == s->reg_almyear)) {
	181	alarm_raise = 1;
	182	}
	183
	184	if (alarm_raise) {
	185	DPRINTF("ALARM IRQ\n");
	186	/* set irq status */
	187	s->reg_intp \|= INTP_ALM_ENABLE;
	188	qemu_irq_raise(s->alm_irq);
	189	}
	190	}
	191
	192	/*
	193	* RTC update frequency
	194	* Parameters:
	195	* reg_value - current RTCCON register or his new value
	196	*/
	197	static void exynos4210_rtc_update_freq(Exynos4210RTCState *s,
	198	uint32_t reg_value)
	199	{
	200	uint32_t freq;
	201
	202	freq = s->freq;
	203	/* set frequncy for time generator */
	204	s->freq = RTC_BASE_FREQ / (1 << TICCKSEL(reg_value));
	205
	206	if (freq != s->freq) {
	207	ptimer_set_freq(s->ptimer, s->freq);
	208	DPRINTF("freq=%dHz\n", s->freq);
	209	}
	210	}
	211
	212	/* month is between 0 and 11. */
	213	static int get_days_in_month(int month, int year)
	214	{
	215	static const int days_tab[12] = {
216	31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31
217	};
218	int d;
219	if ((unsigned)month >= 12) {
220	return 31;
221	}
222	d = days_tab[month];
223	if (month == 1) {
224	if ((year % 4) == 0 && ((year % 100) != 0 \|\| (year % 400) == 0)) {
225	d++;
226	}
227	}
228	return d;
229	}
230
231	/* update 'tm' to the next second */
232	static void rtc_next_second(struct tm *tm)
233	{
234	int days_in_month;
235
236	tm->tm_sec++;
237	if ((unsigned)tm->tm_sec >= 60) {
238	tm->tm_sec = 0;
239	tm->tm_min++;
240	if ((unsigned)tm->tm_min >= 60) {
241	tm->tm_min = 0;
242	tm->tm_hour++;
243	if ((unsigned)tm->tm_hour >= 24) {
244	tm->tm_hour = 0;
245	/* next day */
246	tm->tm_wday++;
247	if ((unsigned)tm->tm_wday >= 7) {
248	tm->tm_wday = 0;
249	}
250	days_in_month = get_days_in_month(tm->tm_mon,
251	tm->tm_year + 1900);
252	tm->tm_mday++;
253	if (tm->tm_mday < 1) {
254	tm->tm_mday = 1;
255	} else if (tm->tm_mday > days_in_month) {
256	tm->tm_mday = 1;
257	tm->tm_mon++;
258	if (tm->tm_mon >= 12) {
259	tm->tm_mon = 0;
260	tm->tm_year++;
261	}
262	}
263	}
264	}
265	}
266	}
267
268	/*
269	* tick handler
270	*/
271	static void exynos4210_rtc_tick(void *opaque)
272	{
273	Exynos4210RTCState s = (Exynos4210RTCState )opaque;
274
275	DPRINTF("TICK IRQ\n");
276	/* set irq status */
277	s->reg_intp \|= INTP_TICK_ENABLE;
278	/* raise IRQ */
279	qemu_irq_raise(s->tick_irq);
280
281	/* restart timer */
282	ptimer_set_count(s->ptimer, s->reg_ticcnt);
283	ptimer_run(s->ptimer, 1);
284	}
285
286	/*
287	* 1Hz clock handler
288	*/
289	static void exynos4210_rtc_1Hz_tick(void *opaque)
290	{
291	Exynos4210RTCState s = (Exynos4210RTCState )opaque;
292
293	rtc_next_second(&s->current_tm);
294	/* DPRINTF("1Hz tick\n"); */
295
296	/* raise IRQ */
297	if (s->reg_rtcalm & ALARM_INT_ENABLE) {
298	check_alarm_raise(s);
299	}
300
301	ptimer_set_count(s->ptimer_1Hz, RTC_BASE_FREQ);
302	ptimer_run(s->ptimer_1Hz, 1);
303	}
304
305	/*
306	* RTC Read
307	*/
a8170e5e	308	static uint64_t exynos4210_rtc_read(void *opaque, hwaddr offset,
7bdf43a7 OO	309	unsigned size)
	310	{
	311	uint32_t value = 0;
	312	Exynos4210RTCState s = (Exynos4210RTCState )opaque;
	313
	314	switch (offset) {
	315	case INTP:
	316	value = s->reg_intp;
	317	break;
	318	case RTCCON:
	319	value = s->reg_rtccon;
	320	break;
	321	case TICCNT:
	322	value = s->reg_ticcnt;
	323	break;
	324	case RTCALM:
	325	value = s->reg_rtcalm;
	326	break;
	327	case ALMSEC:
	328	value = s->reg_almsec;
	329	break;
	330	case ALMMIN:
	331	value = s->reg_almmin;
	332	break;
	333	case ALMHOUR:
	334	value = s->reg_almhour;
	335	break;
	336	case ALMDAY:
	337	value = s->reg_almday;
	338	break;
	339	case ALMMON:
	340	value = s->reg_almmon;
	341	break;
	342	case ALMYEAR:
	343	value = s->reg_almyear;
	344	break;
	345
	346	case BCDSEC:
	347	value = (uint32_t)to_bcd((uint8_t)s->current_tm.tm_sec);
	348	break;
	349	case BCDMIN:
	350	value = (uint32_t)to_bcd((uint8_t)s->current_tm.tm_min);
	351	break;
	352	case BCDHOUR:
	353	value = (uint32_t)to_bcd((uint8_t)s->current_tm.tm_hour);
	354	break;
	355	case BCDDAYWEEK:
	356	value = (uint32_t)to_bcd((uint8_t)s->current_tm.tm_wday);
	357	break;
	358	case BCDDAY:
	359	value = (uint32_t)to_bcd((uint8_t)s->current_tm.tm_mday);
	360	break;
	361	case BCDMON:
	362	value = (uint32_t)to_bcd((uint8_t)s->current_tm.tm_mon + 1);
	363	break;
	364	case BCDYEAR:
	365	value = BCD3DIGITS(s->current_tm.tm_year);
	366	break;
	367
	368	case CURTICNT:
	369	s->reg_curticcnt = ptimer_get_count(s->ptimer);
	370	value = s->reg_curticcnt;
	371	break;
	372
373	default:
f2ad5140 KK	374	qemu_log_mask(LOG_GUEST_ERROR,
	375	"exynos4210.rtc: bad read offset " TARGET_FMT_plx,
	376	offset);
7bdf43a7 OO	377	break;
	378	}
	379	return value;
	380	}
	381
	382	/*
	383	* RTC Write
	384	*/
a8170e5e	385	static void exynos4210_rtc_write(void *opaque, hwaddr offset,
7bdf43a7 OO	386	uint64_t value, unsigned size)
	387	{
	388	Exynos4210RTCState s = (Exynos4210RTCState )opaque;
	389
	390	switch (offset) {
	391	case INTP:
	392	if (value & INTP_ALM_ENABLE) {
	393	qemu_irq_lower(s->alm_irq);
	394	s->reg_intp &= (~INTP_ALM_ENABLE);
	395	}
	396	if (value & INTP_TICK_ENABLE) {
	397	qemu_irq_lower(s->tick_irq);
	398	s->reg_intp &= (~INTP_TICK_ENABLE);
	399	}
	400	break;
	401	case RTCCON:
	402	if (value & RTC_ENABLE) {
	403	exynos4210_rtc_update_freq(s, value);
	404	}
	405	if ((value & RTC_ENABLE) > (s->reg_rtccon & RTC_ENABLE)) {
	406	/* clock timer */
	407	ptimer_set_count(s->ptimer_1Hz, RTC_BASE_FREQ);
	408	ptimer_run(s->ptimer_1Hz, 1);
	409	DPRINTF("run clock timer\n");
	410	}
	411	if ((value & RTC_ENABLE) < (s->reg_rtccon & RTC_ENABLE)) {
	412	/* tick timer */
	413	ptimer_stop(s->ptimer);
	414	/* clock timer */
	415	ptimer_stop(s->ptimer_1Hz);
	416	DPRINTF("stop all timers\n");
	417	}
	418	if (value & RTC_ENABLE) {
	419	if ((value & TICK_TIMER_ENABLE) >
	420	(s->reg_rtccon & TICK_TIMER_ENABLE) &&
	421	(s->reg_ticcnt)) {
	422	ptimer_set_count(s->ptimer, s->reg_ticcnt);
	423	ptimer_run(s->ptimer, 1);
	424	DPRINTF("run tick timer\n");
	425	}
	426	if ((value & TICK_TIMER_ENABLE) <
	427	(s->reg_rtccon & TICK_TIMER_ENABLE)) {
	428	ptimer_stop(s->ptimer);
	429	}
	430	}
	431	s->reg_rtccon = value;
	432	break;
	433	case TICCNT:
4c293dc6	434	if (value > TICNT_THRESHOLD) {
7bdf43a7 OO	435	s->reg_ticcnt = value;
7bdf43a7 OO	436	} else {
f2ad5140 KK	437	qemu_log_mask(LOG_GUEST_ERROR,
	438	"exynos4210.rtc: bad TICNT value %u",
	439	(uint32_t)value);
7bdf43a7 OO	440	}
	441	break;
	442
	443	case RTCALM:
	444	s->reg_rtcalm = value;
	445	break;
	446	case ALMSEC:
	447	s->reg_almsec = (value & 0x7f);
	448	break;
	449	case ALMMIN:
	450	s->reg_almmin = (value & 0x7f);
	451	break;
	452	case ALMHOUR:
	453	s->reg_almhour = (value & 0x3f);
	454	break;
	455	case ALMDAY:
	456	s->reg_almday = (value & 0x3f);
	457	break;
	458	case ALMMON:
	459	s->reg_almmon = (value & 0x1f);
	460	break;
	461	case ALMYEAR:
	462	s->reg_almyear = (value & 0x0fff);
	463	break;
	464
	465	case BCDSEC:
	466	if (s->reg_rtccon & RTC_ENABLE) {
	467	s->current_tm.tm_sec = (int)from_bcd((uint8_t)value);
	468	}
	469	break;
	470	case BCDMIN:
	471	if (s->reg_rtccon & RTC_ENABLE) {
	472	s->current_tm.tm_min = (int)from_bcd((uint8_t)value);
	473	}
	474	break;
	475	case BCDHOUR:
	476	if (s->reg_rtccon & RTC_ENABLE) {
	477	s->current_tm.tm_hour = (int)from_bcd((uint8_t)value);
	478	}
	479	break;
	480	case BCDDAYWEEK:
	481	if (s->reg_rtccon & RTC_ENABLE) {
	482	s->current_tm.tm_wday = (int)from_bcd((uint8_t)value);
	483	}
	484	break;
	485	case BCDDAY:
	486	if (s->reg_rtccon & RTC_ENABLE) {
	487	s->current_tm.tm_mday = (int)from_bcd((uint8_t)value);
	488	}
	489	break;
	490	case BCDMON:
	491	if (s->reg_rtccon & RTC_ENABLE) {
	492	s->current_tm.tm_mon = (int)from_bcd((uint8_t)value) - 1;
	493	}
	494	break;
	495	case BCDYEAR:
	496	if (s->reg_rtccon & RTC_ENABLE) {
	497	/* 3 digits */
	498	s->current_tm.tm_year = (int)from_bcd((uint8_t)value) +
	499	(int)from_bcd((uint8_t)((value >> 8) & 0x0f)) * 100;
	500	}
	501	break;
	502
	503	default:
f2ad5140 KK	504	qemu_log_mask(LOG_GUEST_ERROR,
	505	"exynos4210.rtc: bad write offset " TARGET_FMT_plx,
	506	offset);
7bdf43a7 OO	507	break;
	508
	509	}
	510	}
	511
	512	/*
	513	* Set default values to timer fields and registers
	514	*/
	515	static void exynos4210_rtc_reset(DeviceState *d)
	516	{
3ddacf27	517	Exynos4210RTCState *s = EXYNOS4210_RTC(d);
7bdf43a7	518
4688870d	519	qemu_get_timedate(&s->current_tm, 0);
7bdf43a7 OO	520
	521	DPRINTF("Get time from host: %d-%d-%d %2d:%02d:%02d\n",
	522	s->current_tm.tm_year, s->current_tm.tm_mon, s->current_tm.tm_mday,
	523	s->current_tm.tm_hour, s->current_tm.tm_min, s->current_tm.tm_sec);
	524
	525	s->reg_intp = 0;
	526	s->reg_rtccon = 0;
	527	s->reg_ticcnt = 0;
	528	s->reg_rtcalm = 0;
	529	s->reg_almsec = 0;
	530	s->reg_almmin = 0;
	531	s->reg_almhour = 0;
	532	s->reg_almday = 0;
	533	s->reg_almmon = 0;
	534	s->reg_almyear = 0;
	535
	536	s->reg_curticcnt = 0;
	537
	538	exynos4210_rtc_update_freq(s, s->reg_rtccon);
	539	ptimer_stop(s->ptimer);
	540	ptimer_stop(s->ptimer_1Hz);
	541	}
	542
	543	static const MemoryRegionOps exynos4210_rtc_ops = {
	544	.read = exynos4210_rtc_read,
	545	.write = exynos4210_rtc_write,
	546	.endianness = DEVICE_NATIVE_ENDIAN,
	547	};
	548
	549	/*
	550	* RTC timer initialization
	551	*/
c9d64639	552	static void exynos4210_rtc_init(Object *obj)
7bdf43a7	553	{
c9d64639 XZ	554	Exynos4210RTCState *s = EXYNOS4210_RTC(obj);
c9d64639 XZ	555	SysBusDevice *dev = SYS_BUS_DEVICE(obj);
7bdf43a7 OO	556	QEMUBH *bh;
	557
	558	bh = qemu_bh_new(exynos4210_rtc_tick, s);
e7ea81c3	559	s->ptimer = ptimer_init(bh, PTIMER_POLICY_DEFAULT);
7bdf43a7 OO	560	ptimer_set_freq(s->ptimer, RTC_BASE_FREQ);
	561	exynos4210_rtc_update_freq(s, 0);
	562
	563	bh = qemu_bh_new(exynos4210_rtc_1Hz_tick, s);
e7ea81c3	564	s->ptimer_1Hz = ptimer_init(bh, PTIMER_POLICY_DEFAULT);
7bdf43a7 OO	565	ptimer_set_freq(s->ptimer_1Hz, RTC_BASE_FREQ);
	566
	567	sysbus_init_irq(dev, &s->alm_irq);
	568	sysbus_init_irq(dev, &s->tick_irq);
	569
c9d64639	570	memory_region_init_io(&s->iomem, obj, &exynos4210_rtc_ops, s,
853dca12	571	"exynos4210-rtc", EXYNOS4210_RTC_REG_MEM_SIZE);
7bdf43a7	572	sysbus_init_mmio(dev, &s->iomem);
7bdf43a7 OO	573	}
	574
	575	static void exynos4210_rtc_class_init(ObjectClass klass, void data)
	576	{
	577	DeviceClass *dc = DEVICE_CLASS(klass);
7bdf43a7	578
7bdf43a7 OO	579	dc->reset = exynos4210_rtc_reset;
	580	dc->vmsd = &vmstate_exynos4210_rtc_state;
	581	}
	582
	583	static const TypeInfo exynos4210_rtc_info = {
3ddacf27	584	.name = TYPE_EXYNOS4210_RTC,
7bdf43a7 OO	585	.parent = TYPE_SYS_BUS_DEVICE,
7bdf43a7 OO	586	.instance_size = sizeof(Exynos4210RTCState),
c9d64639	587	.instance_init = exynos4210_rtc_init,
7bdf43a7 OO	588	.class_init = exynos4210_rtc_class_init,
	589	};
	590
	591	static void exynos4210_rtc_register_types(void)
	592	{
	593	type_register_static(&exynos4210_rtc_info);
	594	}
	595
	596	type_init(exynos4210_rtc_register_types)