[qemu.git] / hw / msix.c

/*
 * MSI-X device support
 *
 * This module includes support for MSI-X in pci devices.
 *
 * Author: Michael S. Tsirkin <[email protected]>
 *
 *  Copyright (c) 2009, Red Hat Inc, Michael S. Tsirkin ([email protected])
 *
 * This work is licensed under the terms of the GNU GPL, version 2.  See
 * the COPYING file in the top-level directory.
 *
 * Contributions after 2012-01-13 are licensed under the terms of the
 * GNU GPL, version 2 or (at your option) any later version.
 */

#include "hw.h"
#include "msix.h"
#include "pci.h"
#include "range.h"

#define MSIX_CAP_LENGTH 12

/* MSI enable bit and maskall bit are in byte 1 in FLAGS register */
#define MSIX_CONTROL_OFFSET (PCI_MSIX_FLAGS + 1)
#define MSIX_ENABLE_MASK (PCI_MSIX_FLAGS_ENABLE >> 8)
#define MSIX_MASKALL_MASK (PCI_MSIX_FLAGS_MASKALL >> 8)

/* How much space does an MSIX table need. */
/* The spec requires giving the table structure
 * a 4K aligned region all by itself. */
#define MSIX_PAGE_SIZE 0x1000
/* Reserve second half of the page for pending bits */
#define MSIX_PAGE_PENDING (MSIX_PAGE_SIZE / 2)
#define MSIX_MAX_ENTRIES 32


/* Flag for interrupt controller to declare MSI-X support */
int msix_supported;

/* Add MSI-X capability to the config space for the device. */
/* Given a bar and its size, add MSI-X table on top of it
 * and fill MSI-X capability in the config space.
 * Original bar size must be a power of 2 or 0.
 * New bar size is returned. */
static int msix_add_config(struct PCIDevice *pdev, unsigned short nentries,
                           unsigned bar_nr, unsigned bar_size)
{
    int config_offset;
    uint8_t *config;
    uint32_t new_size;

    if (nentries < 1 || nentries > PCI_MSIX_FLAGS_QSIZE + 1)
        return -EINVAL;
    if (bar_size > 0x80000000)
        return -ENOSPC;

    /* Add space for MSI-X structures */
    if (!bar_size) {
        new_size = MSIX_PAGE_SIZE;
    } else if (bar_size < MSIX_PAGE_SIZE) {
        bar_size = MSIX_PAGE_SIZE;
        new_size = MSIX_PAGE_SIZE * 2;
    } else {
        new_size = bar_size * 2;
    }

    pdev->msix_bar_size = new_size;
    config_offset = pci_add_capability(pdev, PCI_CAP_ID_MSIX,
                                       0, MSIX_CAP_LENGTH);
    if (config_offset < 0)
        return config_offset;
    config = pdev->config + config_offset;

    pci_set_word(config + PCI_MSIX_FLAGS, nentries - 1);
    /* Table on top of BAR */
    pci_set_long(config + PCI_MSIX_TABLE, bar_size | bar_nr);
    /* Pending bits on top of that */
    pci_set_long(config + PCI_MSIX_PBA, (bar_size + MSIX_PAGE_PENDING) |
                 bar_nr);
    pdev->msix_cap = config_offset;
    /* Make flags bit writable. */
    pdev->wmask[config_offset + MSIX_CONTROL_OFFSET] |= MSIX_ENABLE_MASK |
	    MSIX_MASKALL_MASK;
    pdev->msix_function_masked = true;
    return 0;
}

static uint64_t msix_mmio_read(void *opaque, target_phys_addr_t addr,
                               unsigned size)
{
    PCIDevice *dev = opaque;
    unsigned int offset = addr & (MSIX_PAGE_SIZE - 1) & ~0x3;
    void *page = dev->msix_table_page;

    return pci_get_long(page + offset);
}

static uint8_t msix_pending_mask(int vector)
{
    return 1 << (vector % 8);
}

static uint8_t *msix_pending_byte(PCIDevice *dev, int vector)
{
    return dev->msix_table_page + MSIX_PAGE_PENDING + vector / 8;
}

static int msix_is_pending(PCIDevice *dev, int vector)
{
    return *msix_pending_byte(dev, vector) & msix_pending_mask(vector);
}

static void msix_set_pending(PCIDevice *dev, int vector)
{
    *msix_pending_byte(dev, vector) |= msix_pending_mask(vector);
}

static void msix_clr_pending(PCIDevice *dev, int vector)
{
    *msix_pending_byte(dev, vector) &= ~msix_pending_mask(vector);
}

static bool msix_vector_masked(PCIDevice *dev, int vector, bool fmask)
{
    unsigned offset = vector * PCI_MSIX_ENTRY_SIZE + PCI_MSIX_ENTRY_VECTOR_CTRL;
    return fmask || dev->msix_table_page[offset] & PCI_MSIX_ENTRY_CTRL_MASKBIT;
}

static bool msix_is_masked(PCIDevice *dev, int vector)
{
    return msix_vector_masked(dev, vector, dev->msix_function_masked);
}

static void msix_handle_mask_update(PCIDevice *dev, int vector, bool was_masked)
{
    bool is_masked = msix_is_masked(dev, vector);
    if (is_masked == was_masked) {
        return;
    }

    if (!is_masked && msix_is_pending(dev, vector)) {
        msix_clr_pending(dev, vector);
        msix_notify(dev, vector);
    }
}

static void msix_update_function_masked(PCIDevice *dev)
{
    dev->msix_function_masked = !msix_enabled(dev) ||
        (dev->config[dev->msix_cap + MSIX_CONTROL_OFFSET] & MSIX_MASKALL_MASK);
}

/* Handle MSI-X capability config write. */
void msix_write_config(PCIDevice *dev, uint32_t addr,
                       uint32_t val, int len)
{
    unsigned enable_pos = dev->msix_cap + MSIX_CONTROL_OFFSET;
    int vector;
    bool was_masked;

    if (!range_covers_byte(addr, len, enable_pos)) {
        return;
    }

    was_masked = dev->msix_function_masked;
    msix_update_function_masked(dev);

    if (!msix_enabled(dev)) {
        return;
    }

    pci_device_deassert_intx(dev);

    if (dev->msix_function_masked == was_masked) {
        return;
    }

    for (vector = 0; vector < dev->msix_entries_nr; ++vector) {
        msix_handle_mask_update(dev, vector,
                                msix_vector_masked(dev, vector, was_masked));
    }
}

static void msix_mmio_write(void *opaque, target_phys_addr_t addr,
                            uint64_t val, unsigned size)
{
    PCIDevice *dev = opaque;
    unsigned int offset = addr & (MSIX_PAGE_SIZE - 1) & ~0x3;
    int vector = offset / PCI_MSIX_ENTRY_SIZE;
    bool was_masked;

    /* MSI-X page includes a read-only PBA and a writeable Vector Control. */
    if (vector >= dev->msix_entries_nr) {
        return;
    }

    was_masked = msix_is_masked(dev, vector);
    pci_set_long(dev->msix_table_page + offset, val);
    msix_handle_mask_update(dev, vector, was_masked);
}

static const MemoryRegionOps msix_mmio_ops = {
    .read = msix_mmio_read,
    .write = msix_mmio_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
    .valid = {
        .min_access_size = 4,
        .max_access_size = 4,
    },
};

static void msix_mmio_setup(PCIDevice *d, MemoryRegion *bar)
{
    uint8_t *config = d->config + d->msix_cap;
    uint32_t table = pci_get_long(config + PCI_MSIX_TABLE);
    uint32_t offset = table & ~(MSIX_PAGE_SIZE - 1);
    /* TODO: for assigned devices, we'll want to make it possible to map
     * pending bits separately in case they are in a separate bar. */

    memory_region_add_subregion(bar, offset, &d->msix_mmio);
}

static void msix_mask_all(struct PCIDevice *dev, unsigned nentries)
{
    int vector;
    for (vector = 0; vector < nentries; ++vector) {
        unsigned offset =
            vector * PCI_MSIX_ENTRY_SIZE + PCI_MSIX_ENTRY_VECTOR_CTRL;
        dev->msix_table_page[offset] |= PCI_MSIX_ENTRY_CTRL_MASKBIT;
    }
}

/* Initialize the MSI-X structures. Note: if MSI-X is supported, BAR size is
 * modified, it should be retrieved with msix_bar_size. */
int msix_init(struct PCIDevice *dev, unsigned short nentries,
              MemoryRegion *bar,
              unsigned bar_nr, unsigned bar_size)
{
    int ret;
    /* Nothing to do if MSI is not supported by interrupt controller */
    if (!msix_supported)
        return -ENOTSUP;

    if (nentries > MSIX_MAX_ENTRIES)
        return -EINVAL;

    dev->msix_entry_used = g_malloc0(MSIX_MAX_ENTRIES *
                                        sizeof *dev->msix_entry_used);

    dev->msix_table_page = g_malloc0(MSIX_PAGE_SIZE);
    msix_mask_all(dev, nentries);

    memory_region_init_io(&dev->msix_mmio, &msix_mmio_ops, dev,
                          "msix", MSIX_PAGE_SIZE);

    dev->msix_entries_nr = nentries;
    ret = msix_add_config(dev, nentries, bar_nr, bar_size);
    if (ret)
        goto err_config;

    dev->cap_present |= QEMU_PCI_CAP_MSIX;
    msix_mmio_setup(dev, bar);
    return 0;

err_config:
    dev->msix_entries_nr = 0;
    memory_region_destroy(&dev->msix_mmio);
    g_free(dev->msix_table_page);
    dev->msix_table_page = NULL;
    g_free(dev->msix_entry_used);
    dev->msix_entry_used = NULL;
    return ret;
}

static void msix_free_irq_entries(PCIDevice *dev)
{
    int vector;

    for (vector = 0; vector < dev->msix_entries_nr; ++vector) {
        dev->msix_entry_used[vector] = 0;
        msix_clr_pending(dev, vector);
    }
}

/* Clean up resources for the device. */
int msix_uninit(PCIDevice *dev, MemoryRegion *bar)
{
    if (!(dev->cap_present & QEMU_PCI_CAP_MSIX))
        return 0;
    pci_del_capability(dev, PCI_CAP_ID_MSIX, MSIX_CAP_LENGTH);
    dev->msix_cap = 0;
    msix_free_irq_entries(dev);
    dev->msix_entries_nr = 0;
    memory_region_del_subregion(bar, &dev->msix_mmio);
    memory_region_destroy(&dev->msix_mmio);
    g_free(dev->msix_table_page);
    dev->msix_table_page = NULL;
    g_free(dev->msix_entry_used);
    dev->msix_entry_used = NULL;
    dev->cap_present &= ~QEMU_PCI_CAP_MSIX;
    return 0;
}

void msix_save(PCIDevice *dev, QEMUFile *f)
{
    unsigned n = dev->msix_entries_nr;

    if (!(dev->cap_present & QEMU_PCI_CAP_MSIX)) {
        return;
    }

    qemu_put_buffer(f, dev->msix_table_page, n * PCI_MSIX_ENTRY_SIZE);
    qemu_put_buffer(f, dev->msix_table_page + MSIX_PAGE_PENDING, (n + 7) / 8);
}

/* Should be called after restoring the config space. */
void msix_load(PCIDevice *dev, QEMUFile *f)
{
    unsigned n = dev->msix_entries_nr;

    if (!(dev->cap_present & QEMU_PCI_CAP_MSIX)) {
        return;
    }

    msix_free_irq_entries(dev);
    qemu_get_buffer(f, dev->msix_table_page, n * PCI_MSIX_ENTRY_SIZE);
    qemu_get_buffer(f, dev->msix_table_page + MSIX_PAGE_PENDING, (n + 7) / 8);
    msix_update_function_masked(dev);
}

/* Does device support MSI-X? */
int msix_present(PCIDevice *dev)
{
    return dev->cap_present & QEMU_PCI_CAP_MSIX;
}

/* Is MSI-X enabled? */
int msix_enabled(PCIDevice *dev)
{
    return (dev->cap_present & QEMU_PCI_CAP_MSIX) &&
        (dev->config[dev->msix_cap + MSIX_CONTROL_OFFSET] &
         MSIX_ENABLE_MASK);
}

/* Size of bar where MSI-X table resides, or 0 if MSI-X not supported. */
uint32_t msix_bar_size(PCIDevice *dev)
{
    return (dev->cap_present & QEMU_PCI_CAP_MSIX) ?
        dev->msix_bar_size : 0;
}

/* Send an MSI-X message */
void msix_notify(PCIDevice *dev, unsigned vector)
{
    uint8_t *table_entry = dev->msix_table_page + vector * PCI_MSIX_ENTRY_SIZE;
    uint64_t address;
    uint32_t data;

    if (vector >= dev->msix_entries_nr || !dev->msix_entry_used[vector])
        return;
    if (msix_is_masked(dev, vector)) {
        msix_set_pending(dev, vector);
        return;
    }

    address = pci_get_quad(table_entry + PCI_MSIX_ENTRY_LOWER_ADDR);
    data = pci_get_long(table_entry + PCI_MSIX_ENTRY_DATA);
    stl_le_phys(address, data);
}

void msix_reset(PCIDevice *dev)
{
    if (!(dev->cap_present & QEMU_PCI_CAP_MSIX))
        return;
    msix_free_irq_entries(dev);
    dev->config[dev->msix_cap + MSIX_CONTROL_OFFSET] &=
	    ~dev->wmask[dev->msix_cap + MSIX_CONTROL_OFFSET];
    memset(dev->msix_table_page, 0, MSIX_PAGE_SIZE);
    msix_mask_all(dev, dev->msix_entries_nr);
}

/* PCI spec suggests that devices make it possible for software to configure
 * less vectors than supported by the device, but does not specify a standard
 * mechanism for devices to do so.
 *
 * We support this by asking devices to declare vectors software is going to
 * actually use, and checking this on the notification path. Devices that
 * don't want to follow the spec suggestion can declare all vectors as used. */

/* Mark vector as used. */
int msix_vector_use(PCIDevice *dev, unsigned vector)
{
    if (vector >= dev->msix_entries_nr)
        return -EINVAL;
    dev->msix_entry_used[vector]++;
    return 0;
}

/* Mark vector as unused. */
void msix_vector_unuse(PCIDevice *dev, unsigned vector)
{
    if (vector >= dev->msix_entries_nr || !dev->msix_entry_used[vector]) {
        return;
    }
    if (--dev->msix_entry_used[vector]) {
        return;
    }
    msix_clr_pending(dev, vector);
}

void msix_unuse_all_vectors(PCIDevice *dev)
{
    if (!(dev->cap_present & QEMU_PCI_CAP_MSIX))
        return;
    msix_free_irq_entries(dev);
}
Commit	Line	Data
02eb84d0 MT	1	/*
	2	* MSI-X device support
	3	*
	4	* This module includes support for MSI-X in pci devices.
	5	*
	6	* Author: Michael S. Tsirkin <[email protected]>
	7	*
	8	* Copyright (c) 2009, Red Hat Inc, Michael S. Tsirkin ([email protected])
	9	*
	10	* This work is licensed under the terms of the GNU GPL, version 2. See
	11	* the COPYING file in the top-level directory.
6b620ca3 PB	12	*
	13	* Contributions after 2012-01-13 are licensed under the terms of the
	14	* GNU GPL, version 2 or (at your option) any later version.
02eb84d0 MT	15	*/
	16
	17	#include "hw.h"
	18	#include "msix.h"
	19	#include "pci.h"
bf1b0071	20	#include "range.h"
02eb84d0	21
02eb84d0 MT	22	#define MSIX_CAP_LENGTH 12
02eb84d0 MT	23
2760952b MT	24	/* MSI enable bit and maskall bit are in byte 1 in FLAGS register */
2760952b MT	25	#define MSIX_CONTROL_OFFSET (PCI_MSIX_FLAGS + 1)
02eb84d0	26	#define MSIX_ENABLE_MASK (PCI_MSIX_FLAGS_ENABLE >> 8)
5b5cb086	27	#define MSIX_MASKALL_MASK (PCI_MSIX_FLAGS_MASKALL >> 8)
02eb84d0	28
5a1fc5e8 MT	29	/* How much space does an MSIX table need. */
	30	/* The spec requires giving the table structure
	31	* a 4K aligned region all by itself. */
	32	#define MSIX_PAGE_SIZE 0x1000
	33	/* Reserve second half of the page for pending bits */
	34	#define MSIX_PAGE_PENDING (MSIX_PAGE_SIZE / 2)
02eb84d0 MT	35	#define MSIX_MAX_ENTRIES 32
	36
	37
02eb84d0 MT	38	/* Flag for interrupt controller to declare MSI-X support */
	39	int msix_supported;
	40
	41	/* Add MSI-X capability to the config space for the device. */
	42	/* Given a bar and its size, add MSI-X table on top of it
	43	* and fill MSI-X capability in the config space.
	44	* Original bar size must be a power of 2 or 0.
	45	* New bar size is returned. */
	46	static int msix_add_config(struct PCIDevice *pdev, unsigned short nentries,
	47	unsigned bar_nr, unsigned bar_size)
	48	{
	49	int config_offset;
	50	uint8_t *config;
	51	uint32_t new_size;
	52
	53	if (nentries < 1 \|\| nentries > PCI_MSIX_FLAGS_QSIZE + 1)
	54	return -EINVAL;
	55	if (bar_size > 0x80000000)
	56	return -ENOSPC;
	57
	58	/* Add space for MSI-X structures */
5e520a7d	59	if (!bar_size) {
5a1fc5e8 MT	60	new_size = MSIX_PAGE_SIZE;
	61	} else if (bar_size < MSIX_PAGE_SIZE) {
	62	bar_size = MSIX_PAGE_SIZE;
	63	new_size = MSIX_PAGE_SIZE * 2;
	64	} else {
02eb84d0	65	new_size = bar_size * 2;
5a1fc5e8	66	}
02eb84d0 MT	67
02eb84d0 MT	68	pdev->msix_bar_size = new_size;
ca77089d IY	69	config_offset = pci_add_capability(pdev, PCI_CAP_ID_MSIX,
ca77089d IY	70	0, MSIX_CAP_LENGTH);
02eb84d0 MT	71	if (config_offset < 0)
	72	return config_offset;
	73	config = pdev->config + config_offset;
	74
	75	pci_set_word(config + PCI_MSIX_FLAGS, nentries - 1);
	76	/* Table on top of BAR */
01731cfb	77	pci_set_long(config + PCI_MSIX_TABLE, bar_size \| bar_nr);
02eb84d0	78	/* Pending bits on top of that */
01731cfb	79	pci_set_long(config + PCI_MSIX_PBA, (bar_size + MSIX_PAGE_PENDING) \|
5a1fc5e8	80	bar_nr);
02eb84d0	81	pdev->msix_cap = config_offset;
ebabb67a	82	/* Make flags bit writable. */
5b5cb086 MT	83	pdev->wmask[config_offset + MSIX_CONTROL_OFFSET] \|= MSIX_ENABLE_MASK \|
5b5cb086 MT	84	MSIX_MASKALL_MASK;
50322249	85	pdev->msix_function_masked = true;
02eb84d0 MT	86	return 0;
	87	}
	88
95524ae8 AK	89	static uint64_t msix_mmio_read(void *opaque, target_phys_addr_t addr,
95524ae8 AK	90	unsigned size)
02eb84d0 MT	91	{
02eb84d0 MT	92	PCIDevice *dev = opaque;
76f5159d	93	unsigned int offset = addr & (MSIX_PAGE_SIZE - 1) & ~0x3;
02eb84d0	94	void *page = dev->msix_table_page;
02eb84d0	95
76f5159d	96	return pci_get_long(page + offset);
02eb84d0 MT	97	}
02eb84d0 MT	98
02eb84d0 MT	99	static uint8_t msix_pending_mask(int vector)
	100	{
	101	return 1 << (vector % 8);
	102	}
	103
	104	static uint8_t msix_pending_byte(PCIDevice dev, int vector)
	105	{
5a1fc5e8	106	return dev->msix_table_page + MSIX_PAGE_PENDING + vector / 8;
02eb84d0 MT	107	}
	108
	109	static int msix_is_pending(PCIDevice *dev, int vector)
	110	{
	111	return *msix_pending_byte(dev, vector) & msix_pending_mask(vector);
	112	}
	113
	114	static void msix_set_pending(PCIDevice *dev, int vector)
	115	{
	116	*msix_pending_byte(dev, vector) \|= msix_pending_mask(vector);
	117	}
	118
	119	static void msix_clr_pending(PCIDevice *dev, int vector)
	120	{
	121	*msix_pending_byte(dev, vector) &= ~msix_pending_mask(vector);
	122	}
	123
ae392c41	124	static bool msix_vector_masked(PCIDevice *dev, int vector, bool fmask)
02eb84d0	125	{
ae392c41 MT	126	unsigned offset = vector * PCI_MSIX_ENTRY_SIZE + PCI_MSIX_ENTRY_VECTOR_CTRL;
ae392c41 MT	127	return fmask \|\| dev->msix_table_page[offset] & PCI_MSIX_ENTRY_CTRL_MASKBIT;
5b5cb086 MT	128	}
5b5cb086 MT	129
ae392c41	130	static bool msix_is_masked(PCIDevice *dev, int vector)
5b5cb086	131	{
ae392c41 MT	132	return msix_vector_masked(dev, vector, dev->msix_function_masked);
	133	}
	134
	135	static void msix_handle_mask_update(PCIDevice *dev, int vector, bool was_masked)
	136	{
	137	bool is_masked = msix_is_masked(dev, vector);
	138	if (is_masked == was_masked) {
	139	return;
	140	}
	141
	142	if (!is_masked && msix_is_pending(dev, vector)) {
5b5cb086 MT	143	msix_clr_pending(dev, vector);
	144	msix_notify(dev, vector);
	145	}
	146	}
	147
50322249 MT	148	static void msix_update_function_masked(PCIDevice *dev)
	149	{
	150	dev->msix_function_masked = !msix_enabled(dev) \|\|
	151	(dev->config[dev->msix_cap + MSIX_CONTROL_OFFSET] & MSIX_MASKALL_MASK);
	152	}
	153
5b5cb086 MT	154	/* Handle MSI-X capability config write. */
	155	void msix_write_config(PCIDevice *dev, uint32_t addr,
	156	uint32_t val, int len)
	157	{
	158	unsigned enable_pos = dev->msix_cap + MSIX_CONTROL_OFFSET;
	159	int vector;
50322249	160	bool was_masked;
5b5cb086	161
98a3cb02	162	if (!range_covers_byte(addr, len, enable_pos)) {
5b5cb086 MT	163	return;
	164	}
	165
50322249 MT	166	was_masked = dev->msix_function_masked;
	167	msix_update_function_masked(dev);
	168
5b5cb086 MT	169	if (!msix_enabled(dev)) {
	170	return;
	171	}
	172
e407bf13	173	pci_device_deassert_intx(dev);
5b5cb086	174
50322249	175	if (dev->msix_function_masked == was_masked) {
5b5cb086 MT	176	return;
	177	}
	178
	179	for (vector = 0; vector < dev->msix_entries_nr; ++vector) {
ae392c41 MT	180	msix_handle_mask_update(dev, vector,
ae392c41 MT	181	msix_vector_masked(dev, vector, was_masked));
5b5cb086	182	}
02eb84d0 MT	183	}
02eb84d0 MT	184
95524ae8 AK	185	static void msix_mmio_write(void *opaque, target_phys_addr_t addr,
95524ae8 AK	186	uint64_t val, unsigned size)
02eb84d0 MT	187	{
02eb84d0 MT	188	PCIDevice *dev = opaque;
76f5159d	189	unsigned int offset = addr & (MSIX_PAGE_SIZE - 1) & ~0x3;
01731cfb	190	int vector = offset / PCI_MSIX_ENTRY_SIZE;
ae392c41	191	bool was_masked;
9a93b617 MT	192
	193	/* MSI-X page includes a read-only PBA and a writeable Vector Control. */
	194	if (vector >= dev->msix_entries_nr) {
	195	return;
	196	}
	197
ae392c41	198	was_masked = msix_is_masked(dev, vector);
76f5159d	199	pci_set_long(dev->msix_table_page + offset, val);
ae392c41	200	msix_handle_mask_update(dev, vector, was_masked);
02eb84d0 MT	201	}
02eb84d0 MT	202
95524ae8 AK	203	static const MemoryRegionOps msix_mmio_ops = {
	204	.read = msix_mmio_read,
	205	.write = msix_mmio_write,
	206	.endianness = DEVICE_NATIVE_ENDIAN,
	207	.valid = {
	208	.min_access_size = 4,
	209	.max_access_size = 4,
	210	},
02eb84d0 MT	211	};
02eb84d0 MT	212
95524ae8	213	static void msix_mmio_setup(PCIDevice d, MemoryRegion bar)
02eb84d0 MT	214	{
02eb84d0 MT	215	uint8_t *config = d->config + d->msix_cap;
01731cfb	216	uint32_t table = pci_get_long(config + PCI_MSIX_TABLE);
5a1fc5e8	217	uint32_t offset = table & ~(MSIX_PAGE_SIZE - 1);
02eb84d0 MT	218	/* TODO: for assigned devices, we'll want to make it possible to map
02eb84d0 MT	219	* pending bits separately in case they are in a separate bar. */
02eb84d0	220
95524ae8	221	memory_region_add_subregion(bar, offset, &d->msix_mmio);
02eb84d0 MT	222	}
02eb84d0 MT	223
ae1be0bb MT	224	static void msix_mask_all(struct PCIDevice *dev, unsigned nentries)
	225	{
	226	int vector;
	227	for (vector = 0; vector < nentries; ++vector) {
01731cfb JK	228	unsigned offset =
	229	vector * PCI_MSIX_ENTRY_SIZE + PCI_MSIX_ENTRY_VECTOR_CTRL;
	230	dev->msix_table_page[offset] \|= PCI_MSIX_ENTRY_CTRL_MASKBIT;
ae1be0bb MT	231	}
	232	}
	233
02eb84d0 MT	234	/* Initialize the MSI-X structures. Note: if MSI-X is supported, BAR size is
	235	* modified, it should be retrieved with msix_bar_size. */
	236	int msix_init(struct PCIDevice *dev, unsigned short nentries,
95524ae8	237	MemoryRegion *bar,
5a1fc5e8	238	unsigned bar_nr, unsigned bar_size)
02eb84d0 MT	239	{
	240	int ret;
	241	/* Nothing to do if MSI is not supported by interrupt controller */
	242	if (!msix_supported)
	243	return -ENOTSUP;
	244
	245	if (nentries > MSIX_MAX_ENTRIES)
	246	return -EINVAL;
	247
7267c094	248	dev->msix_entry_used = g_malloc0(MSIX_MAX_ENTRIES *
02eb84d0 MT	249	sizeof *dev->msix_entry_used);
02eb84d0 MT	250
7267c094	251	dev->msix_table_page = g_malloc0(MSIX_PAGE_SIZE);
ae1be0bb	252	msix_mask_all(dev, nentries);
02eb84d0	253
95524ae8 AK	254	memory_region_init_io(&dev->msix_mmio, &msix_mmio_ops, dev,
95524ae8 AK	255	"msix", MSIX_PAGE_SIZE);
02eb84d0 MT	256
	257	dev->msix_entries_nr = nentries;
	258	ret = msix_add_config(dev, nentries, bar_nr, bar_size);
	259	if (ret)
	260	goto err_config;
	261
	262	dev->cap_present \|= QEMU_PCI_CAP_MSIX;
95524ae8	263	msix_mmio_setup(dev, bar);
02eb84d0 MT	264	return 0;
	265
	266	err_config:
3174ecd1	267	dev->msix_entries_nr = 0;
95524ae8	268	memory_region_destroy(&dev->msix_mmio);
7267c094	269	g_free(dev->msix_table_page);
02eb84d0	270	dev->msix_table_page = NULL;
7267c094	271	g_free(dev->msix_entry_used);
02eb84d0 MT	272	dev->msix_entry_used = NULL;
	273	return ret;
	274	}
	275
98304c84 MT	276	static void msix_free_irq_entries(PCIDevice *dev)
	277	{
	278	int vector;
	279
	280	for (vector = 0; vector < dev->msix_entries_nr; ++vector) {
	281	dev->msix_entry_used[vector] = 0;
	282	msix_clr_pending(dev, vector);
	283	}
	284	}
	285
02eb84d0	286	/* Clean up resources for the device. */
95524ae8	287	int msix_uninit(PCIDevice dev, MemoryRegion bar)
02eb84d0 MT	288	{
	289	if (!(dev->cap_present & QEMU_PCI_CAP_MSIX))
	290	return 0;
	291	pci_del_capability(dev, PCI_CAP_ID_MSIX, MSIX_CAP_LENGTH);
	292	dev->msix_cap = 0;
	293	msix_free_irq_entries(dev);
	294	dev->msix_entries_nr = 0;
95524ae8 AK	295	memory_region_del_subregion(bar, &dev->msix_mmio);
95524ae8 AK	296	memory_region_destroy(&dev->msix_mmio);
7267c094	297	g_free(dev->msix_table_page);
02eb84d0	298	dev->msix_table_page = NULL;
7267c094	299	g_free(dev->msix_entry_used);
02eb84d0 MT	300	dev->msix_entry_used = NULL;
	301	dev->cap_present &= ~QEMU_PCI_CAP_MSIX;
	302	return 0;
	303	}
	304
	305	void msix_save(PCIDevice dev, QEMUFile f)
	306	{
9a3e12c8 MT	307	unsigned n = dev->msix_entries_nr;
9a3e12c8 MT	308
72755a70	309	if (!(dev->cap_present & QEMU_PCI_CAP_MSIX)) {
9a3e12c8	310	return;
72755a70	311	}
9a3e12c8	312
01731cfb	313	qemu_put_buffer(f, dev->msix_table_page, n * PCI_MSIX_ENTRY_SIZE);
5a1fc5e8	314	qemu_put_buffer(f, dev->msix_table_page + MSIX_PAGE_PENDING, (n + 7) / 8);
02eb84d0 MT	315	}
	316
	317	/* Should be called after restoring the config space. */
	318	void msix_load(PCIDevice dev, QEMUFile f)
	319	{
	320	unsigned n = dev->msix_entries_nr;
	321
98846d73	322	if (!(dev->cap_present & QEMU_PCI_CAP_MSIX)) {
02eb84d0	323	return;
98846d73	324	}
02eb84d0	325
4bfd1712	326	msix_free_irq_entries(dev);
01731cfb	327	qemu_get_buffer(f, dev->msix_table_page, n * PCI_MSIX_ENTRY_SIZE);
5a1fc5e8	328	qemu_get_buffer(f, dev->msix_table_page + MSIX_PAGE_PENDING, (n + 7) / 8);
50322249	329	msix_update_function_masked(dev);
02eb84d0 MT	330	}
	331
	332	/* Does device support MSI-X? */
	333	int msix_present(PCIDevice *dev)
	334	{
	335	return dev->cap_present & QEMU_PCI_CAP_MSIX;
	336	}
	337
	338	/* Is MSI-X enabled? */
	339	int msix_enabled(PCIDevice *dev)
	340	{
	341	return (dev->cap_present & QEMU_PCI_CAP_MSIX) &&
2760952b	342	(dev->config[dev->msix_cap + MSIX_CONTROL_OFFSET] &
02eb84d0 MT	343	MSIX_ENABLE_MASK);
	344	}
	345
	346	/* Size of bar where MSI-X table resides, or 0 if MSI-X not supported. */
	347	uint32_t msix_bar_size(PCIDevice *dev)
	348	{
	349	return (dev->cap_present & QEMU_PCI_CAP_MSIX) ?
	350	dev->msix_bar_size : 0;
	351	}
	352
	353	/* Send an MSI-X message */
	354	void msix_notify(PCIDevice *dev, unsigned vector)
	355	{
01731cfb	356	uint8_t table_entry = dev->msix_table_page + vector PCI_MSIX_ENTRY_SIZE;
02eb84d0 MT	357	uint64_t address;
	358	uint32_t data;
	359
	360	if (vector >= dev->msix_entries_nr \|\| !dev->msix_entry_used[vector])
	361	return;
	362	if (msix_is_masked(dev, vector)) {
	363	msix_set_pending(dev, vector);
	364	return;
	365	}
	366
01731cfb JK	367	address = pci_get_quad(table_entry + PCI_MSIX_ENTRY_LOWER_ADDR);
01731cfb JK	368	data = pci_get_long(table_entry + PCI_MSIX_ENTRY_DATA);
ae5d3eb4	369	stl_le_phys(address, data);
02eb84d0 MT	370	}
	371
	372	void msix_reset(PCIDevice *dev)
	373	{
	374	if (!(dev->cap_present & QEMU_PCI_CAP_MSIX))
	375	return;
	376	msix_free_irq_entries(dev);
2760952b MT	377	dev->config[dev->msix_cap + MSIX_CONTROL_OFFSET] &=
2760952b MT	378	~dev->wmask[dev->msix_cap + MSIX_CONTROL_OFFSET];
5a1fc5e8	379	memset(dev->msix_table_page, 0, MSIX_PAGE_SIZE);
ae1be0bb	380	msix_mask_all(dev, dev->msix_entries_nr);
02eb84d0 MT	381	}
	382
	383	/* PCI spec suggests that devices make it possible for software to configure
	384	* less vectors than supported by the device, but does not specify a standard
	385	* mechanism for devices to do so.
	386	*
	387	* We support this by asking devices to declare vectors software is going to
	388	* actually use, and checking this on the notification path. Devices that
	389	* don't want to follow the spec suggestion can declare all vectors as used. */
	390
	391	/* Mark vector as used. */
	392	int msix_vector_use(PCIDevice *dev, unsigned vector)
	393	{
	394	if (vector >= dev->msix_entries_nr)
	395	return -EINVAL;
	396	dev->msix_entry_used[vector]++;
	397	return 0;
	398	}
	399
	400	/* Mark vector as unused. */
	401	void msix_vector_unuse(PCIDevice *dev, unsigned vector)
	402	{
98304c84 MT	403	if (vector >= dev->msix_entries_nr \|\| !dev->msix_entry_used[vector]) {
	404	return;
	405	}
	406	if (--dev->msix_entry_used[vector]) {
	407	return;
	408	}
	409	msix_clr_pending(dev, vector);
02eb84d0	410	}
b5f28bca MT	411
	412	void msix_unuse_all_vectors(PCIDevice *dev)
	413	{
	414	if (!(dev->cap_present & QEMU_PCI_CAP_MSIX))
	415	return;
	416	msix_free_irq_entries(dev);
	417	}