projects / qemu.git / blame
| Commit | Line | Data |
|---|---|---|
| cfb0a50a IY |
1 | #ifndef QEMU_PCI_INTERNALS_H |
| 2 | #define QEMU_PCI_INTERNALS_H | |
| 3 | ||
| 4 | /* | |
| 5 | * This header files is private to pci.c and pci_bridge.c | |
| 6 | * So following structures are opaque to others and shouldn't be | |
| 7 | * accessed. | |
| 68f79994 IY |
8 | * |
| 9 | * For pci-to-pci bridge needs to include this header file to embed | |
| 10 | * PCIBridge in its structure or to get sizeof(PCIBridge), | |
| 11 | * However, they shouldn't access those following members directly. | |
| 12 | * Use accessor function in pci.h, pci_bridge.h | |
| cfb0a50a IY |
13 | */ |
| 14 | ||
| 0d936928 AL |
15 | #define TYPE_PCI_BUS "PCI" |
| 16 | #define PCI_BUS(obj) OBJECT_CHECK(PCIBus, (obj), TYPE_PCI_BUS) | |
| cfb0a50a IY |
17 | |
| 18 | struct PCIBus { | |
| 19 | BusState qbus; | |
| 5fa45de5 DG |
20 | PCIDMAContextFunc dma_context_fn; |
| 21 | void *dma_context_opaque; | |
| 6f3279b5 | 22 | uint8_t devfn_min; |
| cfb0a50a IY |
23 | pci_set_irq_fn set_irq; |
| 24 | pci_map_irq_fn map_irq; | |
| 3afa9bb4 | 25 | pci_route_irq_fn route_intx_to_irq; |
| cfb0a50a IY |
26 | pci_hotplug_fn hotplug; |
| 27 | DeviceState *hotplug_qdev; | |
| 28 | void *irq_opaque; | |
| 90a20dbb | 29 | PCIDevice *devices[PCI_SLOT_MAX * PCI_FUNC_MAX]; |
| cfb0a50a | 30 | PCIDevice *parent_dev; |
| 5968eca3 AK |
31 | MemoryRegion *address_space_mem; |
| 32 | MemoryRegion *address_space_io; | |
| cfb0a50a IY |
33 | |
| 34 | QLIST_HEAD(, PCIBus) child; /* this will be replaced by qdev later */ | |
| 35 | QLIST_ENTRY(PCIBus) sibling;/* this will be replaced by qdev later */ | |
| 36 | ||
| 37 | /* The bus IRQ state is the logical OR of the connected devices. | |
| 38 | Keep a count of the number of devices with raised IRQs. */ | |
| 39 | int nirq; | |
| 40 | int *irq_count; | |
| 41 | }; | |
| 42 | ||
| 68f79994 | 43 | struct PCIBridge { |
| cfb0a50a | 44 | PCIDevice dev; |
| 68f79994 IY |
45 | |
| 46 | /* private member */ | |
| 7e98e3af | 47 | PCIBus sec_bus; |
| 336411ca MT |
48 | /* |
| 49 | * Memory regions for the bridge's address spaces. These regions are not | |
| 50 | * directly added to system_memory/system_io or its descendants. | |
| 51 | * Bridge's secondary bus points to these, so that devices | |
| 52 | * under the bridge see these regions as its address spaces. | |
| 53 | * The regions are as large as the entire address space - | |
| 54 | * they don't take into account any windows. | |
| 55 | */ | |
| 56 | MemoryRegion address_space_mem; | |
| 57 | MemoryRegion address_space_io; | |
| 58 | /* | |
| 59 | * Aliases for each of the address space windows that the bridge | |
| 60 | * can forward. Mapped into the bridge's parent's address space, | |
| 61 | * as subregions. | |
| 62 | */ | |
| 7df32ca0 MT |
63 | MemoryRegion alias_pref_mem; |
| 64 | MemoryRegion alias_mem; | |
| 65 | MemoryRegion alias_io; | |
| 68f79994 IY |
66 | pci_map_irq_fn map_irq; |
| 67 | const char *bus_name; | |
| 68 | }; | |
| cfb0a50a IY |
69 | |
| 70 | #endif /* QEMU_PCI_INTERNALS_H */ |