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suppressed -enable-audio and simplified -soundhw option handling (malc)
[qemu.git] / cpu-exec.c
CommitLineData
7d13299d
FB		 1/*
2 * i386 emulator main execution loop
3 *
66321a11 4 * Copyright (c) 2003-2005 Fabrice Bellard
7d13299d 5 *
3ef693a0
FB		 6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
7d13299d 10 *
3ef693a0
FB		 11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
7d13299d 15 *
3ef693a0
FB		 16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
7d13299d 19 */
e4533c7a 20#include "config.h"
93ac68bc 21#include "exec.h"
956034d7 22#include "disas.h"
7d13299d 23
fbf9eeb3
FB		 24#if !defined(CONFIG_SOFTMMU)
25#undef EAX
26#undef ECX
27#undef EDX
28#undef EBX
29#undef ESP
30#undef EBP
31#undef ESI
32#undef EDI
33#undef EIP
34#include <signal.h>
35#include <sys/ucontext.h>
36#endif
37
36bdbe54
FB		 38int tb_invalidated_flag;
39
dc99065b 40//#define DEBUG_EXEC
9de5e440 41//#define DEBUG_SIGNAL
7d13299d 42
93ac68bc 43#if defined(TARGET_ARM) || defined(TARGET_SPARC)
e4533c7a
FB		 44/* XXX: unify with i386 target */
45void cpu_loop_exit(void)
46{
47 longjmp(env->jmp_env, 1);
48}
49#endif
3475187d
FB		 50#ifndef TARGET_SPARC
51#define reg_T2
52#endif
e4533c7a 53
fbf9eeb3
FB		 54/* exit the current TB from a signal handler. The host registers are
55 restored in a state compatible with the CPU emulator
56 */
57void cpu_resume_from_signal(CPUState *env1, void *puc)
58{
59#if !defined(CONFIG_SOFTMMU)
60 struct ucontext *uc = puc;
61#endif
62
63 env = env1;
64
65 /* XXX: restore cpu registers saved in host registers */
66
67#if !defined(CONFIG_SOFTMMU)
68 if (puc) {
69 /* XXX: use siglongjmp ? */
70 sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
71 }
72#endif
73 longjmp(env->jmp_env, 1);
74}
75
8a40a180
FB		 76
77static TranslationBlock *tb_find_slow(target_ulong pc,
78 target_ulong cs_base,
79 unsigned int flags)
80{
81 TranslationBlock *tb, **ptb1;
82 int code_gen_size;
83 unsigned int h;
84 target_ulong phys_pc, phys_page1, phys_page2, virt_page2;
85 uint8_t *tc_ptr;
86
87 spin_lock(&tb_lock);
88
89 tb_invalidated_flag = 0;
90
91 regs_to_env(); /* XXX: do it just before cpu_gen_code() */
92
93 /* find translated block using physical mappings */
94 phys_pc = get_phys_addr_code(env, pc);
95 phys_page1 = phys_pc & TARGET_PAGE_MASK;
96 phys_page2 = -1;
97 h = tb_phys_hash_func(phys_pc);
98 ptb1 = &tb_phys_hash[h];
99 for(;;) {
100 tb = *ptb1;
101 if (!tb)
102 goto not_found;
103 if (tb->pc == pc &&
104 tb->page_addr[0] == phys_page1 &&
105 tb->cs_base == cs_base &&
106 tb->flags == flags) {
107 /* check next page if needed */
108 if (tb->page_addr[1] != -1) {
109 virt_page2 = (pc & TARGET_PAGE_MASK) +
110 TARGET_PAGE_SIZE;
111 phys_page2 = get_phys_addr_code(env, virt_page2);
112 if (tb->page_addr[1] == phys_page2)
113 goto found;
114 } else {
115 goto found;
116 }
117 }
118 ptb1 = &tb->phys_hash_next;
119 }
120 not_found:
121 /* if no translated code available, then translate it now */
122 tb = tb_alloc(pc);
123 if (!tb) {
124 /* flush must be done */
125 tb_flush(env);
126 /* cannot fail at this point */
127 tb = tb_alloc(pc);
128 /* don't forget to invalidate previous TB info */
129 T0 = 0;
130 }
131 tc_ptr = code_gen_ptr;
132 tb->tc_ptr = tc_ptr;
133 tb->cs_base = cs_base;
134 tb->flags = flags;
135 cpu_gen_code(env, tb, CODE_GEN_MAX_SIZE, &code_gen_size);
136 code_gen_ptr = (void *)(((unsigned long)code_gen_ptr + code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1));
137
138 /* check next page if needed */
139 virt_page2 = (pc + tb->size - 1) & TARGET_PAGE_MASK;
140 phys_page2 = -1;
141 if ((pc & TARGET_PAGE_MASK) != virt_page2) {
142 phys_page2 = get_phys_addr_code(env, virt_page2);
143 }
144 tb_link_phys(tb, phys_pc, phys_page2);
145
146 found:
147 if (tb_invalidated_flag) {
148 /* as some TB could have been invalidated because
149 of memory exceptions while generating the code, we
150 must recompute the hash index here */
151 T0 = 0;
152 }
153 /* we add the TB in the virtual pc hash table */
154 env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)] = tb;
155 spin_unlock(&tb_lock);
156 return tb;
157}
158
159static inline TranslationBlock *tb_find_fast(void)
160{
161 TranslationBlock *tb;
162 target_ulong cs_base, pc;
163 unsigned int flags;
164
165 /* we record a subset of the CPU state. It will
166 always be the same before a given translated block
167 is executed. */
168#if defined(TARGET_I386)
169 flags = env->hflags;
170 flags |= (env->eflags & (IOPL_MASK | TF_MASK | VM_MASK));
171 cs_base = env->segs[R_CS].base;
172 pc = cs_base + env->eip;
173#elif defined(TARGET_ARM)
174 flags = env->thumb | (env->vfp.vec_len << 1)
b5ff1b31
FB		 175 | (env->vfp.vec_stride << 4);
176 if ((env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR)
177 flags |= (1 << 6);
8a40a180
FB		 178 cs_base = 0;
179 pc = env->regs[15];
180#elif defined(TARGET_SPARC)
181#ifdef TARGET_SPARC64
182 flags = (env->pstate << 2) | ((env->lsu & (DMMU_E | IMMU_E)) >> 2);
183#else
184 flags = env->psrs | ((env->mmuregs[0] & (MMU_E | MMU_NF)) << 1);
185#endif
186 cs_base = env->npc;
187 pc = env->pc;
188#elif defined(TARGET_PPC)
189 flags = (msr_pr << MSR_PR) | (msr_fp << MSR_FP) |
190 (msr_se << MSR_SE) | (msr_le << MSR_LE);
191 cs_base = 0;
192 pc = env->nip;
193#elif defined(TARGET_MIPS)
6810e154 194 flags = env->hflags & (MIPS_HFLAGS_TMASK | MIPS_HFLAG_BMASK);
cc9442b9 195 cs_base = 0;
8a40a180
FB		 196 pc = env->PC;
197#else
198#error unsupported CPU
199#endif
200 tb = env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)];
201 if (__builtin_expect(!tb || tb->pc != pc || tb->cs_base != cs_base ||
202 tb->flags != flags, 0)) {
203 tb = tb_find_slow(pc, cs_base, flags);
204 }
205 return tb;
206}
207
208
7d13299d
FB		 209/* main execution loop */
210
e4533c7a 211int cpu_exec(CPUState *env1)
7d13299d 212{
3475187d
FB		 213 int saved_T0, saved_T1;
214#if defined(reg_T2)
215 int saved_T2;
216#endif
e4533c7a 217 CPUState *saved_env;
3475187d 218#if defined(TARGET_I386)
04369ff2
FB		 219#ifdef reg_EAX
220 int saved_EAX;
221#endif
222#ifdef reg_ECX
223 int saved_ECX;
224#endif
225#ifdef reg_EDX
226 int saved_EDX;
227#endif
228#ifdef reg_EBX
229 int saved_EBX;
230#endif
231#ifdef reg_ESP
232 int saved_ESP;
233#endif
234#ifdef reg_EBP
235 int saved_EBP;
236#endif
237#ifdef reg_ESI
238 int saved_ESI;
239#endif
240#ifdef reg_EDI
241 int saved_EDI;
8c6939c0 242#endif
3475187d
FB		 243#elif defined(TARGET_SPARC)
244#if defined(reg_REGWPTR)
245 uint32_t *saved_regwptr;
246#endif
247#endif
8c6939c0
FB		 248#ifdef __sparc__
249 int saved_i7, tmp_T0;
04369ff2 250#endif
8a40a180 251 int ret, interrupt_request;
7d13299d 252 void (*gen_func)(void);
8a40a180 253 TranslationBlock *tb;
c27004ec 254 uint8_t *tc_ptr;
8c6939c0 255
5a1e3cfc
FB		 256#if defined(TARGET_I386)
257 /* handle exit of HALTED state */
258 if (env1->hflags & HF_HALTED_MASK) {
259 /* disable halt condition */
260 if ((env1->interrupt_request & CPU_INTERRUPT_HARD) &&
261 (env1->eflags & IF_MASK)) {
262 env1->hflags &= ~HF_HALTED_MASK;
263 } else {
264 return EXCP_HALTED;
e80e1cc4
FB		 265 }
266 }
267#elif defined(TARGET_PPC)
50443c98 268 if (env1->halted) {
e80e1cc4
FB		 269 if (env1->msr[MSR_EE] &&
270 (env1->interrupt_request &
271 (CPU_INTERRUPT_HARD | CPU_INTERRUPT_TIMER))) {
50443c98 272 env1->halted = 0;
e80e1cc4
FB		 273 } else {
274 return EXCP_HALTED;
5a1e3cfc
FB		 275 }
276 }
ba3c64fb
FB		 277#elif defined(TARGET_SPARC)
278 if (env1->halted) {
279 if ((env1->interrupt_request & CPU_INTERRUPT_HARD) &&
280 (env1->psret != 0)) {
281 env1->halted = 0;
282 } else {
283 return EXCP_HALTED;
284 }
285 }
9332f9da
FB		 286#elif defined(TARGET_ARM)
287 if (env1->halted) {
288 /* An interrupt wakes the CPU even if the I and F CPSR bits are
289 set. */
290 if (env1->interrupt_request
291 & (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD)) {
292 env1->halted = 0;
293 } else {
294 return EXCP_HALTED;
295 }
296 }
6810e154
FB		 297#elif defined(TARGET_MIPS)
298 if (env1->halted) {
299 if (env1->interrupt_request &
300 (CPU_INTERRUPT_HARD | CPU_INTERRUPT_TIMER)) {
301 env1->halted = 0;
302 } else {
303 return EXCP_HALTED;
304 }
305 }
5a1e3cfc
FB		 306#endif
307
6a00d601
FB		 308 cpu_single_env = env1;
309
7d13299d 310 /* first we save global registers */
c27004ec
FB		 311 saved_env = env;
312 env = env1;
7d13299d
FB		 313 saved_T0 = T0;
314 saved_T1 = T1;
3475187d 315#if defined(reg_T2)
e4533c7a 316 saved_T2 = T2;
3475187d 317#endif
e4533c7a
FB		 318#ifdef __sparc__
319 /* we also save i7 because longjmp may not restore it */
320 asm volatile ("mov %%i7, %0" : "=r" (saved_i7));
321#endif
322
323#if defined(TARGET_I386)
04369ff2
FB		 324#ifdef reg_EAX
325 saved_EAX = EAX;
04369ff2
FB		 326#endif
327#ifdef reg_ECX
328 saved_ECX = ECX;
04369ff2
FB		 329#endif
330#ifdef reg_EDX
331 saved_EDX = EDX;
04369ff2
FB		 332#endif
333#ifdef reg_EBX
334 saved_EBX = EBX;
04369ff2
FB		 335#endif
336#ifdef reg_ESP
337 saved_ESP = ESP;
04369ff2
FB		 338#endif
339#ifdef reg_EBP
340 saved_EBP = EBP;
04369ff2
FB		 341#endif
342#ifdef reg_ESI
343 saved_ESI = ESI;
04369ff2
FB		 344#endif
345#ifdef reg_EDI
346 saved_EDI = EDI;
04369ff2 347#endif
0d1a29f9
FB		 348
349 env_to_regs();
9de5e440 350 /* put eflags in CPU temporary format */
fc2b4c48
FB		 351 CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
352 DF = 1 - (2 * ((env->eflags >> 10) & 1));
9de5e440 353 CC_OP = CC_OP_EFLAGS;
fc2b4c48 354 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
e4533c7a 355#elif defined(TARGET_ARM)
93ac68bc 356#elif defined(TARGET_SPARC)
3475187d
FB		 357#if defined(reg_REGWPTR)
358 saved_regwptr = REGWPTR;
359#endif
67867308 360#elif defined(TARGET_PPC)
6af0bf9c 361#elif defined(TARGET_MIPS)
e4533c7a
FB		 362#else
363#error unsupported target CPU
364#endif
3fb2ded1 365 env->exception_index = -1;
9d27abd9 366
7d13299d 367 /* prepare setjmp context for exception handling */
3fb2ded1
FB		 368 for(;;) {
369 if (setjmp(env->jmp_env) == 0) {
ee8b7021 370 env->current_tb = NULL;
3fb2ded1
FB		 371 /* if an exception is pending, we execute it here */
372 if (env->exception_index >= 0) {
373 if (env->exception_index >= EXCP_INTERRUPT) {
374 /* exit request from the cpu execution loop */
375 ret = env->exception_index;
376 break;
377 } else if (env->user_mode_only) {
378 /* if user mode only, we simulate a fake exception
379 which will be hanlded outside the cpu execution
380 loop */
83479e77 381#if defined(TARGET_I386)
3fb2ded1
FB		 382 do_interrupt_user(env->exception_index,
383 env->exception_is_int,
384 env->error_code,
385 env->exception_next_eip);
83479e77 386#endif
3fb2ded1
FB		 387 ret = env->exception_index;
388 break;
389 } else {
83479e77 390#if defined(TARGET_I386)
3fb2ded1
FB		 391 /* simulate a real cpu exception. On i386, it can
392 trigger new exceptions, but we do not handle
393 double or triple faults yet. */
394 do_interrupt(env->exception_index,
395 env->exception_is_int,
396 env->error_code,
d05e66d2 397 env->exception_next_eip, 0);
ce09776b
FB		 398#elif defined(TARGET_PPC)
399 do_interrupt(env);
6af0bf9c
FB		 400#elif defined(TARGET_MIPS)
401 do_interrupt(env);
e95c8d51 402#elif defined(TARGET_SPARC)
1a0c3292 403 do_interrupt(env->exception_index);
b5ff1b31
FB		 404#elif defined(TARGET_ARM)
405 do_interrupt(env);
83479e77 406#endif
3fb2ded1
FB		 407 }
408 env->exception_index = -1;
9df217a3
FB		 409 }
410#ifdef USE_KQEMU
411 if (kqemu_is_ok(env) && env->interrupt_request == 0) {
412 int ret;
413 env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
414 ret = kqemu_cpu_exec(env);
415 /* put eflags in CPU temporary format */
416 CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
417 DF = 1 - (2 * ((env->eflags >> 10) & 1));
418 CC_OP = CC_OP_EFLAGS;
419 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
420 if (ret == 1) {
421 /* exception */
422 longjmp(env->jmp_env, 1);
423 } else if (ret == 2) {
424 /* softmmu execution needed */
425 } else {
426 if (env->interrupt_request != 0) {
427 /* hardware interrupt will be executed just after */
428 } else {
429 /* otherwise, we restart */
430 longjmp(env->jmp_env, 1);
431 }
432 }
3fb2ded1 433 }
9df217a3
FB		 434#endif
435
3fb2ded1
FB		 436 T0 = 0; /* force lookup of first TB */
437 for(;;) {
8c6939c0 438#ifdef __sparc__
3fb2ded1
FB		 439 /* g1 can be modified by some libc? functions */
440 tmp_T0 = T0;
8c6939c0 441#endif
68a79315 442 interrupt_request = env->interrupt_request;
2e255c6b 443 if (__builtin_expect(interrupt_request, 0)) {
68a79315
FB		 444#if defined(TARGET_I386)
445 /* if hardware interrupt pending, we execute it */
446 if ((interrupt_request & CPU_INTERRUPT_HARD) &&
3f337316
FB		 447 (env->eflags & IF_MASK) &&
448 !(env->hflags & HF_INHIBIT_IRQ_MASK)) {
68a79315 449 int intno;
fbf9eeb3 450 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
a541f297 451 intno = cpu_get_pic_interrupt(env);
f193c797 452 if (loglevel & CPU_LOG_TB_IN_ASM) {
68a79315
FB		 453 fprintf(logfile, "Servicing hardware INT=0x%02x\n", intno);
454 }
d05e66d2 455 do_interrupt(intno, 0, 0, 0, 1);
907a5b26
FB		 456 /* ensure that no TB jump will be modified as
457 the program flow was changed */
458#ifdef __sparc__
459 tmp_T0 = 0;
460#else
461 T0 = 0;
462#endif
68a79315 463 }
ce09776b 464#elif defined(TARGET_PPC)
9fddaa0c
FB		 465#if 0
466 if ((interrupt_request & CPU_INTERRUPT_RESET)) {
467 cpu_ppc_reset(env);
468 }
469#endif
470 if (msr_ee != 0) {
8a40a180 471 if ((interrupt_request & CPU_INTERRUPT_HARD)) {
9fddaa0c
FB		 472 /* Raise it */
473 env->exception_index = EXCP_EXTERNAL;
474 env->error_code = 0;
ce09776b 475 do_interrupt(env);
8a40a180
FB		 476 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
477#ifdef __sparc__
478 tmp_T0 = 0;
479#else
480 T0 = 0;
481#endif
482 } else if ((interrupt_request & CPU_INTERRUPT_TIMER)) {
483 /* Raise it */
484 env->exception_index = EXCP_DECR;
485 env->error_code = 0;
486 do_interrupt(env);
9fddaa0c 487 env->interrupt_request &= ~CPU_INTERRUPT_TIMER;
8a40a180
FB		 488#ifdef __sparc__
489 tmp_T0 = 0;
490#else
491 T0 = 0;
492#endif
493 }
ce09776b 494 }
6af0bf9c
FB		 495#elif defined(TARGET_MIPS)
496 if ((interrupt_request & CPU_INTERRUPT_HARD) &&
497 (env->CP0_Status & (1 << CP0St_IE)) &&
7ebab699 498 (env->CP0_Status & env->CP0_Cause & 0x0000FF00) &&
6af0bf9c
FB		 499 !(env->hflags & MIPS_HFLAG_EXL) &&
500 !(env->hflags & MIPS_HFLAG_ERL) &&
501 !(env->hflags & MIPS_HFLAG_DM)) {
502 /* Raise it */
503 env->exception_index = EXCP_EXT_INTERRUPT;
504 env->error_code = 0;
505 do_interrupt(env);
506 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
8a40a180
FB		 507#ifdef __sparc__
508 tmp_T0 = 0;
509#else
510 T0 = 0;
511#endif
6af0bf9c 512 }
e95c8d51 513#elif defined(TARGET_SPARC)
66321a11
FB		 514 if ((interrupt_request & CPU_INTERRUPT_HARD) &&
515 (env->psret != 0)) {
516 int pil = env->interrupt_index & 15;
517 int type = env->interrupt_index & 0xf0;
518
519 if (((type == TT_EXTINT) &&
520 (pil == 15 || pil > env->psrpil)) ||
521 type != TT_EXTINT) {
522 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
523 do_interrupt(env->interrupt_index);
524 env->interrupt_index = 0;
8a40a180
FB		 525#ifdef __sparc__
526 tmp_T0 = 0;
527#else
528 T0 = 0;
529#endif
66321a11 530 }
e95c8d51
FB		 531 } else if (interrupt_request & CPU_INTERRUPT_TIMER) {
532 //do_interrupt(0, 0, 0, 0, 0);
533 env->interrupt_request &= ~CPU_INTERRUPT_TIMER;
ba3c64fb
FB		 534 } else if (interrupt_request & CPU_INTERRUPT_HALT) {
535 env1->halted = 1;
536 return EXCP_HALTED;
537 }
b5ff1b31
FB		 538#elif defined(TARGET_ARM)
539 if (interrupt_request & CPU_INTERRUPT_FIQ
540 && !(env->uncached_cpsr & CPSR_F)) {
541 env->exception_index = EXCP_FIQ;
542 do_interrupt(env);
543 }
544 if (interrupt_request & CPU_INTERRUPT_HARD
545 && !(env->uncached_cpsr & CPSR_I)) {
546 env->exception_index = EXCP_IRQ;
547 do_interrupt(env);
548 }
68a79315 549#endif
b5ff1b31 550 if (env->interrupt_request & CPU_INTERRUPT_EXITTB) {
bf3e8bf1
FB		 551 env->interrupt_request &= ~CPU_INTERRUPT_EXITTB;
552 /* ensure that no TB jump will be modified as
553 the program flow was changed */
554#ifdef __sparc__
555 tmp_T0 = 0;
556#else
557 T0 = 0;
558#endif
559 }
68a79315
FB		 560 if (interrupt_request & CPU_INTERRUPT_EXIT) {
561 env->interrupt_request &= ~CPU_INTERRUPT_EXIT;
562 env->exception_index = EXCP_INTERRUPT;
563 cpu_loop_exit();
564 }
3fb2ded1 565 }
7d13299d 566#ifdef DEBUG_EXEC
b5ff1b31 567 if ((loglevel & CPU_LOG_TB_CPU)) {
e4533c7a 568#if defined(TARGET_I386)
3fb2ded1 569 /* restore flags in standard format */
fc9f715d 570#ifdef reg_EAX
3fb2ded1 571 env->regs[R_EAX] = EAX;
fc9f715d
FB		 572#endif
573#ifdef reg_EBX
3fb2ded1 574 env->regs[R_EBX] = EBX;
fc9f715d
FB		 575#endif
576#ifdef reg_ECX
3fb2ded1 577 env->regs[R_ECX] = ECX;
fc9f715d
FB		 578#endif
579#ifdef reg_EDX
3fb2ded1 580 env->regs[R_EDX] = EDX;
fc9f715d
FB		 581#endif
582#ifdef reg_ESI
3fb2ded1 583 env->regs[R_ESI] = ESI;
fc9f715d
FB		 584#endif
585#ifdef reg_EDI
3fb2ded1 586 env->regs[R_EDI] = EDI;
fc9f715d
FB		 587#endif
588#ifdef reg_EBP
3fb2ded1 589 env->regs[R_EBP] = EBP;
fc9f715d
FB		 590#endif
591#ifdef reg_ESP
3fb2ded1 592 env->regs[R_ESP] = ESP;
fc9f715d 593#endif
3fb2ded1 594 env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
7fe48483 595 cpu_dump_state(env, logfile, fprintf, X86_DUMP_CCOP);
3fb2ded1 596 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
e4533c7a 597#elif defined(TARGET_ARM)
7fe48483 598 cpu_dump_state(env, logfile, fprintf, 0);
93ac68bc 599#elif defined(TARGET_SPARC)
3475187d
FB		 600 REGWPTR = env->regbase + (env->cwp * 16);
601 env->regwptr = REGWPTR;
602 cpu_dump_state(env, logfile, fprintf, 0);
67867308 603#elif defined(TARGET_PPC)
7fe48483 604 cpu_dump_state(env, logfile, fprintf, 0);
6af0bf9c
FB		 605#elif defined(TARGET_MIPS)
606 cpu_dump_state(env, logfile, fprintf, 0);
e4533c7a
FB		 607#else
608#error unsupported target CPU
609#endif
3fb2ded1 610 }
7d13299d 611#endif
8a40a180 612 tb = tb_find_fast();
9d27abd9 613#ifdef DEBUG_EXEC
c1135f61 614 if ((loglevel & CPU_LOG_EXEC)) {
c27004ec
FB		 615 fprintf(logfile, "Trace 0x%08lx [" TARGET_FMT_lx "] %s\n",
616 (long)tb->tc_ptr, tb->pc,
617 lookup_symbol(tb->pc));
3fb2ded1 618 }
9d27abd9 619#endif
8c6939c0 620#ifdef __sparc__
3fb2ded1 621 T0 = tmp_T0;
8c6939c0 622#endif
8a40a180
FB		 623 /* see if we can patch the calling TB. When the TB
624 spans two pages, we cannot safely do a direct
625 jump. */
c27004ec 626 {
8a40a180
FB		 627 if (T0 != 0 &&
628 tb->page_addr[1] == -1
bf3e8bf1
FB		 629#if defined(TARGET_I386) && defined(USE_CODE_COPY)
630 && (tb->cflags & CF_CODE_COPY) ==
631 (((TranslationBlock *)(T0 & ~3))->cflags & CF_CODE_COPY)
632#endif
633 ) {
3fb2ded1 634 spin_lock(&tb_lock);
c27004ec 635 tb_add_jump((TranslationBlock *)(long)(T0 & ~3), T0 & 3, tb);
97eb5b14
FB		 636#if defined(USE_CODE_COPY)
637 /* propagates the FP use info */
638 ((TranslationBlock *)(T0 & ~3))->cflags |=
639 (tb->cflags & CF_FP_USED);
640#endif
3fb2ded1
FB		 641 spin_unlock(&tb_lock);
642 }
c27004ec 643 }
3fb2ded1 644 tc_ptr = tb->tc_ptr;
83479e77 645 env->current_tb = tb;
3fb2ded1
FB		 646 /* execute the generated code */
647 gen_func = (void *)tc_ptr;
8c6939c0 648#if defined(__sparc__)
3fb2ded1
FB		 649 __asm__ __volatile__("call %0\n\t"
650 "mov %%o7,%%i0"
651 : /* no outputs */
652 : "r" (gen_func)
653 : "i0", "i1", "i2", "i3", "i4", "i5");
8c6939c0 654#elif defined(__arm__)
3fb2ded1
FB		 655 asm volatile ("mov pc, %0\n\t"
656 ".global exec_loop\n\t"
657 "exec_loop:\n\t"
658 : /* no outputs */
659 : "r" (gen_func)
660 : "r1", "r2", "r3", "r8", "r9", "r10", "r12", "r14");
bf3e8bf1
FB		 661#elif defined(TARGET_I386) && defined(USE_CODE_COPY)
662{
663 if (!(tb->cflags & CF_CODE_COPY)) {
97eb5b14
FB		 664 if ((tb->cflags & CF_FP_USED) && env->native_fp_regs) {
665 save_native_fp_state(env);
666 }
bf3e8bf1
FB		 667 gen_func();
668 } else {
97eb5b14
FB		 669 if ((tb->cflags & CF_FP_USED) && !env->native_fp_regs) {
670 restore_native_fp_state(env);
671 }
bf3e8bf1
FB		 672 /* we work with native eflags */
673 CC_SRC = cc_table[CC_OP].compute_all();
674 CC_OP = CC_OP_EFLAGS;
675 asm(".globl exec_loop\n"
676 "\n"
677 "debug1:\n"
678 " pushl %%ebp\n"
679 " fs movl %10, %9\n"
680 " fs movl %11, %%eax\n"
681 " andl $0x400, %%eax\n"
682 " fs orl %8, %%eax\n"
683 " pushl %%eax\n"
684 " popf\n"
685 " fs movl %%esp, %12\n"
686 " fs movl %0, %%eax\n"
687 " fs movl %1, %%ecx\n"
688 " fs movl %2, %%edx\n"
689 " fs movl %3, %%ebx\n"
690 " fs movl %4, %%esp\n"
691 " fs movl %5, %%ebp\n"
692 " fs movl %6, %%esi\n"
693 " fs movl %7, %%edi\n"
694 " fs jmp *%9\n"
695 "exec_loop:\n"
696 " fs movl %%esp, %4\n"
697 " fs movl %12, %%esp\n"
698 " fs movl %%eax, %0\n"
699 " fs movl %%ecx, %1\n"
700 " fs movl %%edx, %2\n"
701 " fs movl %%ebx, %3\n"
702 " fs movl %%ebp, %5\n"
703 " fs movl %%esi, %6\n"
704 " fs movl %%edi, %7\n"
705 " pushf\n"
706 " popl %%eax\n"
707 " movl %%eax, %%ecx\n"
708 " andl $0x400, %%ecx\n"
709 " shrl $9, %%ecx\n"
710 " andl $0x8d5, %%eax\n"
711 " fs movl %%eax, %8\n"
712 " movl $1, %%eax\n"
713 " subl %%ecx, %%eax\n"
714 " fs movl %%eax, %11\n"
715 " fs movl %9, %%ebx\n" /* get T0 value */
716 " popl %%ebp\n"
717 :
718 : "m" (*(uint8_t *)offsetof(CPUState, regs[0])),
719 "m" (*(uint8_t *)offsetof(CPUState, regs[1])),
720 "m" (*(uint8_t *)offsetof(CPUState, regs[2])),
721 "m" (*(uint8_t *)offsetof(CPUState, regs[3])),
722 "m" (*(uint8_t *)offsetof(CPUState, regs[4])),
723 "m" (*(uint8_t *)offsetof(CPUState, regs[5])),
724 "m" (*(uint8_t *)offsetof(CPUState, regs[6])),
725 "m" (*(uint8_t *)offsetof(CPUState, regs[7])),
726 "m" (*(uint8_t *)offsetof(CPUState, cc_src)),
727 "m" (*(uint8_t *)offsetof(CPUState, tmp0)),
728 "a" (gen_func),
729 "m" (*(uint8_t *)offsetof(CPUState, df)),
730 "m" (*(uint8_t *)offsetof(CPUState, saved_esp))
731 : "%ecx", "%edx"
732 );
733 }
734}
b8076a74
FB		 735#elif defined(__ia64)
736 struct fptr {
737 void *ip;
738 void *gp;
739 } fp;
740
741 fp.ip = tc_ptr;
742 fp.gp = code_gen_buffer + 2 * (1 << 20);
743 (*(void (*)(void)) &fp)();
ae228531 744#else
3fb2ded1 745 gen_func();
ae228531 746#endif
83479e77 747 env->current_tb = NULL;
4cbf74b6
FB		 748 /* reset soft MMU for next block (it can currently
749 only be set by a memory fault) */
750#if defined(TARGET_I386) && !defined(CONFIG_SOFTMMU)
3f337316
FB		 751 if (env->hflags & HF_SOFTMMU_MASK) {
752 env->hflags &= ~HF_SOFTMMU_MASK;
4cbf74b6
FB		 753 /* do not allow linking to another block */
754 T0 = 0;
755 }
756#endif
3fb2ded1
FB		 757 }
758 } else {
0d1a29f9 759 env_to_regs();
7d13299d 760 }
3fb2ded1
FB		 761 } /* for(;;) */
762
7d13299d 763
e4533c7a 764#if defined(TARGET_I386)
97eb5b14
FB		 765#if defined(USE_CODE_COPY)
766 if (env->native_fp_regs) {
767 save_native_fp_state(env);
768 }
769#endif
9de5e440 770 /* restore flags in standard format */
fc2b4c48 771 env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
9de5e440 772
7d13299d 773 /* restore global registers */
04369ff2
FB		 774#ifdef reg_EAX
775 EAX = saved_EAX;
776#endif
777#ifdef reg_ECX
778 ECX = saved_ECX;
779#endif
780#ifdef reg_EDX
781 EDX = saved_EDX;
782#endif
783#ifdef reg_EBX
784 EBX = saved_EBX;
785#endif
786#ifdef reg_ESP
787 ESP = saved_ESP;
788#endif
789#ifdef reg_EBP
790 EBP = saved_EBP;
791#endif
792#ifdef reg_ESI
793 ESI = saved_ESI;
794#endif
795#ifdef reg_EDI
796 EDI = saved_EDI;
8c6939c0 797#endif
e4533c7a 798#elif defined(TARGET_ARM)
b7bcbe95 799 /* XXX: Save/restore host fpu exception state?. */
93ac68bc 800#elif defined(TARGET_SPARC)
3475187d
FB		 801#if defined(reg_REGWPTR)
802 REGWPTR = saved_regwptr;
803#endif
67867308 804#elif defined(TARGET_PPC)
6af0bf9c 805#elif defined(TARGET_MIPS)
e4533c7a
FB		 806#else
807#error unsupported target CPU
808#endif
8c6939c0
FB		 809#ifdef __sparc__
810 asm volatile ("mov %0, %%i7" : : "r" (saved_i7));
04369ff2 811#endif
7d13299d
FB		 812 T0 = saved_T0;
813 T1 = saved_T1;
3475187d 814#if defined(reg_T2)
e4533c7a 815 T2 = saved_T2;
3475187d 816#endif
7d13299d 817 env = saved_env;
6a00d601
FB		 818 /* fail safe : never use cpu_single_env outside cpu_exec() */
819 cpu_single_env = NULL;
7d13299d
FB		 820 return ret;
821}
6dbad63e 822
fbf9eeb3
FB		 823/* must only be called from the generated code as an exception can be
824 generated */
825void tb_invalidate_page_range(target_ulong start, target_ulong end)
826{
dc5d0b3d
FB		 827 /* XXX: cannot enable it yet because it yields to MMU exception
828 where NIP != read address on PowerPC */
829#if 0
fbf9eeb3
FB		 830 target_ulong phys_addr;
831 phys_addr = get_phys_addr_code(env, start);
832 tb_invalidate_phys_page_range(phys_addr, phys_addr + end - start, 0);
dc5d0b3d 833#endif
fbf9eeb3
FB		 834}
835
1a18c71b 836#if defined(TARGET_I386) && defined(CONFIG_USER_ONLY)
e4533c7a 837
6dbad63e
FB		 838void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector)
839{
840 CPUX86State *saved_env;
841
842 saved_env = env;
843 env = s;
a412ac57 844 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) {
a513fe19 845 selector &= 0xffff;
2e255c6b 846 cpu_x86_load_seg_cache(env, seg_reg, selector,
c27004ec 847 (selector << 4), 0xffff, 0);
a513fe19 848 } else {
b453b70b 849 load_seg(seg_reg, selector);
a513fe19 850 }
6dbad63e
FB		 851 env = saved_env;
852}
9de5e440 853
d0a1ffc9
FB		 854void cpu_x86_fsave(CPUX86State *s, uint8_t *ptr, int data32)
855{
856 CPUX86State *saved_env;
857
858 saved_env = env;
859 env = s;
860
c27004ec 861 helper_fsave((target_ulong)ptr, data32);
d0a1ffc9
FB		 862
863 env = saved_env;
864}
865
866void cpu_x86_frstor(CPUX86State *s, uint8_t *ptr, int data32)
867{
868 CPUX86State *saved_env;
869
870 saved_env = env;
871 env = s;
872
c27004ec 873 helper_frstor((target_ulong)ptr, data32);
d0a1ffc9
FB		 874
875 env = saved_env;
876}
877
e4533c7a
FB		 878#endif /* TARGET_I386 */
879
67b915a5
FB		 880#if !defined(CONFIG_SOFTMMU)
881
3fb2ded1
FB		 882#if defined(TARGET_I386)
883
b56dad1c 884/* 'pc' is the host PC at which the exception was raised. 'address' is
fd6ce8f6
FB		 885 the effective address of the memory exception. 'is_write' is 1 if a
886 write caused the exception and otherwise 0'. 'old_set' is the
887 signal set which should be restored */
2b413144 888static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
bf3e8bf1
FB		 889 int is_write, sigset_t *old_set,
890 void *puc)
9de5e440 891{
a513fe19
FB		 892 TranslationBlock *tb;
893 int ret;
68a79315 894
83479e77
FB		 895 if (cpu_single_env)
896 env = cpu_single_env; /* XXX: find a correct solution for multithread */
fd6ce8f6 897#if defined(DEBUG_SIGNAL)
bf3e8bf1
FB		 898 qemu_printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
899 pc, address, is_write, *(unsigned long *)old_set);
9de5e440 900#endif
25eb4484 901 /* XXX: locking issue */
fbf9eeb3 902 if (is_write && page_unprotect(address, pc, puc)) {
fd6ce8f6
FB		 903 return 1;
904 }
fbf9eeb3 905
3fb2ded1 906 /* see if it is an MMU fault */
93a40ea9
FB		 907 ret = cpu_x86_handle_mmu_fault(env, address, is_write,
908 ((env->hflags & HF_CPL_MASK) == 3), 0);
3fb2ded1
FB		 909 if (ret < 0)
910 return 0; /* not an MMU fault */
911 if (ret == 0)
912 return 1; /* the MMU fault was handled without causing real CPU fault */
913 /* now we have a real cpu fault */
a513fe19
FB		 914 tb = tb_find_pc(pc);
915 if (tb) {
9de5e440
FB		 916 /* the PC is inside the translated code. It means that we have
917 a virtual CPU fault */
bf3e8bf1 918 cpu_restore_state(tb, env, pc, puc);
3fb2ded1 919 }
4cbf74b6 920 if (ret == 1) {
3fb2ded1 921#if 0
4cbf74b6
FB		 922 printf("PF exception: EIP=0x%08x CR2=0x%08x error=0x%x\n",
923 env->eip, env->cr[2], env->error_code);
3fb2ded1 924#endif
4cbf74b6
FB		 925 /* we restore the process signal mask as the sigreturn should
926 do it (XXX: use sigsetjmp) */
927 sigprocmask(SIG_SETMASK, old_set, NULL);
54ca9095 928 raise_exception_err(env->exception_index, env->error_code);
4cbf74b6
FB		 929 } else {
930 /* activate soft MMU for this block */
3f337316 931 env->hflags |= HF_SOFTMMU_MASK;
fbf9eeb3 932 cpu_resume_from_signal(env, puc);
4cbf74b6 933 }
3fb2ded1
FB		 934 /* never comes here */
935 return 1;
936}
937
e4533c7a 938#elif defined(TARGET_ARM)
3fb2ded1 939static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
bf3e8bf1
FB		 940 int is_write, sigset_t *old_set,
941 void *puc)
3fb2ded1 942{
68016c62
FB		 943 TranslationBlock *tb;
944 int ret;
945
946 if (cpu_single_env)
947 env = cpu_single_env; /* XXX: find a correct solution for multithread */
948#if defined(DEBUG_SIGNAL)
949 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
950 pc, address, is_write, *(unsigned long *)old_set);
951#endif
9f0777ed
FB		 952 /* XXX: locking issue */
953 if (is_write && page_unprotect(address, pc, puc)) {
954 return 1;
955 }
68016c62
FB		 956 /* see if it is an MMU fault */
957 ret = cpu_arm_handle_mmu_fault(env, address, is_write, 1, 0);
958 if (ret < 0)
959 return 0; /* not an MMU fault */
960 if (ret == 0)
961 return 1; /* the MMU fault was handled without causing real CPU fault */
962 /* now we have a real cpu fault */
963 tb = tb_find_pc(pc);
964 if (tb) {
965 /* the PC is inside the translated code. It means that we have
966 a virtual CPU fault */
967 cpu_restore_state(tb, env, pc, puc);
968 }
969 /* we restore the process signal mask as the sigreturn should
970 do it (XXX: use sigsetjmp) */
971 sigprocmask(SIG_SETMASK, old_set, NULL);
972 cpu_loop_exit();
3fb2ded1 973}
93ac68bc
FB		 974#elif defined(TARGET_SPARC)
975static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
bf3e8bf1
FB		 976 int is_write, sigset_t *old_set,
977 void *puc)
93ac68bc 978{
68016c62
FB		 979 TranslationBlock *tb;
980 int ret;
981
982 if (cpu_single_env)
983 env = cpu_single_env; /* XXX: find a correct solution for multithread */
984#if defined(DEBUG_SIGNAL)
985 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
986 pc, address, is_write, *(unsigned long *)old_set);
987#endif
b453b70b 988 /* XXX: locking issue */
fbf9eeb3 989 if (is_write && page_unprotect(address, pc, puc)) {
b453b70b
FB		 990 return 1;
991 }
68016c62
FB		 992 /* see if it is an MMU fault */
993 ret = cpu_sparc_handle_mmu_fault(env, address, is_write, 1, 0);
994 if (ret < 0)
995 return 0; /* not an MMU fault */
996 if (ret == 0)
997 return 1; /* the MMU fault was handled without causing real CPU fault */
998 /* now we have a real cpu fault */
999 tb = tb_find_pc(pc);
1000 if (tb) {
1001 /* the PC is inside the translated code. It means that we have
1002 a virtual CPU fault */
1003 cpu_restore_state(tb, env, pc, puc);
1004 }
1005 /* we restore the process signal mask as the sigreturn should
1006 do it (XXX: use sigsetjmp) */
1007 sigprocmask(SIG_SETMASK, old_set, NULL);
1008 cpu_loop_exit();
93ac68bc 1009}
67867308
FB		 1010#elif defined (TARGET_PPC)
1011static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
bf3e8bf1
FB		 1012 int is_write, sigset_t *old_set,
1013 void *puc)
67867308
FB		 1014{
1015 TranslationBlock *tb;
ce09776b 1016 int ret;
67867308 1017
67867308
FB		 1018 if (cpu_single_env)
1019 env = cpu_single_env; /* XXX: find a correct solution for multithread */
67867308
FB		 1020#if defined(DEBUG_SIGNAL)
1021 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1022 pc, address, is_write, *(unsigned long *)old_set);
1023#endif
1024 /* XXX: locking issue */
fbf9eeb3 1025 if (is_write && page_unprotect(address, pc, puc)) {
67867308
FB		 1026 return 1;
1027 }
1028
ce09776b 1029 /* see if it is an MMU fault */
7f957d28 1030 ret = cpu_ppc_handle_mmu_fault(env, address, is_write, msr_pr, 0);
ce09776b
FB		 1031 if (ret < 0)
1032 return 0; /* not an MMU fault */
1033 if (ret == 0)
1034 return 1; /* the MMU fault was handled without causing real CPU fault */
1035
67867308
FB		 1036 /* now we have a real cpu fault */
1037 tb = tb_find_pc(pc);
1038 if (tb) {
1039 /* the PC is inside the translated code. It means that we have
1040 a virtual CPU fault */
bf3e8bf1 1041 cpu_restore_state(tb, env, pc, puc);
67867308 1042 }
ce09776b 1043 if (ret == 1) {
67867308 1044#if 0
ce09776b
FB		 1045 printf("PF exception: NIP=0x%08x error=0x%x %p\n",
1046 env->nip, env->error_code, tb);
67867308
FB		 1047#endif
1048 /* we restore the process signal mask as the sigreturn should
1049 do it (XXX: use sigsetjmp) */
bf3e8bf1 1050 sigprocmask(SIG_SETMASK, old_set, NULL);
9fddaa0c 1051 do_raise_exception_err(env->exception_index, env->error_code);
ce09776b
FB		 1052 } else {
1053 /* activate soft MMU for this block */
fbf9eeb3 1054 cpu_resume_from_signal(env, puc);
ce09776b 1055 }
67867308
FB		 1056 /* never comes here */
1057 return 1;
1058}
6af0bf9c
FB		 1059
1060#elif defined (TARGET_MIPS)
1061static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
1062 int is_write, sigset_t *old_set,
1063 void *puc)
1064{
1065 TranslationBlock *tb;
1066 int ret;
1067
1068 if (cpu_single_env)
1069 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1070#if defined(DEBUG_SIGNAL)
1071 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1072 pc, address, is_write, *(unsigned long *)old_set);
1073#endif
1074 /* XXX: locking issue */
1075 if (is_write && page_unprotect(address, pc, puc)) {
1076 return 1;
1077 }
1078
1079 /* see if it is an MMU fault */
cc9442b9 1080 ret = cpu_mips_handle_mmu_fault(env, address, is_write, 1, 0);
6af0bf9c
FB		 1081 if (ret < 0)
1082 return 0; /* not an MMU fault */
1083 if (ret == 0)
1084 return 1; /* the MMU fault was handled without causing real CPU fault */
1085
1086 /* now we have a real cpu fault */
1087 tb = tb_find_pc(pc);
1088 if (tb) {
1089 /* the PC is inside the translated code. It means that we have
1090 a virtual CPU fault */
1091 cpu_restore_state(tb, env, pc, puc);
1092 }
1093 if (ret == 1) {
1094#if 0
1095 printf("PF exception: NIP=0x%08x error=0x%x %p\n",
1096 env->nip, env->error_code, tb);
1097#endif
1098 /* we restore the process signal mask as the sigreturn should
1099 do it (XXX: use sigsetjmp) */
1100 sigprocmask(SIG_SETMASK, old_set, NULL);
1101 do_raise_exception_err(env->exception_index, env->error_code);
1102 } else {
1103 /* activate soft MMU for this block */
1104 cpu_resume_from_signal(env, puc);
1105 }
1106 /* never comes here */
1107 return 1;
1108}
1109
e4533c7a
FB		 1110#else
1111#error unsupported target CPU
1112#endif
9de5e440 1113
2b413144
FB		 1114#if defined(__i386__)
1115
bf3e8bf1
FB		 1116#if defined(USE_CODE_COPY)
1117static void cpu_send_trap(unsigned long pc, int trap,
1118 struct ucontext *uc)
1119{
1120 TranslationBlock *tb;
1121
1122 if (cpu_single_env)
1123 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1124 /* now we have a real cpu fault */
1125 tb = tb_find_pc(pc);
1126 if (tb) {
1127 /* the PC is inside the translated code. It means that we have
1128 a virtual CPU fault */
1129 cpu_restore_state(tb, env, pc, uc);
1130 }
1131 sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
1132 raise_exception_err(trap, env->error_code);
1133}
1134#endif
1135
e4533c7a
FB		 1136int cpu_signal_handler(int host_signum, struct siginfo *info,
1137 void *puc)
9de5e440 1138{
9de5e440
FB		 1139 struct ucontext *uc = puc;
1140 unsigned long pc;
bf3e8bf1 1141 int trapno;
97eb5b14 1142
d691f669
FB		 1143#ifndef REG_EIP
1144/* for glibc 2.1 */
fd6ce8f6
FB		 1145#define REG_EIP EIP
1146#define REG_ERR ERR
1147#define REG_TRAPNO TRAPNO
d691f669 1148#endif
fc2b4c48 1149 pc = uc->uc_mcontext.gregs[REG_EIP];
bf3e8bf1
FB		 1150 trapno = uc->uc_mcontext.gregs[REG_TRAPNO];
1151#if defined(TARGET_I386) && defined(USE_CODE_COPY)
1152 if (trapno == 0x00 || trapno == 0x05) {
1153 /* send division by zero or bound exception */
1154 cpu_send_trap(pc, trapno, uc);
1155 return 1;
1156 } else
1157#endif
1158 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1159 trapno == 0xe ?
1160 (uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0,
1161 &uc->uc_sigmask, puc);
2b413144
FB		 1162}
1163
bc51c5c9
FB		 1164#elif defined(__x86_64__)
1165
1166int cpu_signal_handler(int host_signum, struct siginfo *info,
1167 void *puc)
1168{
1169 struct ucontext *uc = puc;
1170 unsigned long pc;
1171
1172 pc = uc->uc_mcontext.gregs[REG_RIP];
1173 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1174 uc->uc_mcontext.gregs[REG_TRAPNO] == 0xe ?
1175 (uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0,
1176 &uc->uc_sigmask, puc);
1177}
1178
83fb7adf 1179#elif defined(__powerpc__)
2b413144 1180
83fb7adf
FB		 1181/***********************************************************************
1182 * signal context platform-specific definitions
1183 * From Wine
1184 */
1185#ifdef linux
1186/* All Registers access - only for local access */
1187# define REG_sig(reg_name, context) ((context)->uc_mcontext.regs->reg_name)
1188/* Gpr Registers access */
1189# define GPR_sig(reg_num, context) REG_sig(gpr[reg_num], context)
1190# define IAR_sig(context) REG_sig(nip, context) /* Program counter */
1191# define MSR_sig(context) REG_sig(msr, context) /* Machine State Register (Supervisor) */
1192# define CTR_sig(context) REG_sig(ctr, context) /* Count register */
1193# define XER_sig(context) REG_sig(xer, context) /* User's integer exception register */
1194# define LR_sig(context) REG_sig(link, context) /* Link register */
1195# define CR_sig(context) REG_sig(ccr, context) /* Condition register */
1196/* Float Registers access */
1197# define FLOAT_sig(reg_num, context) (((double*)((char*)((context)->uc_mcontext.regs+48*4)))[reg_num])
1198# define FPSCR_sig(context) (*(int*)((char*)((context)->uc_mcontext.regs+(48+32*2)*4)))
1199/* Exception Registers access */
1200# define DAR_sig(context) REG_sig(dar, context)
1201# define DSISR_sig(context) REG_sig(dsisr, context)
1202# define TRAP_sig(context) REG_sig(trap, context)
1203#endif /* linux */
1204
1205#ifdef __APPLE__
1206# include <sys/ucontext.h>
1207typedef struct ucontext SIGCONTEXT;
1208/* All Registers access - only for local access */
1209# define REG_sig(reg_name, context) ((context)->uc_mcontext->ss.reg_name)
1210# define FLOATREG_sig(reg_name, context) ((context)->uc_mcontext->fs.reg_name)
1211# define EXCEPREG_sig(reg_name, context) ((context)->uc_mcontext->es.reg_name)
1212# define VECREG_sig(reg_name, context) ((context)->uc_mcontext->vs.reg_name)
1213/* Gpr Registers access */
1214# define GPR_sig(reg_num, context) REG_sig(r##reg_num, context)
1215# define IAR_sig(context) REG_sig(srr0, context) /* Program counter */
1216# define MSR_sig(context) REG_sig(srr1, context) /* Machine State Register (Supervisor) */
1217# define CTR_sig(context) REG_sig(ctr, context)
1218# define XER_sig(context) REG_sig(xer, context) /* Link register */
1219# define LR_sig(context) REG_sig(lr, context) /* User's integer exception register */
1220# define CR_sig(context) REG_sig(cr, context) /* Condition register */
1221/* Float Registers access */
1222# define FLOAT_sig(reg_num, context) FLOATREG_sig(fpregs[reg_num], context)
1223# define FPSCR_sig(context) ((double)FLOATREG_sig(fpscr, context))
1224/* Exception Registers access */
1225# define DAR_sig(context) EXCEPREG_sig(dar, context) /* Fault registers for coredump */
1226# define DSISR_sig(context) EXCEPREG_sig(dsisr, context)
1227# define TRAP_sig(context) EXCEPREG_sig(exception, context) /* number of powerpc exception taken */
1228#endif /* __APPLE__ */
1229
d1d9f421 1230int cpu_signal_handler(int host_signum, struct siginfo *info,
e4533c7a 1231 void *puc)
2b413144 1232{
25eb4484 1233 struct ucontext *uc = puc;
25eb4484 1234 unsigned long pc;
25eb4484
FB		 1235 int is_write;
1236
83fb7adf 1237 pc = IAR_sig(uc);
25eb4484
FB		 1238 is_write = 0;
1239#if 0
1240 /* ppc 4xx case */
83fb7adf 1241 if (DSISR_sig(uc) & 0x00800000)
25eb4484
FB		 1242 is_write = 1;
1243#else
83fb7adf 1244 if (TRAP_sig(uc) != 0x400 && (DSISR_sig(uc) & 0x02000000))
25eb4484
FB		 1245 is_write = 1;
1246#endif
1247 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
bf3e8bf1 1248 is_write, &uc->uc_sigmask, puc);
2b413144
FB		 1249}
1250
2f87c607
FB		 1251#elif defined(__alpha__)
1252
e4533c7a 1253int cpu_signal_handler(int host_signum, struct siginfo *info,
2f87c607
FB		 1254 void *puc)
1255{
1256 struct ucontext *uc = puc;
1257 uint32_t *pc = uc->uc_mcontext.sc_pc;
1258 uint32_t insn = *pc;
1259 int is_write = 0;
1260
8c6939c0 1261 /* XXX: need kernel patch to get write flag faster */
2f87c607
FB		 1262 switch (insn >> 26) {
1263 case 0x0d: // stw
1264 case 0x0e: // stb
1265 case 0x0f: // stq_u
1266 case 0x24: // stf
1267 case 0x25: // stg
1268 case 0x26: // sts
1269 case 0x27: // stt
1270 case 0x2c: // stl
1271 case 0x2d: // stq
1272 case 0x2e: // stl_c
1273 case 0x2f: // stq_c
1274 is_write = 1;
1275 }
1276
1277 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
bf3e8bf1 1278 is_write, &uc->uc_sigmask, puc);
2f87c607 1279}
8c6939c0
FB		 1280#elif defined(__sparc__)
1281
e4533c7a
FB		 1282int cpu_signal_handler(int host_signum, struct siginfo *info,
1283 void *puc)
8c6939c0
FB		 1284{
1285 uint32_t *regs = (uint32_t *)(info + 1);
1286 void *sigmask = (regs + 20);
1287 unsigned long pc;
1288 int is_write;
1289 uint32_t insn;
1290
1291 /* XXX: is there a standard glibc define ? */
1292 pc = regs[1];
1293 /* XXX: need kernel patch to get write flag faster */
1294 is_write = 0;
1295 insn = *(uint32_t *)pc;
1296 if ((insn >> 30) == 3) {
1297 switch((insn >> 19) & 0x3f) {
1298 case 0x05: // stb
1299 case 0x06: // sth
1300 case 0x04: // st
1301 case 0x07: // std
1302 case 0x24: // stf
1303 case 0x27: // stdf
1304 case 0x25: // stfsr
1305 is_write = 1;
1306 break;
1307 }
1308 }
1309 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
bf3e8bf1 1310 is_write, sigmask, NULL);
8c6939c0
FB		 1311}
1312
1313#elif defined(__arm__)
1314
e4533c7a
FB		 1315int cpu_signal_handler(int host_signum, struct siginfo *info,
1316 void *puc)
8c6939c0
FB		 1317{
1318 struct ucontext *uc = puc;
1319 unsigned long pc;
1320 int is_write;
1321
1322 pc = uc->uc_mcontext.gregs[R15];
1323 /* XXX: compute is_write */
1324 is_write = 0;
1325 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1326 is_write,
1327 &uc->uc_sigmask);
1328}
1329
38e584a0
FB		 1330#elif defined(__mc68000)
1331
1332int cpu_signal_handler(int host_signum, struct siginfo *info,
1333 void *puc)
1334{
1335 struct ucontext *uc = puc;
1336 unsigned long pc;
1337 int is_write;
1338
1339 pc = uc->uc_mcontext.gregs[16];
1340 /* XXX: compute is_write */
1341 is_write = 0;
1342 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1343 is_write,
bf3e8bf1 1344 &uc->uc_sigmask, puc);
38e584a0
FB		 1345}
1346
b8076a74
FB		 1347#elif defined(__ia64)
1348
1349#ifndef __ISR_VALID
1350 /* This ought to be in <bits/siginfo.h>... */
1351# define __ISR_VALID 1
1352# define si_flags _sifields._sigfault._si_pad0
1353#endif
1354
1355int cpu_signal_handler(int host_signum, struct siginfo *info, void *puc)
1356{
1357 struct ucontext *uc = puc;
1358 unsigned long ip;
1359 int is_write = 0;
1360
1361 ip = uc->uc_mcontext.sc_ip;
1362 switch (host_signum) {
1363 case SIGILL:
1364 case SIGFPE:
1365 case SIGSEGV:
1366 case SIGBUS:
1367 case SIGTRAP:
1368 if (info->si_code && (info->si_flags & __ISR_VALID))
1369 /* ISR.W (write-access) is bit 33: */
1370 is_write = (info->si_isr >> 33) & 1;
1371 break;
1372
1373 default:
1374 break;
1375 }
1376 return handle_cpu_signal(ip, (unsigned long)info->si_addr,
1377 is_write,
1378 &uc->uc_sigmask, puc);
1379}
1380
90cb9493
FB		 1381#elif defined(__s390__)
1382
1383int cpu_signal_handler(int host_signum, struct siginfo *info,
1384 void *puc)
1385{
1386 struct ucontext *uc = puc;
1387 unsigned long pc;
1388 int is_write;
1389
1390 pc = uc->uc_mcontext.psw.addr;
1391 /* XXX: compute is_write */
1392 is_write = 0;
1393 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1394 is_write,
1395 &uc->uc_sigmask, puc);
1396}
1397
9de5e440 1398#else
2b413144 1399
3fb2ded1 1400#error host CPU specific signal handler needed
2b413144 1401
9de5e440 1402#endif
67b915a5
FB		 1403
1404#endif /* !defined(CONFIG_SOFTMMU) */
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