[qemu.git] / hw / pc.h

#ifndef HW_PC_H
#define HW_PC_H
/* PC-style peripherals (also used by other machines).  */

/* serial.c */

SerialState *serial_init(int base, qemu_irq irq, CharDriverState *chr);
SerialState *serial_mm_init (target_phys_addr_t base, int it_shift,
                             qemu_irq irq, CharDriverState *chr,
                             int ioregister);
uint32_t serial_mm_readb (void *opaque, target_phys_addr_t addr);
void serial_mm_writeb (void *opaque, target_phys_addr_t addr, uint32_t value);
uint32_t serial_mm_readw (void *opaque, target_phys_addr_t addr);
void serial_mm_writew (void *opaque, target_phys_addr_t addr, uint32_t value);
uint32_t serial_mm_readl (void *opaque, target_phys_addr_t addr);
void serial_mm_writel (void *opaque, target_phys_addr_t addr, uint32_t value);

/* parallel.c */

typedef struct ParallelState ParallelState;
ParallelState *parallel_init(int base, qemu_irq irq, CharDriverState *chr);
ParallelState *parallel_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq, CharDriverState *chr);

/* i8259.c */

typedef struct PicState2 PicState2;
extern PicState2 *isa_pic;
void pic_set_irq(int irq, int level);
void pic_set_irq_new(void *opaque, int irq, int level);
qemu_irq *i8259_init(qemu_irq parent_irq);
void pic_set_alt_irq_func(PicState2 *s, SetIRQFunc *alt_irq_func,
                          void *alt_irq_opaque);
int pic_read_irq(PicState2 *s);
void pic_update_irq(PicState2 *s);
uint32_t pic_intack_read(PicState2 *s);
void pic_info(void);
void irq_info(void);

/* APIC */
typedef struct IOAPICState IOAPICState;

int apic_init(CPUState *env);
int apic_accept_pic_intr(CPUState *env);
int apic_get_interrupt(CPUState *env);
IOAPICState *ioapic_init(void);
void ioapic_set_irq(void *opaque, int vector, int level);

/* i8254.c */

#define PIT_FREQ 1193182

typedef struct PITState PITState;

PITState *pit_init(int base, qemu_irq irq);
void pit_set_gate(PITState *pit, int channel, int val);
int pit_get_gate(PITState *pit, int channel);
int pit_get_initial_count(PITState *pit, int channel);
int pit_get_mode(PITState *pit, int channel);
int pit_get_out(PITState *pit, int channel, int64_t current_time);

/* vmport.c */
void vmport_init(CPUState *env);
void vmport_register(unsigned char command, IOPortReadFunc *func, void *opaque);

/* vmmouse.c */
void *vmmouse_init(void *m);

/* pckbd.c */

void i8042_init(qemu_irq kbd_irq, qemu_irq mouse_irq, uint32_t io_base);
void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq,
                   target_phys_addr_t base, int it_shift);

/* mc146818rtc.c */

typedef struct RTCState RTCState;

RTCState *rtc_init(int base, qemu_irq irq);
RTCState *rtc_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq);
void rtc_set_memory(RTCState *s, int addr, int val);
void rtc_set_date(RTCState *s, const struct tm *tm);

/* pc.c */
extern int fd_bootchk;

void ioport_set_a20(int enable);
int ioport_get_a20(void);

/* acpi.c */
extern int acpi_enabled;
i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base);
void piix4_smbus_register_device(SMBusDevice *dev, uint8_t addr);
void acpi_bios_init(void);

/* pcspk.c */
void pcspk_init(PITState *);
int pcspk_audio_init(AudioState *, qemu_irq *pic);

/* piix_pci.c */
PCIBus *i440fx_init(PCIDevice **pi440fx_state, qemu_irq *pic);
void i440fx_set_smm(PCIDevice *d, int val);
int piix3_init(PCIBus *bus, int devfn);
void i440fx_init_memory_mappings(PCIDevice *d);

int piix4_init(PCIBus *bus, int devfn);

/* vga.c */

#ifndef TARGET_SPARC
#define VGA_RAM_SIZE (8192 * 1024)
#else
#define VGA_RAM_SIZE (9 * 1024 * 1024)
#endif

int isa_vga_init(DisplayState *ds, uint8_t *vga_ram_base,
                 unsigned long vga_ram_offset, int vga_ram_size);
int pci_vga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
                 unsigned long vga_ram_offset, int vga_ram_size,
                 unsigned long vga_bios_offset, int vga_bios_size);
int isa_vga_mm_init(DisplayState *ds, uint8_t *vga_ram_base,
                    unsigned long vga_ram_offset, int vga_ram_size,
                    target_phys_addr_t vram_base, target_phys_addr_t ctrl_base,
                    int it_shift);

/* cirrus_vga.c */
void pci_cirrus_vga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
                         unsigned long vga_ram_offset, int vga_ram_size);
void isa_cirrus_vga_init(DisplayState *ds, uint8_t *vga_ram_base,
                         unsigned long vga_ram_offset, int vga_ram_size);

/* ide.c */
void isa_ide_init(int iobase, int iobase2, qemu_irq irq,
                  BlockDriverState *hd0, BlockDriverState *hd1);
void pci_cmd646_ide_init(PCIBus *bus, BlockDriverState **hd_table,
                         int secondary_ide_enabled);
void pci_piix3_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn,
                        qemu_irq *pic);
void pci_piix4_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn,
                        qemu_irq *pic);

/* ne2000.c */

void isa_ne2000_init(int base, qemu_irq irq, NICInfo *nd);

#endif
Commit	Line	Data
87ecb68b PB	1	#ifndef HW_PC_H
	2	#define HW_PC_H
	3	/* PC-style peripherals (also used by other machines). */
	4
	5	/* serial.c */
	6
	7	SerialState serial_init(int base, qemu_irq irq, CharDriverState chr);
	8	SerialState *serial_mm_init (target_phys_addr_t base, int it_shift,
	9	qemu_irq irq, CharDriverState *chr,
	10	int ioregister);
	11	uint32_t serial_mm_readb (void *opaque, target_phys_addr_t addr);
	12	void serial_mm_writeb (void *opaque, target_phys_addr_t addr, uint32_t value);
	13	uint32_t serial_mm_readw (void *opaque, target_phys_addr_t addr);
	14	void serial_mm_writew (void *opaque, target_phys_addr_t addr, uint32_t value);
	15	uint32_t serial_mm_readl (void *opaque, target_phys_addr_t addr);
	16	void serial_mm_writel (void *opaque, target_phys_addr_t addr, uint32_t value);
	17
	18	/* parallel.c */
	19
	20	typedef struct ParallelState ParallelState;
	21	ParallelState parallel_init(int base, qemu_irq irq, CharDriverState chr);
	22	ParallelState parallel_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq, CharDriverState chr);
	23
	24	/* i8259.c */
	25
	26	typedef struct PicState2 PicState2;
	27	extern PicState2 *isa_pic;
	28	void pic_set_irq(int irq, int level);
	29	void pic_set_irq_new(void *opaque, int irq, int level);
	30	qemu_irq *i8259_init(qemu_irq parent_irq);
	31	void pic_set_alt_irq_func(PicState2 s, SetIRQFunc alt_irq_func,
	32	void *alt_irq_opaque);
	33	int pic_read_irq(PicState2 *s);
	34	void pic_update_irq(PicState2 *s);
	35	uint32_t pic_intack_read(PicState2 *s);
	36	void pic_info(void);
	37	void irq_info(void);
	38
	39	/* APIC */
	40	typedef struct IOAPICState IOAPICState;
	41
	42	int apic_init(CPUState *env);
	43	int apic_accept_pic_intr(CPUState *env);
	44	int apic_get_interrupt(CPUState *env);
	45	IOAPICState *ioapic_init(void);
	46	void ioapic_set_irq(void *opaque, int vector, int level);
	47
	48	/* i8254.c */
	49
	50	#define PIT_FREQ 1193182
	51
	52	typedef struct PITState PITState;
	53
	54	PITState *pit_init(int base, qemu_irq irq);
	55	void pit_set_gate(PITState *pit, int channel, int val);
	56	int pit_get_gate(PITState *pit, int channel);
	57	int pit_get_initial_count(PITState *pit, int channel);
	58	int pit_get_mode(PITState *pit, int channel);
	59	int pit_get_out(PITState *pit, int channel, int64_t current_time);
	60
	61	/* vmport.c */
	62	void vmport_init(CPUState *env);
	63	void vmport_register(unsigned char command, IOPortReadFunc func, void opaque);
	64
65	/* vmmouse.c */
66	void vmmouse_init(void m);
67
68	/* pckbd.c */
69
70	void i8042_init(qemu_irq kbd_irq, qemu_irq mouse_irq, uint32_t io_base);
71	void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq,
72	target_phys_addr_t base, int it_shift);
73
74	/* mc146818rtc.c */
75
76	typedef struct RTCState RTCState;
77
78	RTCState *rtc_init(int base, qemu_irq irq);
79	RTCState *rtc_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq);
80	void rtc_set_memory(RTCState *s, int addr, int val);
81	void rtc_set_date(RTCState s, const struct tm tm);
82
83	/* pc.c */
84	extern int fd_bootchk;
85
86	void ioport_set_a20(int enable);
87	int ioport_get_a20(void);
88
89	/* acpi.c */
90	extern int acpi_enabled;
91	i2c_bus piix4_pm_init(PCIBus bus, int devfn, uint32_t smb_io_base);
92	void piix4_smbus_register_device(SMBusDevice *dev, uint8_t addr);
93	void acpi_bios_init(void);
94
95	/* pcspk.c */
96	void pcspk_init(PITState *);
97	int pcspk_audio_init(AudioState , qemu_irq pic);
98
99	/* piix_pci.c */
100	PCIBus i440fx_init(PCIDevice pi440fx_state, qemu_irq pic);
101	void i440fx_set_smm(PCIDevice *d, int val);
102	int piix3_init(PCIBus *bus, int devfn);
103	void i440fx_init_memory_mappings(PCIDevice *d);
104
105	int piix4_init(PCIBus *bus, int devfn);
106
107	/* vga.c */
108
109	#ifndef TARGET_SPARC
110	#define VGA_RAM_SIZE (8192 * 1024)
111	#else
112	#define VGA_RAM_SIZE (9 * 1024 * 1024)
113	#endif
114
115	int isa_vga_init(DisplayState ds, uint8_t vga_ram_base,
116	unsigned long vga_ram_offset, int vga_ram_size);
117	int pci_vga_init(PCIBus bus, DisplayState ds, uint8_t *vga_ram_base,
118	unsigned long vga_ram_offset, int vga_ram_size,
119	unsigned long vga_bios_offset, int vga_bios_size);
120	int isa_vga_mm_init(DisplayState ds, uint8_t vga_ram_base,
121	unsigned long vga_ram_offset, int vga_ram_size,
122	target_phys_addr_t vram_base, target_phys_addr_t ctrl_base,
123	int it_shift);
124
125	/* cirrus_vga.c */
126	void pci_cirrus_vga_init(PCIBus bus, DisplayState ds, uint8_t *vga_ram_base,
127	unsigned long vga_ram_offset, int vga_ram_size);
128	void isa_cirrus_vga_init(DisplayState ds, uint8_t vga_ram_base,
129	unsigned long vga_ram_offset, int vga_ram_size);
130
131	/* ide.c */
132	void isa_ide_init(int iobase, int iobase2, qemu_irq irq,
133	BlockDriverState hd0, BlockDriverState hd1);
134	void pci_cmd646_ide_init(PCIBus bus, BlockDriverState *hd_table,
135	int secondary_ide_enabled);
136	void pci_piix3_ide_init(PCIBus bus, BlockDriverState *hd_table, int devfn,
137	qemu_irq *pic);
138	void pci_piix4_ide_init(PCIBus bus, BlockDriverState *hd_table, int devfn,
139	qemu_irq *pic);
140
141	/* ne2000.c */
142
143	void isa_ne2000_init(int base, qemu_irq irq, NICInfo *nd);
144
145	#endif