[qemu.git] / hw / timer / pxa2xx_timer.c

/*
 * Intel XScale PXA255/270 OS Timers.
 *
 * Copyright (c) 2006 Openedhand Ltd.
 * Copyright (c) 2006 Thorsten Zitterell
 *
 * This code is licensed under the GPL.
 */

#include "qemu/osdep.h"
#include "hw/irq.h"
#include "hw/qdev-properties.h"
#include "qemu/timer.h"
#include "sysemu/runstate.h"
#include "hw/arm/pxa.h"
#include "hw/sysbus.h"
#include "migration/vmstate.h"
#include "qemu/log.h"
#include "qemu/module.h"

#define OSMR0	0x00
#define OSMR1	0x04
#define OSMR2	0x08
#define OSMR3	0x0c
#define OSMR4	0x80
#define OSMR5	0x84
#define OSMR6	0x88
#define OSMR7	0x8c
#define OSMR8	0x90
#define OSMR9	0x94
#define OSMR10	0x98
#define OSMR11	0x9c
#define OSCR	0x10	/* OS Timer Count */
#define OSCR4	0x40
#define OSCR5	0x44
#define OSCR6	0x48
#define OSCR7	0x4c
#define OSCR8	0x50
#define OSCR9	0x54
#define OSCR10	0x58
#define OSCR11	0x5c
#define OSSR	0x14	/* Timer status register */
#define OWER	0x18
#define OIER	0x1c	/* Interrupt enable register  3-0 to E3-E0 */
#define OMCR4	0xc0	/* OS Match Control registers */
#define OMCR5	0xc4
#define OMCR6	0xc8
#define OMCR7	0xcc
#define OMCR8	0xd0
#define OMCR9	0xd4
#define OMCR10	0xd8
#define OMCR11	0xdc
#define OSNR	0x20

#define PXA25X_FREQ	3686400	/* 3.6864 MHz */
#define PXA27X_FREQ	3250000	/* 3.25 MHz */

static int pxa2xx_timer4_freq[8] = {
    [0] = 0,
    [1] = 32768,
    [2] = 1000,
    [3] = 1,
    [4] = 1000000,
    /* [5] is the "Externally supplied clock".  Assign if necessary.  */
    [5 ... 7] = 0,
};

#define TYPE_PXA2XX_TIMER "pxa2xx-timer"
#define PXA2XX_TIMER(obj) \
    OBJECT_CHECK(PXA2xxTimerInfo, (obj), TYPE_PXA2XX_TIMER)

typedef struct PXA2xxTimerInfo PXA2xxTimerInfo;

typedef struct {
    uint32_t value;
    qemu_irq irq;
    QEMUTimer *qtimer;
    int num;
    PXA2xxTimerInfo *info;
} PXA2xxTimer0;

typedef struct {
    PXA2xxTimer0 tm;
    int32_t oldclock;
    int32_t clock;
    uint64_t lastload;
    uint32_t freq;
    uint32_t control;
} PXA2xxTimer4;

struct PXA2xxTimerInfo {
    SysBusDevice parent_obj;

    MemoryRegion iomem;
    uint32_t flags;

    int32_t clock;
    int32_t oldclock;
    uint64_t lastload;
    uint32_t freq;
    PXA2xxTimer0 timer[4];
    uint32_t events;
    uint32_t irq_enabled;
    uint32_t reset3;
    uint32_t snapshot;

    qemu_irq irq4;
    PXA2xxTimer4 tm4[8];
};

#define PXA2XX_TIMER_HAVE_TM4	0

static inline int pxa2xx_timer_has_tm4(PXA2xxTimerInfo *s)
{
    return s->flags & (1 << PXA2XX_TIMER_HAVE_TM4);
}

static void pxa2xx_timer_update(void *opaque, uint64_t now_qemu)
{
    PXA2xxTimerInfo *s = (PXA2xxTimerInfo *) opaque;
    int i;
    uint32_t now_vm;
    uint64_t new_qemu;

    now_vm = s->clock +
            muldiv64(now_qemu - s->lastload, s->freq, NANOSECONDS_PER_SECOND);

    for (i = 0; i < 4; i ++) {
        new_qemu = now_qemu + muldiv64((uint32_t) (s->timer[i].value - now_vm),
                        NANOSECONDS_PER_SECOND, s->freq);
        timer_mod(s->timer[i].qtimer, new_qemu);
    }
}

static void pxa2xx_timer_update4(void *opaque, uint64_t now_qemu, int n)
{
    PXA2xxTimerInfo *s = (PXA2xxTimerInfo *) opaque;
    uint32_t now_vm;
    uint64_t new_qemu;
    static const int counters[8] = { 0, 0, 0, 0, 4, 4, 6, 6 };
    int counter;

    if (s->tm4[n].control & (1 << 7))
        counter = n;
    else
        counter = counters[n];

    if (!s->tm4[counter].freq) {
        timer_del(s->tm4[n].tm.qtimer);
        return;
    }

    now_vm = s->tm4[counter].clock + muldiv64(now_qemu -
                    s->tm4[counter].lastload,
                    s->tm4[counter].freq, NANOSECONDS_PER_SECOND);

    new_qemu = now_qemu + muldiv64((uint32_t) (s->tm4[n].tm.value - now_vm),
                    NANOSECONDS_PER_SECOND, s->tm4[counter].freq);
    timer_mod(s->tm4[n].tm.qtimer, new_qemu);
}

static uint64_t pxa2xx_timer_read(void *opaque, hwaddr offset,
                                  unsigned size)
{
    PXA2xxTimerInfo *s = (PXA2xxTimerInfo *) opaque;
    int tm = 0;

    switch (offset) {
    case OSMR3:  tm ++;
        /* fall through */
    case OSMR2:  tm ++;
        /* fall through */
    case OSMR1:  tm ++;
        /* fall through */
    case OSMR0:
        return s->timer[tm].value;
    case OSMR11: tm ++;
        /* fall through */
    case OSMR10: tm ++;
        /* fall through */
    case OSMR9:  tm ++;
        /* fall through */
    case OSMR8:  tm ++;
        /* fall through */
    case OSMR7:  tm ++;
        /* fall through */
    case OSMR6:  tm ++;
        /* fall through */
    case OSMR5:  tm ++;
        /* fall through */
    case OSMR4:
        if (!pxa2xx_timer_has_tm4(s))
            goto badreg;
        return s->tm4[tm].tm.value;
    case OSCR:
        return s->clock + muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) -
                        s->lastload, s->freq, NANOSECONDS_PER_SECOND);
    case OSCR11: tm ++;
        /* fall through */
    case OSCR10: tm ++;
        /* fall through */
    case OSCR9:  tm ++;
        /* fall through */
    case OSCR8:  tm ++;
        /* fall through */
    case OSCR7:  tm ++;
        /* fall through */
    case OSCR6:  tm ++;
        /* fall through */
    case OSCR5:  tm ++;
        /* fall through */
    case OSCR4:
        if (!pxa2xx_timer_has_tm4(s))
            goto badreg;

        if ((tm == 9 - 4 || tm == 11 - 4) && (s->tm4[tm].control & (1 << 9))) {
            if (s->tm4[tm - 1].freq)
                s->snapshot = s->tm4[tm - 1].clock + muldiv64(
                                qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) -
                                s->tm4[tm - 1].lastload,
                                s->tm4[tm - 1].freq, NANOSECONDS_PER_SECOND);
            else
                s->snapshot = s->tm4[tm - 1].clock;
        }

        if (!s->tm4[tm].freq)
            return s->tm4[tm].clock;
        return s->tm4[tm].clock +
            muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) -
                     s->tm4[tm].lastload, s->tm4[tm].freq,
                     NANOSECONDS_PER_SECOND);
    case OIER:
        return s->irq_enabled;
    case OSSR:	/* Status register */
        return s->events;
    case OWER:
        return s->reset3;
    case OMCR11: tm ++;
        /* fall through */
    case OMCR10: tm ++;
        /* fall through */
    case OMCR9:  tm ++;
        /* fall through */
    case OMCR8:  tm ++;
        /* fall through */
    case OMCR7:  tm ++;
        /* fall through */
    case OMCR6:  tm ++;
        /* fall through */
    case OMCR5:  tm ++;
        /* fall through */
    case OMCR4:
        if (!pxa2xx_timer_has_tm4(s))
            goto badreg;
        return s->tm4[tm].control;
    case OSNR:
        return s->snapshot;
    default:
        qemu_log_mask(LOG_UNIMP,
                      "%s: unknown register 0x%02" HWADDR_PRIx "\n",
                      __func__, offset);
        break;
    badreg:
        qemu_log_mask(LOG_GUEST_ERROR,
                      "%s: incorrect register 0x%02" HWADDR_PRIx "\n",
                      __func__, offset);
    }

    return 0;
}

static void pxa2xx_timer_write(void *opaque, hwaddr offset,
                               uint64_t value, unsigned size)
{
    int i, tm = 0;
    PXA2xxTimerInfo *s = (PXA2xxTimerInfo *) opaque;

    switch (offset) {
    case OSMR3:  tm ++;
        /* fall through */
    case OSMR2:  tm ++;
        /* fall through */
    case OSMR1:  tm ++;
        /* fall through */
    case OSMR0:
        s->timer[tm].value = value;
        pxa2xx_timer_update(s, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
        break;
    case OSMR11: tm ++;
        /* fall through */
    case OSMR10: tm ++;
        /* fall through */
    case OSMR9:  tm ++;
        /* fall through */
    case OSMR8:  tm ++;
        /* fall through */
    case OSMR7:  tm ++;
        /* fall through */
    case OSMR6:  tm ++;
        /* fall through */
    case OSMR5:  tm ++;
        /* fall through */
    case OSMR4:
        if (!pxa2xx_timer_has_tm4(s))
            goto badreg;
        s->tm4[tm].tm.value = value;
        pxa2xx_timer_update4(s, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tm);
        break;
    case OSCR:
        s->oldclock = s->clock;
        s->lastload = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
        s->clock = value;
        pxa2xx_timer_update(s, s->lastload);
        break;
    case OSCR11: tm ++;
        /* fall through */
    case OSCR10: tm ++;
        /* fall through */
    case OSCR9:  tm ++;
        /* fall through */
    case OSCR8:  tm ++;
        /* fall through */
    case OSCR7:  tm ++;
        /* fall through */
    case OSCR6:  tm ++;
        /* fall through */
    case OSCR5:  tm ++;
        /* fall through */
    case OSCR4:
        if (!pxa2xx_timer_has_tm4(s))
            goto badreg;
        s->tm4[tm].oldclock = s->tm4[tm].clock;
        s->tm4[tm].lastload = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
        s->tm4[tm].clock = value;
        pxa2xx_timer_update4(s, s->tm4[tm].lastload, tm);
        break;
    case OIER:
        s->irq_enabled = value & 0xfff;
        break;
    case OSSR:	/* Status register */
        value &= s->events;
        s->events &= ~value;
        for (i = 0; i < 4; i ++, value >>= 1)
            if (value & 1)
                qemu_irq_lower(s->timer[i].irq);
        if (pxa2xx_timer_has_tm4(s) && !(s->events & 0xff0) && value)
            qemu_irq_lower(s->irq4);
        break;
    case OWER:	/* XXX: Reset on OSMR3 match? */
        s->reset3 = value;
        break;
    case OMCR7:  tm ++;
        /* fall through */
    case OMCR6:  tm ++;
        /* fall through */
    case OMCR5:  tm ++;
        /* fall through */
    case OMCR4:
        if (!pxa2xx_timer_has_tm4(s))
            goto badreg;
        s->tm4[tm].control = value & 0x0ff;
        /* XXX Stop if running (shouldn't happen) */
        if ((value & (1 << 7)) || tm == 0)
            s->tm4[tm].freq = pxa2xx_timer4_freq[value & 7];
        else {
            s->tm4[tm].freq = 0;
            pxa2xx_timer_update4(s, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tm);
        }
        break;
    case OMCR11: tm ++;
        /* fall through */
    case OMCR10: tm ++;
        /* fall through */
    case OMCR9:  tm ++;
        /* fall through */
    case OMCR8:  tm += 4;
        if (!pxa2xx_timer_has_tm4(s))
            goto badreg;
        s->tm4[tm].control = value & 0x3ff;
        /* XXX Stop if running (shouldn't happen) */
        if ((value & (1 << 7)) || !(tm & 1))
            s->tm4[tm].freq =
                    pxa2xx_timer4_freq[(value & (1 << 8)) ?  0 : (value & 7)];
        else {
            s->tm4[tm].freq = 0;
            pxa2xx_timer_update4(s, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tm);
        }
        break;
    default:
        qemu_log_mask(LOG_UNIMP,
                      "%s: unknown register 0x%02" HWADDR_PRIx " "
                      "(value 0x%08" PRIx64 ")\n",  __func__, offset, value);
        break;
    badreg:
        qemu_log_mask(LOG_GUEST_ERROR,
                      "%s: incorrect register 0x%02" HWADDR_PRIx " "
                      "(value 0x%08" PRIx64 ")\n", __func__, offset, value);
    }
}

static const MemoryRegionOps pxa2xx_timer_ops = {
    .read = pxa2xx_timer_read,
    .write = pxa2xx_timer_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
};

static void pxa2xx_timer_tick(void *opaque)
{
    PXA2xxTimer0 *t = (PXA2xxTimer0 *) opaque;
    PXA2xxTimerInfo *i = t->info;

    if (i->irq_enabled & (1 << t->num)) {
        i->events |= 1 << t->num;
        qemu_irq_raise(t->irq);
    }

    if (t->num == 3)
        if (i->reset3 & 1) {
            i->reset3 = 0;
            qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
        }
}

static void pxa2xx_timer_tick4(void *opaque)
{
    PXA2xxTimer4 *t = (PXA2xxTimer4 *) opaque;
    PXA2xxTimerInfo *i = (PXA2xxTimerInfo *) t->tm.info;

    pxa2xx_timer_tick(&t->tm);
    if (t->control & (1 << 3))
        t->clock = 0;
    if (t->control & (1 << 6))
        pxa2xx_timer_update4(i, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), t->tm.num - 4);
    if (i->events & 0xff0)
        qemu_irq_raise(i->irq4);
}

static int pxa25x_timer_post_load(void *opaque, int version_id)
{
    PXA2xxTimerInfo *s = (PXA2xxTimerInfo *) opaque;
    int64_t now;
    int i;

    now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
    pxa2xx_timer_update(s, now);

    if (pxa2xx_timer_has_tm4(s))
        for (i = 0; i < 8; i ++)
            pxa2xx_timer_update4(s, now, i);

    return 0;
}

static void pxa2xx_timer_init(Object *obj)
{
    PXA2xxTimerInfo *s = PXA2XX_TIMER(obj);
    SysBusDevice *dev = SYS_BUS_DEVICE(obj);

    s->irq_enabled = 0;
    s->oldclock = 0;
    s->clock = 0;
    s->lastload = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
    s->reset3 = 0;

    memory_region_init_io(&s->iomem, obj, &pxa2xx_timer_ops, s,
                          "pxa2xx-timer", 0x00001000);
    sysbus_init_mmio(dev, &s->iomem);
}

static void pxa2xx_timer_realize(DeviceState *dev, Error **errp)
{
    PXA2xxTimerInfo *s = PXA2XX_TIMER(dev);
    SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
    int i;

    for (i = 0; i < 4; i ++) {
        s->timer[i].value = 0;
        sysbus_init_irq(sbd, &s->timer[i].irq);
        s->timer[i].info = s;
        s->timer[i].num = i;
        s->timer[i].qtimer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
                                          pxa2xx_timer_tick, &s->timer[i]);
    }

    if (s->flags & (1 << PXA2XX_TIMER_HAVE_TM4)) {
        sysbus_init_irq(sbd, &s->irq4);

        for (i = 0; i < 8; i ++) {
            s->tm4[i].tm.value = 0;
            s->tm4[i].tm.info = s;
            s->tm4[i].tm.num = i + 4;
            s->tm4[i].freq = 0;
            s->tm4[i].control = 0x0;
            s->tm4[i].tm.qtimer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
                                               pxa2xx_timer_tick4, &s->tm4[i]);
        }
    }
}

static const VMStateDescription vmstate_pxa2xx_timer0_regs = {
    .name = "pxa2xx_timer0",
    .version_id = 2,
    .minimum_version_id = 2,
    .fields = (VMStateField[]) {
        VMSTATE_UINT32(value, PXA2xxTimer0),
        VMSTATE_END_OF_LIST(),
    },
};

static const VMStateDescription vmstate_pxa2xx_timer4_regs = {
    .name = "pxa2xx_timer4",
    .version_id = 1,
    .minimum_version_id = 1,
    .fields = (VMStateField[]) {
        VMSTATE_STRUCT(tm, PXA2xxTimer4, 1,
                        vmstate_pxa2xx_timer0_regs, PXA2xxTimer0),
        VMSTATE_INT32(oldclock, PXA2xxTimer4),
        VMSTATE_INT32(clock, PXA2xxTimer4),
        VMSTATE_UINT64(lastload, PXA2xxTimer4),
        VMSTATE_UINT32(freq, PXA2xxTimer4),
        VMSTATE_UINT32(control, PXA2xxTimer4),
        VMSTATE_END_OF_LIST(),
    },
};

static bool pxa2xx_timer_has_tm4_test(void *opaque, int version_id)
{
    return pxa2xx_timer_has_tm4(opaque);
}

static const VMStateDescription vmstate_pxa2xx_timer_regs = {
    .name = "pxa2xx_timer",
    .version_id = 1,
    .minimum_version_id = 1,
    .post_load = pxa25x_timer_post_load,
    .fields = (VMStateField[]) {
        VMSTATE_INT32(clock, PXA2xxTimerInfo),
        VMSTATE_INT32(oldclock, PXA2xxTimerInfo),
        VMSTATE_UINT64(lastload, PXA2xxTimerInfo),
        VMSTATE_STRUCT_ARRAY(timer, PXA2xxTimerInfo, 4, 1,
                        vmstate_pxa2xx_timer0_regs, PXA2xxTimer0),
        VMSTATE_UINT32(events, PXA2xxTimerInfo),
        VMSTATE_UINT32(irq_enabled, PXA2xxTimerInfo),
        VMSTATE_UINT32(reset3, PXA2xxTimerInfo),
        VMSTATE_UINT32(snapshot, PXA2xxTimerInfo),
        VMSTATE_STRUCT_ARRAY_TEST(tm4, PXA2xxTimerInfo, 8,
                        pxa2xx_timer_has_tm4_test, 0,
                        vmstate_pxa2xx_timer4_regs, PXA2xxTimer4),
        VMSTATE_END_OF_LIST(),
    }
};

static Property pxa25x_timer_dev_properties[] = {
    DEFINE_PROP_UINT32("freq", PXA2xxTimerInfo, freq, PXA25X_FREQ),
    DEFINE_PROP_BIT("tm4", PXA2xxTimerInfo, flags,
                    PXA2XX_TIMER_HAVE_TM4, false),
    DEFINE_PROP_END_OF_LIST(),
};

static void pxa25x_timer_dev_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);

    dc->desc = "PXA25x timer";
    dc->props = pxa25x_timer_dev_properties;
}

static const TypeInfo pxa25x_timer_dev_info = {
    .name          = "pxa25x-timer",
    .parent        = TYPE_PXA2XX_TIMER,
    .instance_size = sizeof(PXA2xxTimerInfo),
    .class_init    = pxa25x_timer_dev_class_init,
};

static Property pxa27x_timer_dev_properties[] = {
    DEFINE_PROP_UINT32("freq", PXA2xxTimerInfo, freq, PXA27X_FREQ),
    DEFINE_PROP_BIT("tm4", PXA2xxTimerInfo, flags,
                    PXA2XX_TIMER_HAVE_TM4, true),
    DEFINE_PROP_END_OF_LIST(),
};

static void pxa27x_timer_dev_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);

    dc->desc = "PXA27x timer";
    dc->props = pxa27x_timer_dev_properties;
}

static const TypeInfo pxa27x_timer_dev_info = {
    .name          = "pxa27x-timer",
    .parent        = TYPE_PXA2XX_TIMER,
    .instance_size = sizeof(PXA2xxTimerInfo),
    .class_init    = pxa27x_timer_dev_class_init,
};

static void pxa2xx_timer_class_init(ObjectClass *oc, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(oc);

    dc->realize  = pxa2xx_timer_realize;
    dc->vmsd = &vmstate_pxa2xx_timer_regs;
}

static const TypeInfo pxa2xx_timer_type_info = {
    .name          = TYPE_PXA2XX_TIMER,
    .parent        = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(PXA2xxTimerInfo),
    .instance_init = pxa2xx_timer_init,
    .abstract      = true,
    .class_init    = pxa2xx_timer_class_init,
};

static void pxa2xx_timer_register_types(void)
{
    type_register_static(&pxa2xx_timer_type_info);
    type_register_static(&pxa25x_timer_dev_info);
    type_register_static(&pxa27x_timer_dev_info);
}

type_init(pxa2xx_timer_register_types)
Commit	Line	Data
a171fe39 AZ	1	/*
	2	* Intel XScale PXA255/270 OS Timers.
	3	*
	4	* Copyright (c) 2006 Openedhand Ltd.
	5	* Copyright (c) 2006 Thorsten Zitterell
	6	*
8e31bf38	7	* This code is licensed under the GPL.
a171fe39 AZ	8	*/
a171fe39 AZ	9
8ef94f0b	10	#include "qemu/osdep.h"
64552b6b	11	#include "hw/irq.h"
a27bd6c7	12	#include "hw/qdev-properties.h"
1de7afc9	13	#include "qemu/timer.h"
54d31236	14	#include "sysemu/runstate.h"
0d09e41a	15	#include "hw/arm/pxa.h"
83c9f4ca	16	#include "hw/sysbus.h"
d6454270	17	#include "migration/vmstate.h"
2ba63e4a	18	#include "qemu/log.h"
0b8fa32f	19	#include "qemu/module.h"
a171fe39 AZ	20
	21	#define OSMR0 0x00
	22	#define OSMR1 0x04
	23	#define OSMR2 0x08
	24	#define OSMR3 0x0c
	25	#define OSMR4 0x80
	26	#define OSMR5 0x84
	27	#define OSMR6 0x88
	28	#define OSMR7 0x8c
	29	#define OSMR8 0x90
	30	#define OSMR9 0x94
	31	#define OSMR10 0x98
	32	#define OSMR11 0x9c
	33	#define OSCR 0x10 /* OS Timer Count */
	34	#define OSCR4 0x40
	35	#define OSCR5 0x44
	36	#define OSCR6 0x48
	37	#define OSCR7 0x4c
	38	#define OSCR8 0x50
	39	#define OSCR9 0x54
	40	#define OSCR10 0x58
	41	#define OSCR11 0x5c
	42	#define OSSR 0x14 /* Timer status register */
	43	#define OWER 0x18
	44	#define OIER 0x1c /* Interrupt enable register 3-0 to E3-E0 */
	45	#define OMCR4 0xc0 /* OS Match Control registers */
	46	#define OMCR5 0xc4
	47	#define OMCR6 0xc8
	48	#define OMCR7 0xcc
	49	#define OMCR8 0xd0
	50	#define OMCR9 0xd4
	51	#define OMCR10 0xd8
	52	#define OMCR11 0xdc
	53	#define OSNR 0x20
	54
	55	#define PXA25X_FREQ 3686400 /* 3.6864 MHz */
	56	#define PXA27X_FREQ 3250000 /* 3.25 MHz */
	57
	58	static int pxa2xx_timer4_freq[8] = {
	59	[0] = 0,
	60	[1] = 32768,
	61	[2] = 1000,
	62	[3] = 1,
	63	[4] = 1000000,
	64	/* [5] is the "Externally supplied clock". Assign if necessary. */
	65	[5 ... 7] = 0,
	66	};
	67
feea4361 AF	68	#define TYPE_PXA2XX_TIMER "pxa2xx-timer"
	69	#define PXA2XX_TIMER(obj) \
	70	OBJECT_CHECK(PXA2xxTimerInfo, (obj), TYPE_PXA2XX_TIMER)
	71
797e9542 DES	72	typedef struct PXA2xxTimerInfo PXA2xxTimerInfo;
797e9542 DES	73
bc24a225	74	typedef struct {
a171fe39	75	uint32_t value;
5251d196	76	qemu_irq irq;
a171fe39 AZ	77	QEMUTimer *qtimer;
a171fe39 AZ	78	int num;
797e9542	79	PXA2xxTimerInfo *info;
bc24a225	80	} PXA2xxTimer0;
a171fe39	81
bc24a225 PB	82	typedef struct {
bc24a225 PB	83	PXA2xxTimer0 tm;
a171fe39 AZ	84	int32_t oldclock;
	85	int32_t clock;
	86	uint64_t lastload;
	87	uint32_t freq;
	88	uint32_t control;
bc24a225	89	} PXA2xxTimer4;
a171fe39	90
797e9542	91	struct PXA2xxTimerInfo {
feea4361 AF	92	SysBusDevice parent_obj;
feea4361 AF	93
b755bde3	94	MemoryRegion iomem;
797e9542 DES	95	uint32_t flags;
797e9542 DES	96
a171fe39 AZ	97	int32_t clock;
	98	int32_t oldclock;
	99	uint64_t lastload;
	100	uint32_t freq;
bc24a225	101	PXA2xxTimer0 timer[4];
a171fe39 AZ	102	uint32_t events;
	103	uint32_t irq_enabled;
	104	uint32_t reset3;
a171fe39	105	uint32_t snapshot;
797e9542	106
4ff927cc	107	qemu_irq irq4;
797e9542	108	PXA2xxTimer4 tm4[8];
797e9542 DES	109	};
	110
	111	#define PXA2XX_TIMER_HAVE_TM4 0
	112
	113	static inline int pxa2xx_timer_has_tm4(PXA2xxTimerInfo *s)
	114	{
	115	return s->flags & (1 << PXA2XX_TIMER_HAVE_TM4);
	116	}
a171fe39 AZ	117
	118	static void pxa2xx_timer_update(void *opaque, uint64_t now_qemu)
	119	{
d353eb43	120	PXA2xxTimerInfo s = (PXA2xxTimerInfo ) opaque;
a171fe39 AZ	121	int i;
	122	uint32_t now_vm;
	123	uint64_t new_qemu;
	124
	125	now_vm = s->clock +
73bcb24d	126	muldiv64(now_qemu - s->lastload, s->freq, NANOSECONDS_PER_SECOND);
a171fe39 AZ	127
	128	for (i = 0; i < 4; i ++) {
	129	new_qemu = now_qemu + muldiv64((uint32_t) (s->timer[i].value - now_vm),
73bcb24d	130	NANOSECONDS_PER_SECOND, s->freq);
bc72ad67	131	timer_mod(s->timer[i].qtimer, new_qemu);
a171fe39 AZ	132	}
	133	}
	134
	135	static void pxa2xx_timer_update4(void *opaque, uint64_t now_qemu, int n)
	136	{
d353eb43	137	PXA2xxTimerInfo s = (PXA2xxTimerInfo ) opaque;
a171fe39 AZ	138	uint32_t now_vm;
	139	uint64_t new_qemu;
	140	static const int counters[8] = { 0, 0, 0, 0, 4, 4, 6, 6 };
	141	int counter;
	142
	143	if (s->tm4[n].control & (1 << 7))
	144	counter = n;
	145	else
	146	counter = counters[n];
	147
	148	if (!s->tm4[counter].freq) {
bc72ad67	149	timer_del(s->tm4[n].tm.qtimer);
a171fe39 AZ	150	return;
	151	}
	152
	153	now_vm = s->tm4[counter].clock + muldiv64(now_qemu -
	154	s->tm4[counter].lastload,
73bcb24d	155	s->tm4[counter].freq, NANOSECONDS_PER_SECOND);
a171fe39	156
3bdd58a4	157	new_qemu = now_qemu + muldiv64((uint32_t) (s->tm4[n].tm.value - now_vm),
73bcb24d	158	NANOSECONDS_PER_SECOND, s->tm4[counter].freq);
bc72ad67	159	timer_mod(s->tm4[n].tm.qtimer, new_qemu);
a171fe39 AZ	160	}
a171fe39 AZ	161
a8170e5e	162	static uint64_t pxa2xx_timer_read(void *opaque, hwaddr offset,
b755bde3	163	unsigned size)
a171fe39	164	{
d353eb43	165	PXA2xxTimerInfo s = (PXA2xxTimerInfo ) opaque;
a171fe39 AZ	166	int tm = 0;
a171fe39 AZ	167
a171fe39 AZ	168	switch (offset) {
a171fe39 AZ	169	case OSMR3: tm ++;
de16017d	170	/* fall through */
a171fe39	171	case OSMR2: tm ++;
de16017d	172	/* fall through */
a171fe39	173	case OSMR1: tm ++;
de16017d	174	/* fall through */
a171fe39 AZ	175	case OSMR0:
	176	return s->timer[tm].value;
	177	case OSMR11: tm ++;
de16017d	178	/* fall through */
a171fe39	179	case OSMR10: tm ++;
de16017d	180	/* fall through */
a171fe39	181	case OSMR9: tm ++;
de16017d	182	/* fall through */
a171fe39	183	case OSMR8: tm ++;
de16017d	184	/* fall through */
a171fe39	185	case OSMR7: tm ++;
de16017d	186	/* fall through */
a171fe39	187	case OSMR6: tm ++;
de16017d	188	/* fall through */
a171fe39	189	case OSMR5: tm ++;
de16017d	190	/* fall through */
a171fe39	191	case OSMR4:
797e9542	192	if (!pxa2xx_timer_has_tm4(s))
a171fe39	193	goto badreg;
3bdd58a4	194	return s->tm4[tm].tm.value;
a171fe39	195	case OSCR:
bc72ad67	196	return s->clock + muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) -
73bcb24d	197	s->lastload, s->freq, NANOSECONDS_PER_SECOND);
a171fe39	198	case OSCR11: tm ++;
de16017d	199	/* fall through */
a171fe39	200	case OSCR10: tm ++;
de16017d	201	/* fall through */
a171fe39	202	case OSCR9: tm ++;
de16017d	203	/* fall through */
a171fe39	204	case OSCR8: tm ++;
de16017d	205	/* fall through */
a171fe39	206	case OSCR7: tm ++;
de16017d	207	/* fall through */
a171fe39	208	case OSCR6: tm ++;
de16017d	209	/* fall through */
a171fe39	210	case OSCR5: tm ++;
de16017d	211	/* fall through */
a171fe39	212	case OSCR4:
797e9542	213	if (!pxa2xx_timer_has_tm4(s))
a171fe39 AZ	214	goto badreg;
	215
	216	if ((tm == 9 - 4 \|\| tm == 11 - 4) && (s->tm4[tm].control & (1 << 9))) {
	217	if (s->tm4[tm - 1].freq)
	218	s->snapshot = s->tm4[tm - 1].clock + muldiv64(
bc72ad67	219	qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) -
a171fe39	220	s->tm4[tm - 1].lastload,
73bcb24d	221	s->tm4[tm - 1].freq, NANOSECONDS_PER_SECOND);
a171fe39 AZ	222	else
	223	s->snapshot = s->tm4[tm - 1].clock;
	224	}
	225
	226	if (!s->tm4[tm].freq)
	227	return s->tm4[tm].clock;
73bcb24d RS	228	return s->tm4[tm].clock +
	229	muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) -
	230	s->tm4[tm].lastload, s->tm4[tm].freq,
	231	NANOSECONDS_PER_SECOND);
a171fe39 AZ	232	case OIER:
	233	return s->irq_enabled;
	234	case OSSR: /* Status register */
	235	return s->events;
	236	case OWER:
	237	return s->reset3;
	238	case OMCR11: tm ++;
de16017d	239	/* fall through */
a171fe39	240	case OMCR10: tm ++;
de16017d	241	/* fall through */
a171fe39	242	case OMCR9: tm ++;
de16017d	243	/* fall through */
a171fe39	244	case OMCR8: tm ++;
de16017d	245	/* fall through */
a171fe39	246	case OMCR7: tm ++;
de16017d	247	/* fall through */
a171fe39	248	case OMCR6: tm ++;
de16017d	249	/* fall through */
a171fe39	250	case OMCR5: tm ++;
de16017d	251	/* fall through */
a171fe39	252	case OMCR4:
797e9542	253	if (!pxa2xx_timer_has_tm4(s))
a171fe39 AZ	254	goto badreg;
	255	return s->tm4[tm].control;
	256	case OSNR:
	257	return s->snapshot;
	258	default:
2ba63e4a PMD	259	qemu_log_mask(LOG_UNIMP,
	260	"%s: unknown register 0x%02" HWADDR_PRIx "\n",
	261	__func__, offset);
	262	break;
a171fe39	263	badreg:
2ba63e4a PMD	264	qemu_log_mask(LOG_GUEST_ERROR,
	265	"%s: incorrect register 0x%02" HWADDR_PRIx "\n",
	266	__func__, offset);
a171fe39 AZ	267	}
	268
	269	return 0;
	270	}
	271
a8170e5e	272	static void pxa2xx_timer_write(void *opaque, hwaddr offset,
b755bde3	273	uint64_t value, unsigned size)
a171fe39 AZ	274	{
a171fe39 AZ	275	int i, tm = 0;
d353eb43	276	PXA2xxTimerInfo s = (PXA2xxTimerInfo ) opaque;
a171fe39	277
a171fe39 AZ	278	switch (offset) {
a171fe39 AZ	279	case OSMR3: tm ++;
de16017d	280	/* fall through */
a171fe39	281	case OSMR2: tm ++;
de16017d	282	/* fall through */
a171fe39	283	case OSMR1: tm ++;
de16017d	284	/* fall through */
a171fe39 AZ	285	case OSMR0:
a171fe39 AZ	286	s->timer[tm].value = value;
bc72ad67	287	pxa2xx_timer_update(s, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
a171fe39 AZ	288	break;
a171fe39 AZ	289	case OSMR11: tm ++;
de16017d	290	/* fall through */
a171fe39	291	case OSMR10: tm ++;
de16017d	292	/* fall through */
a171fe39	293	case OSMR9: tm ++;
de16017d	294	/* fall through */
a171fe39	295	case OSMR8: tm ++;
de16017d	296	/* fall through */
a171fe39	297	case OSMR7: tm ++;
de16017d	298	/* fall through */
a171fe39	299	case OSMR6: tm ++;
de16017d	300	/* fall through */
a171fe39	301	case OSMR5: tm ++;
de16017d	302	/* fall through */
a171fe39	303	case OSMR4:
797e9542	304	if (!pxa2xx_timer_has_tm4(s))
a171fe39	305	goto badreg;
3bdd58a4	306	s->tm4[tm].tm.value = value;
bc72ad67	307	pxa2xx_timer_update4(s, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tm);
a171fe39 AZ	308	break;
	309	case OSCR:
	310	s->oldclock = s->clock;
bc72ad67	311	s->lastload = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
a171fe39 AZ	312	s->clock = value;
	313	pxa2xx_timer_update(s, s->lastload);
	314	break;
	315	case OSCR11: tm ++;
de16017d	316	/* fall through */
a171fe39	317	case OSCR10: tm ++;
de16017d	318	/* fall through */
a171fe39	319	case OSCR9: tm ++;
de16017d	320	/* fall through */
a171fe39	321	case OSCR8: tm ++;
de16017d	322	/* fall through */
a171fe39	323	case OSCR7: tm ++;
de16017d	324	/* fall through */
a171fe39	325	case OSCR6: tm ++;
de16017d	326	/* fall through */
a171fe39	327	case OSCR5: tm ++;
de16017d	328	/* fall through */
a171fe39	329	case OSCR4:
797e9542	330	if (!pxa2xx_timer_has_tm4(s))
a171fe39 AZ	331	goto badreg;
a171fe39 AZ	332	s->tm4[tm].oldclock = s->tm4[tm].clock;
bc72ad67	333	s->tm4[tm].lastload = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
a171fe39 AZ	334	s->tm4[tm].clock = value;
	335	pxa2xx_timer_update4(s, s->tm4[tm].lastload, tm);
	336	break;
	337	case OIER:
	338	s->irq_enabled = value & 0xfff;
	339	break;
	340	case OSSR: /* Status register */
8034ce7d	341	value &= s->events;
a171fe39	342	s->events &= ~value;
8034ce7d AZ	343	for (i = 0; i < 4; i ++, value >>= 1)
8034ce7d AZ	344	if (value & 1)
5251d196	345	qemu_irq_lower(s->timer[i].irq);
8034ce7d AZ	346	if (pxa2xx_timer_has_tm4(s) && !(s->events & 0xff0) && value)
8034ce7d AZ	347	qemu_irq_lower(s->irq4);
a171fe39 AZ	348	break;
	349	case OWER: /* XXX: Reset on OSMR3 match? */
	350	s->reset3 = value;
	351	break;
	352	case OMCR7: tm ++;
de16017d	353	/* fall through */
a171fe39	354	case OMCR6: tm ++;
de16017d	355	/* fall through */
a171fe39	356	case OMCR5: tm ++;
de16017d	357	/* fall through */
a171fe39	358	case OMCR4:
797e9542	359	if (!pxa2xx_timer_has_tm4(s))
a171fe39 AZ	360	goto badreg;
	361	s->tm4[tm].control = value & 0x0ff;
	362	/* XXX Stop if running (shouldn't happen) */
	363	if ((value & (1 << 7)) \|\| tm == 0)
	364	s->tm4[tm].freq = pxa2xx_timer4_freq[value & 7];
	365	else {
	366	s->tm4[tm].freq = 0;
bc72ad67	367	pxa2xx_timer_update4(s, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tm);
a171fe39 AZ	368	}
	369	break;
	370	case OMCR11: tm ++;
de16017d	371	/* fall through */
a171fe39	372	case OMCR10: tm ++;
de16017d	373	/* fall through */
a171fe39	374	case OMCR9: tm ++;
de16017d	375	/* fall through */
a171fe39	376	case OMCR8: tm += 4;
797e9542	377	if (!pxa2xx_timer_has_tm4(s))
a171fe39 AZ	378	goto badreg;
	379	s->tm4[tm].control = value & 0x3ff;
	380	/* XXX Stop if running (shouldn't happen) */
	381	if ((value & (1 << 7)) \|\| !(tm & 1))
	382	s->tm4[tm].freq =
	383	pxa2xx_timer4_freq[(value & (1 << 8)) ? 0 : (value & 7)];
	384	else {
	385	s->tm4[tm].freq = 0;
bc72ad67	386	pxa2xx_timer_update4(s, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tm);
a171fe39 AZ	387	}
	388	break;
	389	default:
2ba63e4a PMD	390	qemu_log_mask(LOG_UNIMP,
	391	"%s: unknown register 0x%02" HWADDR_PRIx " "
	392	"(value 0x%08" PRIx64 ")\n", __func__, offset, value);
	393	break;
a171fe39	394	badreg:
2ba63e4a PMD	395	qemu_log_mask(LOG_GUEST_ERROR,
	396	"%s: incorrect register 0x%02" HWADDR_PRIx " "
	397	"(value 0x%08" PRIx64 ")\n", __func__, offset, value);
a171fe39 AZ	398	}
	399	}
	400
b755bde3 BC	401	static const MemoryRegionOps pxa2xx_timer_ops = {
	402	.read = pxa2xx_timer_read,
	403	.write = pxa2xx_timer_write,
	404	.endianness = DEVICE_NATIVE_ENDIAN,
a171fe39 AZ	405	};
	406
	407	static void pxa2xx_timer_tick(void *opaque)
	408	{
bc24a225	409	PXA2xxTimer0 t = (PXA2xxTimer0 ) opaque;
797e9542	410	PXA2xxTimerInfo *i = t->info;
a171fe39 AZ	411
a171fe39 AZ	412	if (i->irq_enabled & (1 << t->num)) {
a171fe39	413	i->events \|= 1 << t->num;
5251d196	414	qemu_irq_raise(t->irq);
a171fe39 AZ	415	}
	416
	417	if (t->num == 3)
	418	if (i->reset3 & 1) {
	419	i->reset3 = 0;
cf83f140	420	qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
a171fe39 AZ	421	}
	422	}
	423
	424	static void pxa2xx_timer_tick4(void *opaque)
	425	{
bc24a225	426	PXA2xxTimer4 t = (PXA2xxTimer4 ) opaque;
d353eb43	427	PXA2xxTimerInfo i = (PXA2xxTimerInfo ) t->tm.info;
a171fe39	428
3bdd58a4	429	pxa2xx_timer_tick(&t->tm);
a171fe39 AZ	430	if (t->control & (1 << 3))
	431	t->clock = 0;
	432	if (t->control & (1 << 6))
bc72ad67	433	pxa2xx_timer_update4(i, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), t->tm.num - 4);
4ff927cc DES	434	if (i->events & 0xff0)
4ff927cc DES	435	qemu_irq_raise(i->irq4);
a171fe39 AZ	436	}
a171fe39 AZ	437
797e9542	438	static int pxa25x_timer_post_load(void *opaque, int version_id)
aa941b94	439	{
d353eb43	440	PXA2xxTimerInfo s = (PXA2xxTimerInfo ) opaque;
aa941b94 AZ	441	int64_t now;
	442	int i;
	443
bc72ad67	444	now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
aa941b94 AZ	445	pxa2xx_timer_update(s, now);
aa941b94 AZ	446
797e9542 DES	447	if (pxa2xx_timer_has_tm4(s))
797e9542 DES	448	for (i = 0; i < 8; i ++)
aa941b94	449	pxa2xx_timer_update4(s, now, i);
aa941b94 AZ	450
	451	return 0;
	452	}
	453
5d83e348	454	static void pxa2xx_timer_init(Object *obj)
a171fe39	455	{
5d83e348 XZ	456	PXA2xxTimerInfo *s = PXA2XX_TIMER(obj);
5d83e348 XZ	457	SysBusDevice *dev = SYS_BUS_DEVICE(obj);
a171fe39	458
a171fe39 AZ	459	s->irq_enabled = 0;
	460	s->oldclock = 0;
	461	s->clock = 0;
bc72ad67	462	s->lastload = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
a171fe39	463	s->reset3 = 0;
a171fe39	464
5d83e348 XZ	465	memory_region_init_io(&s->iomem, obj, &pxa2xx_timer_ops, s,
	466	"pxa2xx-timer", 0x00001000);
	467	sysbus_init_mmio(dev, &s->iomem);
	468	}
	469
	470	static void pxa2xx_timer_realize(DeviceState dev, Error *errp)
	471	{
	472	PXA2xxTimerInfo *s = PXA2XX_TIMER(dev);
	473	SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
	474	int i;
	475
a171fe39 AZ	476	for (i = 0; i < 4; i ++) {
a171fe39 AZ	477	s->timer[i].value = 0;
5d83e348	478	sysbus_init_irq(sbd, &s->timer[i].irq);
a171fe39 AZ	479	s->timer[i].info = s;
a171fe39 AZ	480	s->timer[i].num = i;
bc72ad67	481	s->timer[i].qtimer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
5d83e348	482	pxa2xx_timer_tick, &s->timer[i]);
a171fe39	483	}
5d83e348	484
797e9542	485	if (s->flags & (1 << PXA2XX_TIMER_HAVE_TM4)) {
5d83e348	486	sysbus_init_irq(sbd, &s->irq4);
797e9542 DES	487
	488	for (i = 0; i < 8; i ++) {
	489	s->tm4[i].tm.value = 0;
	490	s->tm4[i].tm.info = s;
	491	s->tm4[i].tm.num = i + 4;
797e9542 DES	492	s->tm4[i].freq = 0;
797e9542 DES	493	s->tm4[i].control = 0x0;
bc72ad67	494	s->tm4[i].tm.qtimer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
5d83e348	495	pxa2xx_timer_tick4, &s->tm4[i]);
797e9542 DES	496	}
797e9542 DES	497	}
a171fe39 AZ	498	}
a171fe39 AZ	499
797e9542 DES	500	static const VMStateDescription vmstate_pxa2xx_timer0_regs = {
797e9542 DES	501	.name = "pxa2xx_timer0",
8034ce7d AZ	502	.version_id = 2,
8034ce7d AZ	503	.minimum_version_id = 2,
797e9542 DES	504	.fields = (VMStateField[]) {
797e9542 DES	505	VMSTATE_UINT32(value, PXA2xxTimer0),
797e9542 DES	506	VMSTATE_END_OF_LIST(),
	507	},
	508	};
	509
	510	static const VMStateDescription vmstate_pxa2xx_timer4_regs = {
	511	.name = "pxa2xx_timer4",
	512	.version_id = 1,
	513	.minimum_version_id = 1,
797e9542 DES	514	.fields = (VMStateField[]) {
	515	VMSTATE_STRUCT(tm, PXA2xxTimer4, 1,
	516	vmstate_pxa2xx_timer0_regs, PXA2xxTimer0),
	517	VMSTATE_INT32(oldclock, PXA2xxTimer4),
	518	VMSTATE_INT32(clock, PXA2xxTimer4),
	519	VMSTATE_UINT64(lastload, PXA2xxTimer4),
	520	VMSTATE_UINT32(freq, PXA2xxTimer4),
	521	VMSTATE_UINT32(control, PXA2xxTimer4),
	522	VMSTATE_END_OF_LIST(),
	523	},
	524	};
	525
	526	static bool pxa2xx_timer_has_tm4_test(void *opaque, int version_id)
a171fe39	527	{
797e9542	528	return pxa2xx_timer_has_tm4(opaque);
a171fe39 AZ	529	}
a171fe39 AZ	530
797e9542 DES	531	static const VMStateDescription vmstate_pxa2xx_timer_regs = {
	532	.name = "pxa2xx_timer",
	533	.version_id = 1,
	534	.minimum_version_id = 1,
797e9542 DES	535	.post_load = pxa25x_timer_post_load,
	536	.fields = (VMStateField[]) {
	537	VMSTATE_INT32(clock, PXA2xxTimerInfo),
	538	VMSTATE_INT32(oldclock, PXA2xxTimerInfo),
	539	VMSTATE_UINT64(lastload, PXA2xxTimerInfo),
	540	VMSTATE_STRUCT_ARRAY(timer, PXA2xxTimerInfo, 4, 1,
	541	vmstate_pxa2xx_timer0_regs, PXA2xxTimer0),
	542	VMSTATE_UINT32(events, PXA2xxTimerInfo),
	543	VMSTATE_UINT32(irq_enabled, PXA2xxTimerInfo),
	544	VMSTATE_UINT32(reset3, PXA2xxTimerInfo),
	545	VMSTATE_UINT32(snapshot, PXA2xxTimerInfo),
	546	VMSTATE_STRUCT_ARRAY_TEST(tm4, PXA2xxTimerInfo, 8,
	547	pxa2xx_timer_has_tm4_test, 0,
	548	vmstate_pxa2xx_timer4_regs, PXA2xxTimer4),
	549	VMSTATE_END_OF_LIST(),
a171fe39	550	}
797e9542 DES	551	};
797e9542 DES	552
999e12bb AL	553	static Property pxa25x_timer_dev_properties[] = {
	554	DEFINE_PROP_UINT32("freq", PXA2xxTimerInfo, freq, PXA25X_FREQ),
	555	DEFINE_PROP_BIT("tm4", PXA2xxTimerInfo, flags,
feea4361	556	PXA2XX_TIMER_HAVE_TM4, false),
999e12bb	557	DEFINE_PROP_END_OF_LIST(),
797e9542 DES	558	};
797e9542 DES	559
999e12bb AL	560	static void pxa25x_timer_dev_class_init(ObjectClass klass, void data)
999e12bb AL	561	{
39bffca2	562	DeviceClass *dc = DEVICE_CLASS(klass);
999e12bb	563
39bffca2	564	dc->desc = "PXA25x timer";
39bffca2	565	dc->props = pxa25x_timer_dev_properties;
999e12bb AL	566	}
999e12bb AL	567
8c43a6f0	568	static const TypeInfo pxa25x_timer_dev_info = {
39bffca2	569	.name = "pxa25x-timer",
feea4361	570	.parent = TYPE_PXA2XX_TIMER,
39bffca2 AL	571	.instance_size = sizeof(PXA2xxTimerInfo),
39bffca2 AL	572	.class_init = pxa25x_timer_dev_class_init,
999e12bb AL	573	};
	574
	575	static Property pxa27x_timer_dev_properties[] = {
	576	DEFINE_PROP_UINT32("freq", PXA2xxTimerInfo, freq, PXA27X_FREQ),
	577	DEFINE_PROP_BIT("tm4", PXA2xxTimerInfo, flags,
feea4361	578	PXA2XX_TIMER_HAVE_TM4, true),
999e12bb AL	579	DEFINE_PROP_END_OF_LIST(),
	580	};
	581
	582	static void pxa27x_timer_dev_class_init(ObjectClass klass, void data)
	583	{
39bffca2	584	DeviceClass *dc = DEVICE_CLASS(klass);
999e12bb	585
39bffca2	586	dc->desc = "PXA27x timer";
39bffca2	587	dc->props = pxa27x_timer_dev_properties;
999e12bb AL	588	}
999e12bb AL	589
8c43a6f0	590	static const TypeInfo pxa27x_timer_dev_info = {
39bffca2	591	.name = "pxa27x-timer",
feea4361	592	.parent = TYPE_PXA2XX_TIMER,
39bffca2 AL	593	.instance_size = sizeof(PXA2xxTimerInfo),
39bffca2 AL	594	.class_init = pxa27x_timer_dev_class_init,
797e9542 DES	595	};
797e9542 DES	596
feea4361 AF	597	static void pxa2xx_timer_class_init(ObjectClass oc, void data)
	598	{
	599	DeviceClass *dc = DEVICE_CLASS(oc);
feea4361	600
5d83e348	601	dc->realize = pxa2xx_timer_realize;
feea4361 AF	602	dc->vmsd = &vmstate_pxa2xx_timer_regs;
	603	}
	604
	605	static const TypeInfo pxa2xx_timer_type_info = {
	606	.name = TYPE_PXA2XX_TIMER,
	607	.parent = TYPE_SYS_BUS_DEVICE,
	608	.instance_size = sizeof(PXA2xxTimerInfo),
5d83e348	609	.instance_init = pxa2xx_timer_init,
feea4361 AF	610	.abstract = true,
	611	.class_init = pxa2xx_timer_class_init,
	612	};
	613
83f7d43a	614	static void pxa2xx_timer_register_types(void)
797e9542	615	{
feea4361	616	type_register_static(&pxa2xx_timer_type_info);
39bffca2 AL	617	type_register_static(&pxa25x_timer_dev_info);
39bffca2 AL	618	type_register_static(&pxa27x_timer_dev_info);
83f7d43a AF	619	}
	620
	621	type_init(pxa2xx_timer_register_types)