projects / qemu.git / blame
| Commit | Line | Data |
|---|---|---|
| e723b871 | 1 | # See docs/tracing.txt for syntax documentation. |
| aebd4d17 DB |
2 | |
| 3 | # hw/intc/apic_common.c | |
| 4 | cpu_set_apic_base(uint64_t val) "%016"PRIx64 | |
| 5 | cpu_get_apic_base(uint64_t val) "%016"PRIx64 | |
| 6 | # coalescing | |
| 7 | apic_report_irq_delivered(int apic_irq_delivered) "coalescing %d" | |
| 8 | apic_reset_irq_delivered(int apic_irq_delivered) "old coalescing %d" | |
| 9 | apic_get_irq_delivered(int apic_irq_delivered) "returning coalescing %d" | |
| 10 | ||
| 11 | # hw/intc/apic.c | |
| 12 | apic_local_deliver(int vector, uint32_t lvt) "vector %d delivery mode %d" | |
| 13 | apic_deliver_irq(uint8_t dest, uint8_t dest_mode, uint8_t delivery_mode, uint8_t vector_num, uint8_t trigger_mode) "dest %d dest_mode %d delivery_mode %d vector %d trigger_mode %d" | |
| 14 | apic_mem_readl(uint64_t addr, uint32_t val) "%"PRIx64" = %08x" | |
| 15 | apic_mem_writel(uint64_t addr, uint32_t val) "%"PRIx64" = %08x" | |
| 16 | ||
| e5074b38 PX |
17 | # hw/intc/ioapic.c |
| 18 | ioapic_set_remote_irr(int n) "set remote irr for pin %d" | |
| 19 | ioapic_clear_remote_irr(int n, int vector) "clear remote irr for pin %d vector %d" | |
| 20 | ioapic_eoi_broadcast(int vector) "EOI broadcast for vector %d" | |
| 21 | ioapic_mem_read(uint8_t addr, uint8_t size, uint32_t val) "ioapic mem read addr 0x%"PRIx8" size 0x%"PRIx8" retval 0x%"PRIx32 | |
| 22 | ioapic_mem_write(uint8_t addr, uint8_t size, uint32_t val) "ioapic mem write addr 0x%"PRIx8" size 0x%"PRIx8" val 0x%"PRIx32 | |
| 23 | ||
| aebd4d17 DB |
24 | # hw/intc/slavio_intctl.c |
| 25 | slavio_intctl_mem_readl(uint32_t cpu, uint64_t addr, uint32_t ret) "read cpu %d reg 0x%"PRIx64" = %x" | |
| 26 | slavio_intctl_mem_writel(uint32_t cpu, uint64_t addr, uint32_t val) "write cpu %d reg 0x%"PRIx64" = %x" | |
| 27 | slavio_intctl_mem_writel_clear(uint32_t cpu, uint32_t val, uint32_t intreg_pending) "Cleared cpu %d irq mask %x, curmask %x" | |
| 28 | slavio_intctl_mem_writel_set(uint32_t cpu, uint32_t val, uint32_t intreg_pending) "Set cpu %d irq mask %x, curmask %x" | |
| 29 | slavio_intctlm_mem_readl(uint64_t addr, uint32_t ret) "read system reg 0x%"PRIx64" = %x" | |
| 30 | slavio_intctlm_mem_writel(uint64_t addr, uint32_t val) "write system reg 0x%"PRIx64" = %x" | |
| 31 | slavio_intctlm_mem_writel_enable(uint32_t val, uint32_t intregm_disabled) "Enabled master irq mask %x, curmask %x" | |
| 32 | slavio_intctlm_mem_writel_disable(uint32_t val, uint32_t intregm_disabled) "Disabled master irq mask %x, curmask %x" | |
| 33 | slavio_intctlm_mem_writel_target(uint32_t cpu) "Set master irq cpu %d" | |
| 34 | slavio_check_interrupts(uint32_t pending, uint32_t intregm_disabled) "pending %x disabled %x" | |
| 35 | slavio_set_irq(uint32_t target_cpu, int irq, uint32_t pil, int level) "Set cpu %d irq %d -> pil %d level %d" | |
| 36 | slavio_set_timer_irq_cpu(int cpu, int level) "Set cpu %d local timer level %d" | |
| 37 | ||
| 38 | # hw/intc/grlib_irqmp.c | |
| 39 | grlib_irqmp_check_irqs(uint32_t pend, uint32_t force, uint32_t mask, uint32_t lvl1, uint32_t lvl2) "pend:0x%04x force:0x%04x mask:0x%04x lvl1:0x%04x lvl0:0x%04x" | |
| 40 | grlib_irqmp_ack(int intno) "interrupt:%d" | |
| 41 | grlib_irqmp_set_irq(int irq) "Raise CPU IRQ %d" | |
| 42 | grlib_irqmp_readl_unknown(uint64_t addr) "addr 0x%"PRIx64 | |
| 43 | grlib_irqmp_writel_unknown(uint64_t addr, uint32_t value) "addr 0x%"PRIx64" value 0x%x" | |
| 44 | ||
| 45 | # hw/intc/lm32_pic.c | |
| 46 | lm32_pic_raise_irq(void) "Raise CPU interrupt" | |
| 47 | lm32_pic_lower_irq(void) "Lower CPU interrupt" | |
| 48 | lm32_pic_interrupt(int irq, int level) "Set IRQ%d %d" | |
| 49 | lm32_pic_set_im(uint32_t im) "im 0x%08x" | |
| 50 | lm32_pic_set_ip(uint32_t ip) "ip 0x%08x" | |
| 51 | lm32_pic_get_im(uint32_t im) "im 0x%08x" | |
| 52 | lm32_pic_get_ip(uint32_t ip) "ip 0x%08x" | |
| 53 | ||
| 54 | # hw/intc/xics.c | |
| 55 | xics_icp_check_ipi(int server, uint8_t mfrr) "CPU %d can take IPI mfrr=%#x" | |
| 56 | xics_icp_accept(uint32_t old_xirr, uint32_t new_xirr) "icp_accept: XIRR %#"PRIx32"->%#"PRIx32 | |
| 57 | xics_icp_eoi(int server, uint32_t xirr, uint32_t new_xirr) "icp_eoi: server %d given XIRR %#"PRIx32" new XIRR %#"PRIx32 | |
| 58 | xics_icp_irq(int server, int nr, uint8_t priority) "cpu %d trying to deliver irq %#"PRIx32" priority %#x" | |
| 59 | xics_icp_raise(uint32_t xirr, uint8_t pending_priority) "raising IRQ new XIRR=%#x new pending priority=%#x" | |
| d4d7a59a | 60 | xics_ics_simple_set_irq_msi(int srcno, int nr) "set_irq_msi: srcno %d [irq %#x]" |
| aebd4d17 | 61 | xics_masked_pending(void) "set_irq_msi: masked pending" |
| d4d7a59a BH |
62 | xics_ics_simple_set_irq_lsi(int srcno, int nr) "set_irq_lsi: srcno %d [irq %#x]" |
| 63 | xics_ics_simple_write_xive(int nr, int srcno, int server, uint8_t priority) "ics_write_xive: irq %#x [src %d] server %#x prio %#x" | |
| 64 | xics_ics_simple_reject(int nr, int srcno) "reject irq %#x [src %d]" | |
| 65 | xics_ics_simple_eoi(int nr) "ics_eoi: irq %#x" | |
| cc706a53 BH |
66 | xics_alloc(int irq) "irq %d" |
| 67 | xics_alloc_block(int first, int num, bool lsi, int align) "first irq %d, %d irqs, lsi=%d, alignnum %d" | |
| aebd4d17 DB |
68 | xics_ics_free(int src, int irq, int num) "Source#%d, first irq %d, %d irqs" |
| 69 | xics_ics_free_warn(int src, int irq) "Source#%d, irq %d is already free" | |
| 70 | ||
| 71 | # hw/intc/s390_flic_kvm.c | |
| 72 | flic_create_device(int err) "flic: create device failed %d" | |
| 73 | flic_no_device_api(int err) "flic: no Device Contral API support %d" | |
| 74 | flic_reset_failed(int err) "flic: reset failed %d" | |
| 75 | ||
| 76 | # hw/intc/aspeed_vic.c | |
| 77 | aspeed_vic_set_irq(int irq, int level) "Enabling IRQ %d: %d" | |
| 78 | aspeed_vic_update_fiq(int flags) "Raising FIQ: %d" | |
| 79 | aspeed_vic_update_irq(int flags) "Raising IRQ: %d" | |
| 80 | aspeed_vic_read(uint64_t offset, unsigned size, uint32_t value) "From 0x%" PRIx64 " of size %u: 0x%" PRIx32 | |
| 81 | aspeed_vic_write(uint64_t offset, unsigned size, uint32_t data) "To 0x%" PRIx64 " of size %u: 0x%" PRIx32 | |
| 82 | ||
| 83 | # hw/intc/arm_gic.c | |
| 84 | gic_enable_irq(int irq) "irq %d enabled" | |
| 85 | gic_disable_irq(int irq) "irq %d disabled" | |
| 86 | gic_set_irq(int irq, int level, int cpumask, int target) "irq %d level %d cpumask 0x%x target 0x%x" | |
| 87 | gic_update_bestirq(int cpu, int irq, int prio, int priority_mask, int running_priority) "cpu %d irq %d priority %d cpu priority mask %d cpu running priority %d" | |
| 88 | gic_update_set_irq(int cpu, const char *name, int level) "cpu[%d]: %s = %d" | |
| 89 | gic_acknowledge_irq(int cpu, int irq) "cpu %d acknowledged irq %d" | |
| 90 | ||
| 91 | # hw/intc/arm_gicv3_cpuif.c | |
| 92 | gicv3_icc_pmr_read(uint32_t cpu, uint64_t val) "GICv3 ICC_PMR read cpu %x value 0x%" PRIx64 | |
| 93 | gicv3_icc_pmr_write(uint32_t cpu, uint64_t val) "GICv3 ICC_PMR write cpu %x value 0x%" PRIx64 | |
| 081b1b98 PM |
94 | gicv3_icc_bpr_read(int grp, uint32_t cpu, uint64_t val) "GICv3 ICC_BPR%d read cpu %x value 0x%" PRIx64 |
| 95 | gicv3_icc_bpr_write(int grp, uint32_t cpu, uint64_t val) "GICv3 ICC_BPR%d write cpu %x value 0x%" PRIx64 | |
| 96 | gicv3_icc_ap_read(int grp, int regno, uint32_t cpu, uint64_t val) "GICv3 ICC_AP%dR%d read cpu %x value 0x%" PRIx64 | |
| 97 | gicv3_icc_ap_write(int grp, int regno, uint32_t cpu, uint64_t val) "GICv3 ICC_AP%dR%d write cpu %x value 0x%" PRIx64 | |
| 98 | gicv3_icc_igrpen_read(int grp, uint32_t cpu, uint64_t val) "GICv3 ICC_IGRPEN%d read cpu %x value 0x%" PRIx64 | |
| 99 | gicv3_icc_igrpen_write(int grp, uint32_t cpu, uint64_t val) "GICv3 ICC_IGRPEN%d write cpu %x value 0x%" PRIx64 | |
| aebd4d17 DB |
100 | gicv3_icc_igrpen1_el3_read(uint32_t cpu, uint64_t val) "GICv3 ICC_IGRPEN1_EL3 read cpu %x value 0x%" PRIx64 |
| 101 | gicv3_icc_igrpen1_el3_write(uint32_t cpu, uint64_t val) "GICv3 ICC_IGRPEN1_EL3 write cpu %x value 0x%" PRIx64 | |
| 102 | gicv3_icc_ctlr_read(uint32_t cpu, uint64_t val) "GICv3 ICC_CTLR read cpu %x value 0x%" PRIx64 | |
| 103 | gicv3_icc_ctlr_write(uint32_t cpu, uint64_t val) "GICv3 ICC_CTLR write cpu %x value 0x%" PRIx64 | |
| 104 | gicv3_icc_ctlr_el3_read(uint32_t cpu, uint64_t val) "GICv3 ICC_CTLR_EL3 read cpu %x value 0x%" PRIx64 | |
| 105 | gicv3_icc_ctlr_el3_write(uint32_t cpu, uint64_t val) "GICv3 ICC_CTLR_EL3 write cpu %x value 0x%" PRIx64 | |
| 106 | gicv3_cpuif_update(uint32_t cpuid, int irq, int grp, int prio) "GICv3 CPU i/f %x HPPI update: irq %d group %d prio %d" | |
| 107 | gicv3_cpuif_set_irqs(uint32_t cpuid, int fiqlevel, int irqlevel) "GICv3 CPU i/f %x HPPI update: setting FIQ %d IRQ %d" | |
| 108 | gicv3_icc_generate_sgi(uint32_t cpuid, int irq, int irm, uint32_t aff, uint32_t targetlist) "GICv3 CPU i/f %x generating SGI %d IRM %d target affinity 0x%xxx targetlist 0x%x" | |
| 109 | gicv3_icc_iar0_read(uint32_t cpu, uint64_t val) "GICv3 ICC_IAR0 read cpu %x value 0x%" PRIx64 | |
| 110 | gicv3_icc_iar1_read(uint32_t cpu, uint64_t val) "GICv3 ICC_IAR1 read cpu %x value 0x%" PRIx64 | |
| 081b1b98 | 111 | gicv3_icc_eoir_write(int grp, uint32_t cpu, uint64_t val) "GICv3 ICC_EOIR%d write cpu %x value 0x%" PRIx64 |
| aebd4d17 DB |
112 | gicv3_icc_hppir0_read(uint32_t cpu, uint64_t val) "GICv3 ICC_HPPIR0 read cpu %x value 0x%" PRIx64 |
| 113 | gicv3_icc_hppir1_read(uint32_t cpu, uint64_t val) "GICv3 ICC_HPPIR1 read cpu %x value 0x%" PRIx64 | |
| 114 | gicv3_icc_dir_write(uint32_t cpu, uint64_t val) "GICv3 ICC_DIR write cpu %x value 0x%" PRIx64 | |
| 115 | gicv3_icc_rpr_read(uint32_t cpu, uint64_t val) "GICv3 ICC_RPR read cpu %x value 0x%" PRIx64 | |
| 83f036fe PM |
116 | gicv3_ich_ap_read(int grp, int regno, uint32_t cpu, uint64_t val) "GICv3 ICH_AP%dR%d read cpu %x value 0x%" PRIx64 |
| 117 | gicv3_ich_ap_write(int grp, int regno, uint32_t cpu, uint64_t val) "GICv3 ICH_AP%dR%d write cpu %x value 0x%" PRIx64 | |
| 118 | gicv3_ich_hcr_read(uint32_t cpu, uint64_t val) "GICv3 ICH_HCR_EL2 read cpu %x value 0x%" PRIx64 | |
| 119 | gicv3_ich_hcr_write(uint32_t cpu, uint64_t val) "GICv3 ICH_HCR_EL2 write cpu %x value 0x%" PRIx64 | |
| 120 | gicv3_ich_vmcr_read(uint32_t cpu, uint64_t val) "GICv3 ICH_VMCR_EL2 read cpu %x value 0x%" PRIx64 | |
| 121 | gicv3_ich_vmcr_write(uint32_t cpu, uint64_t val) "GICv3 ICH_VMCR_EL2 write cpu %x value 0x%" PRIx64 | |
| 122 | gicv3_ich_lr_read(int regno, uint32_t cpu, uint64_t val) "GICv3 ICH_LR%d_EL2 read cpu %x value 0x%" PRIx64 | |
| 123 | gicv3_ich_lr32_read(int regno, uint32_t cpu, uint32_t val) "GICv3 ICH_LR%d read cpu %x value 0x%" PRIx32 | |
| 124 | gicv3_ich_lrc_read(int regno, uint32_t cpu, uint32_t val) "GICv3 ICH_LRC%d read cpu %x value 0x%" PRIx32 | |
| 125 | gicv3_ich_lr_write(int regno, uint32_t cpu, uint64_t val) "GICv3 ICH_LR%d_EL2 write cpu %x value 0x%" PRIx64 | |
| 126 | gicv3_ich_lr32_write(int regno, uint32_t cpu, uint32_t val) "GICv3 ICH_LR%d write cpu %x value 0x%" PRIx32 | |
| 127 | gicv3_ich_lrc_write(int regno, uint32_t cpu, uint32_t val) "GICv3 ICH_LRC%d write cpu %x value 0x%" PRIx32 | |
| 128 | gicv3_ich_vtr_read(uint32_t cpu, uint64_t val) "GICv3 ICH_VTR read cpu %x value 0x%" PRIx64 | |
| 129 | gicv3_ich_misr_read(uint32_t cpu, uint64_t val) "GICv3 ICH_MISR read cpu %x value 0x%" PRIx64 | |
| 130 | gicv3_ich_eisr_read(uint32_t cpu, uint64_t val) "GICv3 ICH_EISR read cpu %x value 0x%" PRIx64 | |
| 131 | gicv3_ich_elrsr_read(uint32_t cpu, uint64_t val) "GICv3 ICH_ELRSR read cpu %x value 0x%" PRIx64 | |
| 77620ba6 PM |
132 | gicv3_icv_ap_read(int grp, int regno, uint32_t cpu, uint64_t val) "GICv3 ICV_AP%dR%d read cpu %x value 0x%" PRIx64 |
| 133 | gicv3_icv_ap_write(int grp, int regno, uint32_t cpu, uint64_t val) "GICv3 ICV_AP%dR%d write cpu %x value 0x%" PRIx64 | |
| 134 | gicv3_icv_bpr_read(int grp, uint32_t cpu, uint64_t val) "GICv3 ICV_BPR%d read cpu %x value 0x%" PRIx64 | |
| 135 | gicv3_icv_bpr_write(int grp, uint32_t cpu, uint64_t val) "GICv3 ICV_BPR%d write cpu %x value 0x%" PRIx64 | |
| 136 | gicv3_icv_pmr_read(uint32_t cpu, uint64_t val) "GICv3 ICV_PMR read cpu %x value 0x%" PRIx64 | |
| 137 | gicv3_icv_pmr_write(uint32_t cpu, uint64_t val) "GICv3 ICV_PMR write cpu %x value 0x%" PRIx64 | |
| 138 | gicv3_icv_igrpen_read(int grp, uint32_t cpu, uint64_t val) "GICv3 ICV_IGRPEN%d read cpu %x value 0x%" PRIx64 | |
| 139 | gicv3_icv_igrpen_write(int grp, uint32_t cpu, uint64_t val) "GICv3 ICV_IGRPEN%d write cpu %x value 0x%" PRIx64 | |
| 140 | gicv3_icv_ctlr_read(uint32_t cpu, uint64_t val) "GICv3 ICV_CTLR read cpu %x value 0x%" PRIx64 | |
| 141 | gicv3_icv_ctlr_write(uint32_t cpu, uint64_t val) "GICv3 ICV_CTLR write cpu %x value 0x%" PRIx64 | |
| df313f48 PM |
142 | gicv3_icv_rpr_read(uint32_t cpu, uint64_t val) "GICv3 ICV_RPR read cpu %x value 0x%" PRIx64 |
| 143 | gicv3_icv_hppir_read(int grp, uint32_t cpu, uint64_t val) "GICv3 ICV_HPPIR%d read cpu %x value 0x%" PRIx64 | |
| 144 | gicv3_icv_dir_write(uint32_t cpu, uint64_t val) "GICv3 ICV_DIR write cpu %x value 0x%" PRIx64 | |
| b3b48f52 PM |
145 | gicv3_icv_iar_read(int grp, uint32_t cpu, uint64_t val) "GICv3 ICV_IAR%d read cpu %x value 0x%" PRIx64 |
| 146 | gicv3_icv_eoir_write(int grp, uint32_t cpu, uint64_t val) "GICv3 ICV_EOIR%d write cpu %x value 0x%" PRIx64 | |
| c5fc89b3 PM |
147 | gicv3_cpuif_virt_update(uint32_t cpuid, int idx) "GICv3 CPU i/f %x virt HPPI update LR index %d" |
| 148 | gicv3_cpuif_virt_set_irqs(uint32_t cpuid, int fiqlevel, int irqlevel, int maintlevel) "GICv3 CPU i/f %x virt HPPI update: setting FIQ %d IRQ %d maintenance-irq %d" | |
| aebd4d17 DB |
149 | |
| 150 | # hw/intc/arm_gicv3_dist.c | |
| 151 | gicv3_dist_read(uint64_t offset, uint64_t data, unsigned size, bool secure) "GICv3 distributor read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u secure %d" | |
| 152 | gicv3_dist_badread(uint64_t offset, unsigned size, bool secure) "GICv3 distributor read: offset 0x%" PRIx64 " size %u secure %d: error" | |
| 153 | gicv3_dist_write(uint64_t offset, uint64_t data, unsigned size, bool secure) "GICv3 distributor write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u secure %d" | |
| 154 | gicv3_dist_badwrite(uint64_t offset, uint64_t data, unsigned size, bool secure) "GICv3 distributor write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u secure %d: error" | |
| 155 | gicv3_dist_set_irq(int irq, int level) "GICv3 distributor interrupt %d level changed to %d" | |
| 156 | ||
| 157 | # hw/intc/arm_gicv3_redist.c | |
| 158 | gicv3_redist_read(uint32_t cpu, uint64_t offset, uint64_t data, unsigned size, bool secure) "GICv3 redistributor %x read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u secure %d" | |
| 159 | gicv3_redist_badread(uint32_t cpu, uint64_t offset, unsigned size, bool secure) "GICv3 redistributor %x read: offset 0x%" PRIx64 " size %u secure %d: error" | |
| 160 | gicv3_redist_write(uint32_t cpu, uint64_t offset, uint64_t data, unsigned size, bool secure) "GICv3 redistributor %x write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u secure %d" | |
| 161 | gicv3_redist_badwrite(uint32_t cpu, uint64_t offset, uint64_t data, unsigned size, bool secure) "GICv3 redistributor %x write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u secure %d: error" | |
| 162 | gicv3_redist_set_irq(uint32_t cpu, int irq, int level) "GICv3 redistributor %x interrupt %d level changed to %d" | |
| 163 | gicv3_redist_send_sgi(uint32_t cpu, int irq) "GICv3 redistributor %x pending SGI %d" | |
| da6d674e MD |
164 | |
| 165 | # hw/intc/armv7m_nvic.c | |
| 166 | nvic_recompute_state(int vectpending, int exception_prio) "NVIC state recomputed: vectpending %d exception_prio %d" | |
| 167 | nvic_set_prio(int irq, uint8_t prio) "NVIC set irq %d priority %d" | |
| 168 | nvic_irq_update(int vectpending, int pendprio, int exception_prio, int level) "NVIC vectpending %d pending prio %d exception_prio %d: setting irq line to %d" | |
| 169 | nvic_escalate_prio(int irq, int irqprio, int runprio) "NVIC escalating irq %d to HardFault: insufficient priority %d >= %d" | |
| 170 | nvic_escalate_disabled(int irq) "NVIC escalating irq %d to HardFault: disabled" | |
| 171 | nvic_set_pending(int irq, int en, int prio) "NVIC set pending irq %d (enabled: %d priority %d)" | |
| 172 | nvic_clear_pending(int irq, int en, int prio) "NVIC clear pending irq %d (enabled: %d priority %d)" | |
| 173 | nvic_set_pending_level(int irq) "NVIC set pending: irq %d higher prio than vectpending: setting irq line to 1" | |
| 174 | nvic_acknowledge_irq(int irq, int prio) "NVIC acknowledge IRQ: %d now active (prio %d)" | |
| 175 | nvic_complete_irq(int irq) "NVIC complete IRQ %d" | |
| 176 | nvic_set_irq_level(int irq, int level) "NVIC external irq %d level set to %d" | |
| 177 | nvic_sysreg_read(uint64_t addr, uint32_t value, unsigned size) "NVIC sysreg read addr 0x%" PRIx64 " data 0x%" PRIx32 " size %u" | |
| 178 | nvic_sysreg_write(uint64_t addr, uint32_t value, unsigned size) "NVIC sysreg write addr 0x%" PRIx64 " data 0x%" PRIx32 " size %u" |