[qemu.git] / hw / g364fb.c

/*
 * QEMU G364 framebuffer Emulator.
 *
 * Copyright (c) 2007-2008 Hervé Poussineau
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include "hw.h"
#include "console.h"
#include "pixel_ops.h"

//#define DEBUG_G364

typedef struct G364State {
    target_phys_addr_t vram_base;
    unsigned int vram_size;
    uint8_t *vram_buffer;
    uint32_t ctla;
    uint8_t palette[256][3];
    /* display refresh support */
    DisplayState *ds;
    QEMUConsole *console;
    int graphic_mode;
    uint32_t scr_width, scr_height; /* in pixels */
    uint32_t last_scr_width, last_scr_height; /* in pixels */
} G364State;

/*
 * graphic modes
 */
#define BPP 8
#define PIXEL_WIDTH 8
#include "g364fb_template.h"
#undef BPP
#undef PIXEL_WIDTH

#define BPP 15
#define PIXEL_WIDTH 16
#include "g364fb_template.h"
#undef BPP
#undef PIXEL_WIDTH

#define BPP 16
#define PIXEL_WIDTH 16
#include "g364fb_template.h"
#undef BPP
#undef PIXEL_WIDTH

#define BPP 32
#define PIXEL_WIDTH 32
#include "g364fb_template.h"
#undef BPP
#undef PIXEL_WIDTH

#define REG_DISPLAYX 0x0918
#define REG_DISPLAYY 0x0940

#define CTLA_FORCE_BLANK 0x400

static void g364fb_draw_graphic(G364State *s, int full_update)
{
    if (s->scr_width == 0 || s->scr_height == 0)
        return;

    switch (s->ds->depth) {
        case 8:
            g364fb_draw_graphic8(s, full_update);
            break;
        case 15:
            g364fb_draw_graphic15(s, full_update);
            break;
        case 16:
            g364fb_draw_graphic16(s, full_update);
            break;
        case 32:
            g364fb_draw_graphic32(s, full_update);
            break;
        default:
            printf("g364fb: unknown depth %d\n", s->ds->depth);
            return;
    }

    dpy_update(s->ds, 0, 0, s->last_scr_width, s->last_scr_height);
}

static void g364fb_draw_blank(G364State *s, int full_update)
{
    int i, w;
    uint8_t *d;

    if (!full_update)
        return;
    if (s->last_scr_width <= 0 || s->last_scr_height <= 0)
        return;

    w = s->last_scr_width * ((s->ds->depth + 7) >> 3);
    d = s->ds->data;
    for(i = 0; i < s->last_scr_height; i++) {
        memset(d, 0, w);
        d += s->ds->linesize;
    }
    dpy_update(s->ds, 0, 0,
               s->last_scr_width, s->last_scr_height);
}

#define GMODE_GRAPH 0
#define GMODE_BLANK 1

static void g364fb_update_display(void *opaque)
{
    G364State *s = opaque;
    int full_update, graphic_mode;

    if (s->ctla & CTLA_FORCE_BLANK)
        graphic_mode = GMODE_BLANK;
    else
        graphic_mode = GMODE_GRAPH;
    full_update = 0;
    if (graphic_mode != s->graphic_mode) {
        s->graphic_mode = graphic_mode;
        full_update = 1;
    }
    switch(graphic_mode) {
        case GMODE_GRAPH:
            g364fb_draw_graphic(s, full_update);
            break;
        case GMODE_BLANK:
        default:
            g364fb_draw_blank(s, full_update);
            break;
    }
}

/* force a full display refresh */
static void g364fb_invalidate_display(void *opaque)
{
    G364State *s = opaque;
    s->graphic_mode = -1; /* force full update */
}

static void g364fb_reset(void *opaque)
{
    G364State *s = opaque;

    memset(s->palette, 0, sizeof(s->palette));
    s->scr_width = s->scr_height = 0;
    s->last_scr_width = s->last_scr_height = 0;
    memset(s->vram_buffer, 0, s->vram_size);
    s->graphic_mode = -1; /* force full update */
}

static void g364fb_screen_dump(void *opaque, const char *filename)
{
    G364State *s = opaque;
    int y, x;
    uint8_t index;
    uint8_t *data_buffer;
    FILE *f;

    f = fopen(filename, "wb");
    if (!f)
        return;

    data_buffer = s->vram_buffer;
    fprintf(f, "P6\n%d %d\n%d\n",
        s->scr_width, s->scr_height, 255);
    for(y = 0; y < s->scr_height; y++)
        for(x = 0; x < s->scr_width; x++, data_buffer++) {
            index = *data_buffer;
            fputc(s->palette[index][0], f);
            fputc(s->palette[index][1], f);
            fputc(s->palette[index][2], f);
        }
    fclose(f);
}

/* called for accesses to io ports */
static uint32_t g364fb_ctrl_readb(void *opaque, target_phys_addr_t addr)
{
    //G364State *s = opaque;
    uint32_t val;

    addr &= 0xffff;

    switch (addr) {
        default:
#ifdef DEBUG_G364
            printf("g364fb/ctrl: invalid read at [" TARGET_FMT_lx "]\n", addr);
#endif
            val = 0;
            break;
    }

#ifdef DEBUG_G364
    printf("g364fb/ctrl: read 0x%02x at [" TARGET_FMT_lx "]\n", val, addr);
#endif

    return val;
}

static uint32_t g364fb_ctrl_readw(void *opaque, target_phys_addr_t addr)
{
    uint32_t v;
    v = g364fb_ctrl_readb(opaque, addr);
    v |= g364fb_ctrl_readb(opaque, addr + 1) << 8;
    return v;
}

static uint32_t g364fb_ctrl_readl(void *opaque, target_phys_addr_t addr)
{
    uint32_t v;
    v = g364fb_ctrl_readb(opaque, addr);
    v |= g364fb_ctrl_readb(opaque, addr + 1) << 8;
    v |= g364fb_ctrl_readb(opaque, addr + 2) << 16;
    v |= g364fb_ctrl_readb(opaque, addr + 3) << 24;
    return v;
}

static void g364fb_ctrl_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
{
    G364State *s = opaque;

    addr &= 0xffff;

#ifdef DEBUG_G364
    printf("g364fb/ctrl: write 0x%02x at [" TARGET_FMT_lx "]\n", val, addr);
#endif

    if (addr < 0x0800) {
        /* color palette */
        int idx = addr >> 3;
        int c = addr & 7;
        if (c < 3)
            s->palette[idx][c] = (uint8_t)val;
    } else {
        switch (addr) {
            case REG_DISPLAYX:
                s->scr_width = (s->scr_width & 0xfffffc03) | (val << 2);
                break;
            case REG_DISPLAYX + 1:
                s->scr_width = (s->scr_width & 0xfffc03ff) | (val << 10);
                break;
            case REG_DISPLAYY:
                s->scr_height = (s->scr_height & 0xffffff80) | (val >> 1);
                break;
            case REG_DISPLAYY + 1:
                s->scr_height = (s->scr_height & 0xffff801f) | (val << 7);
                break;
            default:
#ifdef DEBUG_G364
                printf("g364fb/ctrl: invalid write of 0x%02x at [" TARGET_FMT_lx "]\n", val, addr);
#endif
                break;
        }
        if (s->scr_width && s->scr_height)
            qemu_console_resize(s->console, s->scr_width, s->scr_height);
    }
    s->graphic_mode = -1; /* force full update */
}

static void g364fb_ctrl_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
{
    g364fb_ctrl_writeb(opaque, addr, val & 0xff);
    g364fb_ctrl_writeb(opaque, addr + 1, (val >> 8) & 0xff);
}

static void g364fb_ctrl_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
{
    g364fb_ctrl_writeb(opaque, addr, val & 0xff);
    g364fb_ctrl_writeb(opaque, addr + 1, (val >> 8) & 0xff);
    g364fb_ctrl_writeb(opaque, addr + 2, (val >> 16) & 0xff);
    g364fb_ctrl_writeb(opaque, addr + 3, (val >> 24) & 0xff);
}

static CPUReadMemoryFunc *g364fb_ctrl_read[3] = {
    g364fb_ctrl_readb,
    g364fb_ctrl_readw,
    g364fb_ctrl_readl,
};

static CPUWriteMemoryFunc *g364fb_ctrl_write[3] = {
    g364fb_ctrl_writeb,
    g364fb_ctrl_writew,
    g364fb_ctrl_writel,
};

/* called for accesses to video ram */
static uint32_t g364fb_mem_readb(void *opaque, target_phys_addr_t addr)
{
    G364State *s = opaque;
    target_phys_addr_t relative_addr = addr - s->vram_base;

    return s->vram_buffer[relative_addr];
}

static uint32_t g364fb_mem_readw(void *opaque, target_phys_addr_t addr)
{
    uint32_t v;
    v = g364fb_mem_readb(opaque, addr);
    v |= g364fb_mem_readb(opaque, addr + 1) << 8;
    return v;
}

static uint32_t g364fb_mem_readl(void *opaque, target_phys_addr_t addr)
{
    uint32_t v;
    v = g364fb_mem_readb(opaque, addr);
    v |= g364fb_mem_readb(opaque, addr + 1) << 8;
    v |= g364fb_mem_readb(opaque, addr + 2) << 16;
    v |= g364fb_mem_readb(opaque, addr + 3) << 24;
    return v;
}

static void g364fb_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
{
    G364State *s = opaque;
    target_phys_addr_t relative_addr = addr - s->vram_base;

    s->vram_buffer[relative_addr] = val;
}

static void g364fb_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
{
    g364fb_mem_writeb(opaque, addr, val & 0xff);
    g364fb_mem_writeb(opaque, addr + 1, (val >> 8) & 0xff);
}

static void g364fb_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
{
    g364fb_mem_writeb(opaque, addr, val & 0xff);
    g364fb_mem_writeb(opaque, addr + 1, (val >> 8) & 0xff);
    g364fb_mem_writeb(opaque, addr + 2, (val >> 16) & 0xff);
    g364fb_mem_writeb(opaque, addr + 3, (val >> 24) & 0xff);
}

static CPUReadMemoryFunc *g364fb_mem_read[3] = {
    g364fb_mem_readb,
    g364fb_mem_readw,
    g364fb_mem_readl,
};

static CPUWriteMemoryFunc *g364fb_mem_write[3] = {
    g364fb_mem_writeb,
    g364fb_mem_writew,
    g364fb_mem_writel,
};

int g364fb_mm_init(DisplayState *ds,
                   int vram_size, int it_shift,
                   target_phys_addr_t vram_base, target_phys_addr_t ctrl_base)
{
    G364State *s;
    int io_vram, io_ctrl;

    s = qemu_mallocz(sizeof(G364State));
    if (!s)
        return -1;

    s->vram_size = vram_size;
    s->vram_buffer = qemu_mallocz(s->vram_size);

    qemu_register_reset(g364fb_reset, s);
    g364fb_reset(s);

    s->ds = ds;
    s->vram_base = vram_base;

    s->console = graphic_console_init(ds, g364fb_update_display,
                                      g364fb_invalidate_display,
                                      g364fb_screen_dump, NULL, s);

    io_vram = cpu_register_io_memory(0, g364fb_mem_read, g364fb_mem_write, s);
    cpu_register_physical_memory(s->vram_base, vram_size, io_vram);

    io_ctrl = cpu_register_io_memory(0, g364fb_ctrl_read, g364fb_ctrl_write, s);
    cpu_register_physical_memory(ctrl_base, 0x10000, io_ctrl);

    return 0;
}
Commit	Line	Data
1fc3d392 AJ	1	/*
	2	* QEMU G364 framebuffer Emulator.
	3	*
	4	* Copyright (c) 2007-2008 Hervé Poussineau
	5	*
	6	* This program is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU General Public License as
	8	* published by the Free Software Foundation; either version 2 of
	9	* the License, or (at your option) any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program; if not, write to the Free Software
	18	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	19	* MA 02111-1307 USA
	20	*/
	21
	22	#include "hw.h"
	23	#include "console.h"
	24	#include "pixel_ops.h"
	25
	26	//#define DEBUG_G364
	27
	28	typedef struct G364State {
	29	target_phys_addr_t vram_base;
	30	unsigned int vram_size;
	31	uint8_t *vram_buffer;
	32	uint32_t ctla;
	33	uint8_t palette[256][3];
	34	/* display refresh support */
	35	DisplayState *ds;
c60e08d9	36	QEMUConsole *console;
1fc3d392 AJ	37	int graphic_mode;
	38	uint32_t scr_width, scr_height; /* in pixels */
	39	uint32_t last_scr_width, last_scr_height; /* in pixels */
	40	} G364State;
	41
	42	/*
	43	* graphic modes
	44	*/
	45	#define BPP 8
	46	#define PIXEL_WIDTH 8
	47	#include "g364fb_template.h"
	48	#undef BPP
	49	#undef PIXEL_WIDTH
	50
	51	#define BPP 15
	52	#define PIXEL_WIDTH 16
	53	#include "g364fb_template.h"
	54	#undef BPP
	55	#undef PIXEL_WIDTH
	56
	57	#define BPP 16
	58	#define PIXEL_WIDTH 16
	59	#include "g364fb_template.h"
	60	#undef BPP
	61	#undef PIXEL_WIDTH
	62
	63	#define BPP 32
	64	#define PIXEL_WIDTH 32
	65	#include "g364fb_template.h"
	66	#undef BPP
	67	#undef PIXEL_WIDTH
	68
	69	#define REG_DISPLAYX 0x0918
	70	#define REG_DISPLAYY 0x0940
	71
	72	#define CTLA_FORCE_BLANK 0x400
	73
	74	static void g364fb_draw_graphic(G364State *s, int full_update)
	75	{
	76	if (s->scr_width == 0 \|\| s->scr_height == 0)
	77	return;
1fc3d392 AJ	78
	79	switch (s->ds->depth) {
	80	case 8:
	81	g364fb_draw_graphic8(s, full_update);
	82	break;
	83	case 15:
	84	g364fb_draw_graphic15(s, full_update);
	85	break;
	86	case 16:
	87	g364fb_draw_graphic16(s, full_update);
	88	break;
	89	case 32:
	90	g364fb_draw_graphic32(s, full_update);
	91	break;
	92	default:
	93	printf("g364fb: unknown depth %d\n", s->ds->depth);
	94	return;
	95	}
	96
	97	dpy_update(s->ds, 0, 0, s->last_scr_width, s->last_scr_height);
	98	}
	99
	100	static void g364fb_draw_blank(G364State *s, int full_update)
	101	{
	102	int i, w;
	103	uint8_t *d;
	104
	105	if (!full_update)
	106	return;
	107	if (s->last_scr_width <= 0 \|\| s->last_scr_height <= 0)
	108	return;
	109
	110	w = s->last_scr_width * ((s->ds->depth + 7) >> 3);
	111	d = s->ds->data;
	112	for(i = 0; i < s->last_scr_height; i++) {
	113	memset(d, 0, w);
	114	d += s->ds->linesize;
	115	}
	116	dpy_update(s->ds, 0, 0,
	117	s->last_scr_width, s->last_scr_height);
	118	}
	119
	120	#define GMODE_GRAPH 0
	121	#define GMODE_BLANK 1
	122
	123	static void g364fb_update_display(void *opaque)
	124	{
	125	G364State *s = opaque;
	126	int full_update, graphic_mode;
	127
	128	if (s->ctla & CTLA_FORCE_BLANK)
	129	graphic_mode = GMODE_BLANK;
	130	else
	131	graphic_mode = GMODE_GRAPH;
	132	full_update = 0;
	133	if (graphic_mode != s->graphic_mode) {
	134	s->graphic_mode = graphic_mode;
	135	full_update = 1;
	136	}
	137	switch(graphic_mode) {
	138	case GMODE_GRAPH:
	139	g364fb_draw_graphic(s, full_update);
	140	break;
	141	case GMODE_BLANK:
142	default:
143	g364fb_draw_blank(s, full_update);
144	break;
145	}
146	}
147
148	/* force a full display refresh */
149	static void g364fb_invalidate_display(void *opaque)
150	{
151	G364State *s = opaque;
152	s->graphic_mode = -1; /* force full update */
153	}
154
155	static void g364fb_reset(void *opaque)
156	{
157	G364State *s = opaque;
158
159	memset(s->palette, 0, sizeof(s->palette));
160	s->scr_width = s->scr_height = 0;
161	s->last_scr_width = s->last_scr_height = 0;
162	memset(s->vram_buffer, 0, s->vram_size);
163	s->graphic_mode = -1; /* force full update */
164	}
165
166	static void g364fb_screen_dump(void opaque, const char filename)
167	{
168	G364State *s = opaque;
169	int y, x;
170	uint8_t index;
171	uint8_t *data_buffer;
172	FILE *f;
173
174	f = fopen(filename, "wb");
175	if (!f)
176	return;
177
178	data_buffer = s->vram_buffer;
179	fprintf(f, "P6\n%d %d\n%d\n",
180	s->scr_width, s->scr_height, 255);
181	for(y = 0; y < s->scr_height; y++)
182	for(x = 0; x < s->scr_width; x++, data_buffer++) {
183	index = *data_buffer;
184	fputc(s->palette[index][0], f);
185	fputc(s->palette[index][1], f);
186	fputc(s->palette[index][2], f);
187	}
188	fclose(f);
189	}
190
191	/* called for accesses to io ports */
192	static uint32_t g364fb_ctrl_readb(void *opaque, target_phys_addr_t addr)
193	{
194	//G364State *s = opaque;
195	uint32_t val;
196
197	addr &= 0xffff;
198
199	switch (addr) {
200	default:
201	#ifdef DEBUG_G364
202	printf("g364fb/ctrl: invalid read at [" TARGET_FMT_lx "]\n", addr);
203	#endif
204	val = 0;
205	break;
206	}
207
208	#ifdef DEBUG_G364
209	printf("g364fb/ctrl: read 0x%02x at [" TARGET_FMT_lx "]\n", val, addr);
210	#endif
211
212	return val;
213	}
214
215	static uint32_t g364fb_ctrl_readw(void *opaque, target_phys_addr_t addr)
216	{
217	uint32_t v;
218	v = g364fb_ctrl_readb(opaque, addr);
219	v \|= g364fb_ctrl_readb(opaque, addr + 1) << 8;
220	return v;
221	}
222
223	static uint32_t g364fb_ctrl_readl(void *opaque, target_phys_addr_t addr)
224	{
225	uint32_t v;
226	v = g364fb_ctrl_readb(opaque, addr);
227	v \|= g364fb_ctrl_readb(opaque, addr + 1) << 8;
228	v \|= g364fb_ctrl_readb(opaque, addr + 2) << 16;
229	v \|= g364fb_ctrl_readb(opaque, addr + 3) << 24;
230	return v;
231	}
232
233	static void g364fb_ctrl_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
234	{
235	G364State *s = opaque;
236
237	addr &= 0xffff;
238
239	#ifdef DEBUG_G364
240	printf("g364fb/ctrl: write 0x%02x at [" TARGET_FMT_lx "]\n", val, addr);
241	#endif
242
243	if (addr < 0x0800) {
244	/* color palette */
245	int idx = addr >> 3;
246	int c = addr & 7;
247	if (c < 3)
248	s->palette[idx][c] = (uint8_t)val;
249	} else {
250	switch (addr) {
251	case REG_DISPLAYX:
252	s->scr_width = (s->scr_width & 0xfffffc03) \| (val << 2);
253	break;
254	case REG_DISPLAYX + 1:
255	s->scr_width = (s->scr_width & 0xfffc03ff) \| (val << 10);
256	break;
257	case REG_DISPLAYY:
258	s->scr_height = (s->scr_height & 0xffffff80) \| (val >> 1);
259	break;
260	case REG_DISPLAYY + 1:
261	s->scr_height = (s->scr_height & 0xffff801f) \| (val << 7);
262	break;
263	default:
264	#ifdef DEBUG_G364
265	printf("g364fb/ctrl: invalid write of 0x%02x at [" TARGET_FMT_lx "]\n", val, addr);
266	#endif
267	break;
268	}
c60e08d9 PB	269	if (s->scr_width && s->scr_height)
c60e08d9 PB	270	qemu_console_resize(s->console, s->scr_width, s->scr_height);
1fc3d392	271	}
c60e08d9	272	s->graphic_mode = -1; /* force full update */
1fc3d392 AJ	273	}
	274
	275	static void g364fb_ctrl_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
	276	{
	277	g364fb_ctrl_writeb(opaque, addr, val & 0xff);
	278	g364fb_ctrl_writeb(opaque, addr + 1, (val >> 8) & 0xff);
	279	}
	280
	281	static void g364fb_ctrl_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
	282	{
	283	g364fb_ctrl_writeb(opaque, addr, val & 0xff);
	284	g364fb_ctrl_writeb(opaque, addr + 1, (val >> 8) & 0xff);
	285	g364fb_ctrl_writeb(opaque, addr + 2, (val >> 16) & 0xff);
	286	g364fb_ctrl_writeb(opaque, addr + 3, (val >> 24) & 0xff);
	287	}
	288
	289	static CPUReadMemoryFunc *g364fb_ctrl_read[3] = {
	290	g364fb_ctrl_readb,
	291	g364fb_ctrl_readw,
	292	g364fb_ctrl_readl,
	293	};
	294
	295	static CPUWriteMemoryFunc *g364fb_ctrl_write[3] = {
	296	g364fb_ctrl_writeb,
	297	g364fb_ctrl_writew,
	298	g364fb_ctrl_writel,
	299	};
	300
	301	/* called for accesses to video ram */
	302	static uint32_t g364fb_mem_readb(void *opaque, target_phys_addr_t addr)
	303	{
	304	G364State *s = opaque;
	305	target_phys_addr_t relative_addr = addr - s->vram_base;
	306
	307	return s->vram_buffer[relative_addr];
	308	}
	309
	310	static uint32_t g364fb_mem_readw(void *opaque, target_phys_addr_t addr)
	311	{
	312	uint32_t v;
	313	v = g364fb_mem_readb(opaque, addr);
	314	v \|= g364fb_mem_readb(opaque, addr + 1) << 8;
	315	return v;
	316	}
	317
	318	static uint32_t g364fb_mem_readl(void *opaque, target_phys_addr_t addr)
	319	{
	320	uint32_t v;
	321	v = g364fb_mem_readb(opaque, addr);
	322	v \|= g364fb_mem_readb(opaque, addr + 1) << 8;
	323	v \|= g364fb_mem_readb(opaque, addr + 2) << 16;
	324	v \|= g364fb_mem_readb(opaque, addr + 3) << 24;
	325	return v;
	326	}
	327
	328	static void g364fb_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
	329	{
	330	G364State *s = opaque;
	331	target_phys_addr_t relative_addr = addr - s->vram_base;
	332
	333	s->vram_buffer[relative_addr] = val;
	334	}
	335
	336	static void g364fb_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
337	{
338	g364fb_mem_writeb(opaque, addr, val & 0xff);
339	g364fb_mem_writeb(opaque, addr + 1, (val >> 8) & 0xff);
340	}
341
342	static void g364fb_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
343	{
344	g364fb_mem_writeb(opaque, addr, val & 0xff);
345	g364fb_mem_writeb(opaque, addr + 1, (val >> 8) & 0xff);
346	g364fb_mem_writeb(opaque, addr + 2, (val >> 16) & 0xff);
347	g364fb_mem_writeb(opaque, addr + 3, (val >> 24) & 0xff);
348	}
349
350	static CPUReadMemoryFunc *g364fb_mem_read[3] = {
351	g364fb_mem_readb,
352	g364fb_mem_readw,
353	g364fb_mem_readl,
354	};
355
356	static CPUWriteMemoryFunc *g364fb_mem_write[3] = {
357	g364fb_mem_writeb,
358	g364fb_mem_writew,
359	g364fb_mem_writel,
360	};
361
362	int g364fb_mm_init(DisplayState *ds,
363	int vram_size, int it_shift,
364	target_phys_addr_t vram_base, target_phys_addr_t ctrl_base)
365	{
366	G364State *s;
367	int io_vram, io_ctrl;
368
369	s = qemu_mallocz(sizeof(G364State));
370	if (!s)
371	return -1;
372
373	s->vram_size = vram_size;
374	s->vram_buffer = qemu_mallocz(s->vram_size);
375
376	qemu_register_reset(g364fb_reset, s);
377	g364fb_reset(s);
378
379	s->ds = ds;
380	s->vram_base = vram_base;
381
c60e08d9 PB	382	s->console = graphic_console_init(ds, g364fb_update_display,
	383	g364fb_invalidate_display,
	384	g364fb_screen_dump, NULL, s);
1fc3d392 AJ	385
	386	io_vram = cpu_register_io_memory(0, g364fb_mem_read, g364fb_mem_write, s);
	387	cpu_register_physical_memory(s->vram_base, vram_size, io_vram);
	388
	389	io_ctrl = cpu_register_io_memory(0, g364fb_ctrl_read, g364fb_ctrl_write, s);
	390	cpu_register_physical_memory(ctrl_base, 0x10000, io_ctrl);
	391
	392	return 0;
	393	}