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Commit | Line | Data |
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ec82026c GH |
1 | /* |
2 | * QEMU IDE Emulation: ISA Bus support. | |
3 | * | |
4 | * Copyright (c) 2003 Fabrice Bellard | |
5 | * Copyright (c) 2006 Openedhand Ltd. | |
6 | * | |
7 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
8 | * of this software and associated documentation files (the "Software"), to deal | |
9 | * in the Software without restriction, including without limitation the rights | |
10 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
11 | * copies of the Software, and to permit persons to whom the Software is | |
12 | * furnished to do so, subject to the following conditions: | |
13 | * | |
14 | * The above copyright notice and this permission notice shall be included in | |
15 | * all copies or substantial portions of the Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
22 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
23 | * THE SOFTWARE. | |
24 | */ | |
53239262 | 25 | #include "qemu/osdep.h" |
a9c94277 MA |
26 | #include "hw/hw.h" |
27 | #include "hw/i386/pc.h" | |
28 | #include "hw/isa/isa.h" | |
4be74634 | 29 | #include "sysemu/block-backend.h" |
9c17d615 | 30 | #include "sysemu/dma.h" |
59f2a787 | 31 | |
a9c94277 | 32 | #include "hw/ide/internal.h" |
ec82026c GH |
33 | |
34 | /***********************************************************/ | |
35 | /* ISA IDE definitions */ | |
36 | ||
2f12688b AF |
37 | #define TYPE_ISA_IDE "isa-ide" |
38 | #define ISA_IDE(obj) OBJECT_CHECK(ISAIDEState, (obj), TYPE_ISA_IDE) | |
39 | ||
cebbe6d4 | 40 | typedef struct ISAIDEState { |
2f12688b AF |
41 | ISADevice parent_obj; |
42 | ||
1f850f10 | 43 | IDEBus bus; |
dea21e97 GH |
44 | uint32_t iobase; |
45 | uint32_t iobase2; | |
46 | uint32_t isairq; | |
47 | qemu_irq irq; | |
cebbe6d4 GH |
48 | } ISAIDEState; |
49 | ||
4a643563 BS |
50 | static void isa_ide_reset(DeviceState *d) |
51 | { | |
2f12688b | 52 | ISAIDEState *s = ISA_IDE(d); |
4a643563 BS |
53 | |
54 | ide_bus_reset(&s->bus); | |
55 | } | |
56 | ||
200ab5e2 JQ |
57 | static const VMStateDescription vmstate_ide_isa = { |
58 | .name = "isa-ide", | |
59 | .version_id = 3, | |
60 | .minimum_version_id = 0, | |
d49805ae | 61 | .fields = (VMStateField[]) { |
200ab5e2 JQ |
62 | VMSTATE_IDE_BUS(bus, ISAIDEState), |
63 | VMSTATE_IDE_DRIVES(bus.ifs, ISAIDEState), | |
64 | VMSTATE_END_OF_LIST() | |
65 | } | |
66 | }; | |
cebbe6d4 | 67 | |
db895a1e | 68 | static void isa_ide_realizefn(DeviceState *dev, Error **errp) |
ec82026c | 69 | { |
db895a1e | 70 | ISADevice *isadev = ISA_DEVICE(dev); |
2f12688b | 71 | ISAIDEState *s = ISA_IDE(dev); |
dea21e97 | 72 | |
c6baf942 | 73 | ide_bus_new(&s->bus, sizeof(s->bus), dev, 0, 2); |
db895a1e AF |
74 | ide_init_ioport(&s->bus, isadev, s->iobase, s->iobase2); |
75 | isa_init_irq(isadev, &s->irq, s->isairq); | |
57234ee4 | 76 | ide_init2(&s->bus, s->irq); |
db895a1e | 77 | vmstate_register(dev, 0, &vmstate_ide_isa, s); |
d32c76b3 PB |
78 | ide_register_restart_cb(&s->bus); |
79 | } | |
dea21e97 | 80 | |
48a18b3c | 81 | ISADevice *isa_ide_init(ISABus *bus, int iobase, int iobase2, int isairq, |
57c88866 | 82 | DriveInfo *hd0, DriveInfo *hd1) |
dea21e97 | 83 | { |
2f12688b AF |
84 | DeviceState *dev; |
85 | ISADevice *isadev; | |
cebbe6d4 | 86 | ISAIDEState *s; |
ec82026c | 87 | |
2f12688b AF |
88 | isadev = isa_create(bus, TYPE_ISA_IDE); |
89 | dev = DEVICE(isadev); | |
90 | qdev_prop_set_uint32(dev, "iobase", iobase); | |
91 | qdev_prop_set_uint32(dev, "iobase2", iobase2); | |
92 | qdev_prop_set_uint32(dev, "irq", isairq); | |
e25b89e5 | 93 | qdev_init_nofail(dev); |
ec82026c | 94 | |
2f12688b AF |
95 | s = ISA_IDE(dev); |
96 | if (hd0) { | |
1f850f10 | 97 | ide_create_drive(&s->bus, 0, hd0); |
2f12688b AF |
98 | } |
99 | if (hd1) { | |
1f850f10 | 100 | ide_create_drive(&s->bus, 1, hd1); |
2f12688b AF |
101 | } |
102 | return isadev; | |
dea21e97 GH |
103 | } |
104 | ||
39bffca2 | 105 | static Property isa_ide_properties[] = { |
c7bcc85d PB |
106 | DEFINE_PROP_UINT32("iobase", ISAIDEState, iobase, 0x1f0), |
107 | DEFINE_PROP_UINT32("iobase2", ISAIDEState, iobase2, 0x3f6), | |
39bffca2 AL |
108 | DEFINE_PROP_UINT32("irq", ISAIDEState, isairq, 14), |
109 | DEFINE_PROP_END_OF_LIST(), | |
110 | }; | |
111 | ||
8f04ee08 AL |
112 | static void isa_ide_class_initfn(ObjectClass *klass, void *data) |
113 | { | |
39bffca2 | 114 | DeviceClass *dc = DEVICE_CLASS(klass); |
db895a1e AF |
115 | |
116 | dc->realize = isa_ide_realizefn; | |
39bffca2 AL |
117 | dc->fw_name = "ide"; |
118 | dc->reset = isa_ide_reset; | |
119 | dc->props = isa_ide_properties; | |
125ee0ed | 120 | set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); |
8f04ee08 AL |
121 | } |
122 | ||
8c43a6f0 | 123 | static const TypeInfo isa_ide_info = { |
2f12688b | 124 | .name = TYPE_ISA_IDE, |
39bffca2 AL |
125 | .parent = TYPE_ISA_DEVICE, |
126 | .instance_size = sizeof(ISAIDEState), | |
127 | .class_init = isa_ide_class_initfn, | |
dea21e97 GH |
128 | }; |
129 | ||
83f7d43a | 130 | static void isa_ide_register_types(void) |
dea21e97 | 131 | { |
39bffca2 | 132 | type_register_static(&isa_ide_info); |
ec82026c | 133 | } |
dea21e97 | 134 | |
83f7d43a | 135 | type_init(isa_ide_register_types) |