[qemu.git] / hw / etraxfs_pic.c

/*
 * QEMU ETRAX Interrupt Controller.
 *
 * Copyright (c) 2008 Edgar E. Iglesias, Axis Communications AB.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */

#include <stdio.h>
#include "hw.h"
#include "etraxfs.h"

#define D(x)

struct fs_pic_state_t
{
	CPUState *env;

	uint32_t rw_mask;
	/* Active interrupt lines.  */
	uint32_t r_vect;
	/* Active lines, gated through the mask.  */
	uint32_t r_masked_vect;
	uint32_t r_nmi;
	uint32_t r_guru;
};

static void pic_update(struct fs_pic_state_t *fs)
{	
	CPUState *env = fs->env;
	int i;
	uint32_t vector = 0;

	fs->r_masked_vect = fs->r_vect & fs->rw_mask;

	/* The ETRAX interrupt controller signals interrupts to teh core
	   through an interrupt request wire and an irq vector bus. If 
	   multiple interrupts are simultaneously active it chooses vector 
	   0x30 and lets the sw choose the priorities.  */
	if (fs->r_masked_vect) {
		uint32_t mv = fs->r_masked_vect;
		for (i = 0; i < 31; i++) {
			if (mv & 1) {
				vector = 0x31 + i;
				/* Check for multiple interrupts.  */
				if (mv > 1)
					vector = 0x30;
				break;
			}
			mv >>= 1;
		}
		if (vector) {
			env->interrupt_vector = vector;
			D(printf("%s vector=%x\n", __func__, vector));
			cpu_interrupt(env, CPU_INTERRUPT_HARD);
		}
	} else {
		env->interrupt_vector = 0;
		cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
		D(printf("%s reset irqs\n", __func__));
	}
}

static uint32_t pic_readl (void *opaque, target_phys_addr_t addr)
{
	struct fs_pic_state_t *fs = opaque;
	uint32_t rval;

	switch (addr)
	{
		case 0x0: 
			rval = fs->rw_mask;
			break;
		case 0x4: 
			rval = fs->r_vect;
			break;
		case 0x8: 
			rval = fs->r_masked_vect;
			break;
		case 0xc: 
			rval = fs->r_nmi;
			break;
		case 0x10: 
			rval = fs->r_guru;
			break;
		default:
			cpu_abort(fs->env, "invalid PIC register.\n");
			break;

	}
	D(printf("%s %x=%x\n", __func__, addr, rval));
	return rval;
}

static void
pic_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
{
	struct fs_pic_state_t *fs = opaque;
	D(printf("%s addr=%x val=%x\n", __func__, addr, value));
	switch (addr) 
	{
		case 0x0: 
			fs->rw_mask = value;
			pic_update(fs);
			break;
		default:
			cpu_abort(fs->env, "invalid PIC register.\n");
			break;
	}
}

static CPUReadMemoryFunc *pic_read[] = {
	NULL, NULL,
	&pic_readl,
};

static CPUWriteMemoryFunc *pic_write[] = {
	NULL, NULL,
	&pic_writel,
};

void pic_info(void)
{
}

void irq_info(void)
{
}

static void irq_handler(void *opaque, int irq, int level)
{	
	struct fs_pic_state_t *fs = (void *)opaque;

	D(printf("%s irq=%d level=%d mask=%x v=%x mv=%x\n", 
		 __func__, irq, level,
		 fs->rw_mask, fs->r_vect, fs->r_masked_vect));

	irq -= 1;
	fs->r_vect &= ~(1 << irq);
	fs->r_vect |= (!!level << irq);

	pic_update(fs);
}

static void nmi_handler(void *opaque, int irq, int level)
{	
	struct fs_pic_state_t *fs = (void *)opaque;
	CPUState *env = fs->env;
	uint32_t mask;

	mask = 1 << irq;
	if (level)
		fs->r_nmi |= mask;
	else
		fs->r_nmi &= ~mask;

	if (fs->r_nmi)
		cpu_interrupt(env, CPU_INTERRUPT_NMI);
	else
		cpu_reset_interrupt(env, CPU_INTERRUPT_NMI);
}

static void guru_handler(void *opaque, int irq, int level)
{	
	struct fs_pic_state_t *fs = (void *)opaque;
	CPUState *env = fs->env;
	cpu_abort(env, "%s unsupported exception\n", __func__);

}

struct etraxfs_pic *etraxfs_pic_init(CPUState *env, target_phys_addr_t base)
{
	struct fs_pic_state_t *fs = NULL;
	struct etraxfs_pic *pic = NULL;
	int intr_vect_regs;

	pic = qemu_mallocz(sizeof *pic);
	pic->internal = fs = qemu_mallocz(sizeof *fs);
	if (!fs || !pic)
		goto err;

	fs->env = env;
	pic->irq = qemu_allocate_irqs(irq_handler, fs, 30);
	pic->nmi = qemu_allocate_irqs(nmi_handler, fs, 2);
	pic->guru = qemu_allocate_irqs(guru_handler, fs, 1);

	intr_vect_regs = cpu_register_io_memory(0, pic_read, pic_write, fs);
	cpu_register_physical_memory(base, 0x14, intr_vect_regs);

	return pic;
  err:
	free(pic);
	free(fs);
	return NULL;
}
Commit	Line	Data
e62b5b13 EI	1	/*
	2	* QEMU ETRAX Interrupt Controller.
	3	*
	4	* Copyright (c) 2008 Edgar E. Iglesias, Axis Communications AB.
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
	24
	25	#include <stdio.h>
	26	#include "hw.h"
5ef98b47	27	#include "etraxfs.h"
e62b5b13 EI	28
	29	#define D(x)
	30
	31	struct fs_pic_state_t
	32	{
	33	CPUState *env;
e62b5b13 EI	34
	35	uint32_t rw_mask;
	36	/* Active interrupt lines. */
	37	uint32_t r_vect;
	38	/* Active lines, gated through the mask. */
	39	uint32_t r_masked_vect;
	40	uint32_t r_nmi;
	41	uint32_t r_guru;
	42	};
	43
70ea255d EI	44	static void pic_update(struct fs_pic_state_t *fs)
	45	{
	46	CPUState *env = fs->env;
	47	int i;
	48	uint32_t vector = 0;
	49
	50	fs->r_masked_vect = fs->r_vect & fs->rw_mask;
	51
	52	/* The ETRAX interrupt controller signals interrupts to teh core
	53	through an interrupt request wire and an irq vector bus. If
	54	multiple interrupts are simultaneously active it chooses vector
	55	0x30 and lets the sw choose the priorities. */
	56	if (fs->r_masked_vect) {
	57	uint32_t mv = fs->r_masked_vect;
	58	for (i = 0; i < 31; i++) {
	59	if (mv & 1) {
	60	vector = 0x31 + i;
	61	/* Check for multiple interrupts. */
	62	if (mv > 1)
	63	vector = 0x30;
	64	break;
	65	}
	66	mv >>= 1;
	67	}
	68	if (vector) {
	69	env->interrupt_vector = vector;
	70	D(printf("%s vector=%x\n", __func__, vector));
	71	cpu_interrupt(env, CPU_INTERRUPT_HARD);
	72	}
	73	} else {
	74	env->interrupt_vector = 0;
	75	cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
	76	D(printf("%s reset irqs\n", __func__));
	77	}
e62b5b13 EI	78	}
	79
	80	static uint32_t pic_readl (void *opaque, target_phys_addr_t addr)
	81	{
	82	struct fs_pic_state_t *fs = opaque;
	83	uint32_t rval;
	84
e62b5b13 EI	85	switch (addr)
	86	{
	87	case 0x0:
	88	rval = fs->rw_mask;
	89	break;
	90	case 0x4:
	91	rval = fs->r_vect;
	92	break;
	93	case 0x8:
	94	rval = fs->r_masked_vect;
	95	break;
	96	case 0xc:
	97	rval = fs->r_nmi;
	98	break;
	99	case 0x10:
	100	rval = fs->r_guru;
	101	break;
	102	default:
	103	cpu_abort(fs->env, "invalid PIC register.\n");
	104	break;
	105
	106	}
	107	D(printf("%s %x=%x\n", __func__, addr, rval));
	108	return rval;
	109	}
	110
e62b5b13 EI	111	static void
	112	pic_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
	113	{
	114	struct fs_pic_state_t *fs = opaque;
	115	D(printf("%s addr=%x val=%x\n", __func__, addr, value));
e62b5b13 EI	116	switch (addr)
	117	{
	118	case 0x0:
	119	fs->rw_mask = value;
70ea255d	120	pic_update(fs);
e62b5b13 EI	121	break;
	122	default:
	123	cpu_abort(fs->env, "invalid PIC register.\n");
	124	break;
	125	}
	126	}
	127
	128	static CPUReadMemoryFunc *pic_read[] = {
70ea255d	129	NULL, NULL,
e62b5b13 EI	130	&pic_readl,
	131	};
	132
	133	static CPUWriteMemoryFunc *pic_write[] = {
70ea255d	134	NULL, NULL,
e62b5b13 EI	135	&pic_writel,
	136	};
	137
	138	void pic_info(void)
	139	{
	140	}
	141
	142	void irq_info(void)
	143	{
	144	}
	145
5ef98b47	146	static void irq_handler(void *opaque, int irq, int level)
e62b5b13 EI	147	{
e62b5b13 EI	148	struct fs_pic_state_t fs = (void )opaque;
e62b5b13 EI	149
	150	D(printf("%s irq=%d level=%d mask=%x v=%x mv=%x\n",
	151	__func__, irq, level,
	152	fs->rw_mask, fs->r_vect, fs->r_masked_vect));
	153
48318011	154	irq -= 1;
e62b5b13 EI	155	fs->r_vect &= ~(1 << irq);
e62b5b13 EI	156	fs->r_vect \|= (!!level << irq);
e62b5b13	157
70ea255d	158	pic_update(fs);
e62b5b13 EI	159	}
e62b5b13 EI	160
5ef98b47 EI	161	static void nmi_handler(void *opaque, int irq, int level)
	162	{
	163	struct fs_pic_state_t fs = (void )opaque;
	164	CPUState *env = fs->env;
	165	uint32_t mask;
	166
	167	mask = 1 << irq;
	168	if (level)
	169	fs->r_nmi \|= mask;
	170	else
	171	fs->r_nmi &= ~mask;
	172
	173	if (fs->r_nmi)
	174	cpu_interrupt(env, CPU_INTERRUPT_NMI);
	175	else
	176	cpu_reset_interrupt(env, CPU_INTERRUPT_NMI);
	177	}
	178
	179	static void guru_handler(void *opaque, int irq, int level)
	180	{
	181	struct fs_pic_state_t fs = (void )opaque;
	182	CPUState *env = fs->env;
	183	cpu_abort(env, "%s unsupported exception\n", __func__);
	184
	185	}
	186
5ef98b47	187	struct etraxfs_pic etraxfs_pic_init(CPUState env, target_phys_addr_t base)
e62b5b13	188	{
5ef98b47 EI	189	struct fs_pic_state_t *fs = NULL;
5ef98b47 EI	190	struct etraxfs_pic *pic = NULL;
e62b5b13 EI	191	int intr_vect_regs;
e62b5b13 EI	192
5ef98b47 EI	193	pic = qemu_mallocz(sizeof *pic);
	194	pic->internal = fs = qemu_mallocz(sizeof *fs);
	195	if (!fs \|\| !pic)
	196	goto err;
e62b5b13	197
5ef98b47 EI	198	fs->env = env;
	199	pic->irq = qemu_allocate_irqs(irq_handler, fs, 30);
	200	pic->nmi = qemu_allocate_irqs(nmi_handler, fs, 2);
	201	pic->guru = qemu_allocate_irqs(guru_handler, fs, 1);
e62b5b13 EI	202
	203	intr_vect_regs = cpu_register_io_memory(0, pic_read, pic_write, fs);
	204	cpu_register_physical_memory(base, 0x14, intr_vect_regs);
e62b5b13 EI	205
e62b5b13 EI	206	return pic;
5ef98b47 EI	207	err:
	208	free(pic);
	209	free(fs);
	210	return NULL;
e62b5b13	211	}