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bf957284 PB |
1 | /* |
2 | * QEMU monitor | |
3 | * | |
4 | * Copyright (c) 2003-2004 Fabrice Bellard | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
0d75590d | 24 | #include "qemu/osdep.h" |
bf957284 PB |
25 | #include "cpu.h" |
26 | #include "monitor/monitor.h" | |
27 | #include "monitor/hmp-target.h" | |
28 | #include "hmp.h" | |
29 | ||
30 | static target_long monitor_get_ccr (const struct MonitorDef *md, int val) | |
31 | { | |
32 | CPUArchState *env = mon_get_cpu_env(); | |
33 | unsigned int u; | |
34 | int i; | |
35 | ||
36 | u = 0; | |
37 | for (i = 0; i < 8; i++) | |
38 | u |= env->crf[i] << (32 - (4 * (i + 1))); | |
39 | ||
40 | return u; | |
41 | } | |
42 | ||
bf957284 PB |
43 | static target_long monitor_get_decr (const struct MonitorDef *md, int val) |
44 | { | |
45 | CPUArchState *env = mon_get_cpu_env(); | |
46 | return cpu_ppc_load_decr(env); | |
47 | } | |
48 | ||
49 | static target_long monitor_get_tbu (const struct MonitorDef *md, int val) | |
50 | { | |
51 | CPUArchState *env = mon_get_cpu_env(); | |
52 | return cpu_ppc_load_tbu(env); | |
53 | } | |
54 | ||
55 | static target_long monitor_get_tbl (const struct MonitorDef *md, int val) | |
56 | { | |
57 | CPUArchState *env = mon_get_cpu_env(); | |
58 | return cpu_ppc_load_tbl(env); | |
59 | } | |
60 | ||
61 | void hmp_info_tlb(Monitor *mon, const QDict *qdict) | |
62 | { | |
63 | CPUArchState *env1 = mon_get_cpu_env(); | |
64 | ||
854e67fe TH |
65 | if (!env1) { |
66 | monitor_printf(mon, "No CPU available\n"); | |
67 | return; | |
68 | } | |
bf957284 PB |
69 | dump_mmu((FILE*)mon, (fprintf_function)monitor_printf, env1); |
70 | } | |
71 | ||
bf957284 | 72 | const MonitorDef monitor_defs[] = { |
bf957284 PB |
73 | { "fpscr", offsetof(CPUPPCState, fpscr) }, |
74 | /* Next instruction pointer */ | |
75 | { "nip|pc", offsetof(CPUPPCState, nip) }, | |
76 | { "lr", offsetof(CPUPPCState, lr) }, | |
77 | { "ctr", offsetof(CPUPPCState, ctr) }, | |
78 | { "decr", 0, &monitor_get_decr, }, | |
0a9516c2 | 79 | { "ccr|cr", 0, &monitor_get_ccr, }, |
bf957284 | 80 | /* Machine state register */ |
0a9516c2 AK |
81 | { "xer", offsetof(CPUPPCState, xer) }, |
82 | { "msr", offsetof(CPUPPCState, msr) }, | |
bf957284 PB |
83 | { "tbu", 0, &monitor_get_tbu, }, |
84 | { "tbl", 0, &monitor_get_tbl, }, | |
bf957284 PB |
85 | { NULL }, |
86 | }; | |
87 | ||
88 | const MonitorDef *target_monitor_defs(void) | |
89 | { | |
90 | return monitor_defs; | |
91 | } | |
0a9516c2 AK |
92 | |
93 | static int ppc_cpu_get_reg_num(const char *numstr, int maxnum, int *pregnum) | |
94 | { | |
95 | int regnum; | |
96 | char *endptr = NULL; | |
97 | ||
98 | if (!*numstr) { | |
99 | return false; | |
100 | } | |
101 | ||
102 | regnum = strtoul(numstr, &endptr, 10); | |
103 | if (*endptr || (regnum >= maxnum)) { | |
104 | return false; | |
105 | } | |
106 | *pregnum = regnum; | |
107 | ||
108 | return true; | |
109 | } | |
110 | ||
111 | int target_get_monitor_def(CPUState *cs, const char *name, uint64_t *pval) | |
112 | { | |
113 | int i, regnum; | |
114 | PowerPCCPU *cpu = POWERPC_CPU(cs); | |
115 | CPUPPCState *env = &cpu->env; | |
116 | ||
117 | /* General purpose registers */ | |
95a5befc | 118 | if ((qemu_tolower(name[0]) == 'r') && |
0a9516c2 AK |
119 | ppc_cpu_get_reg_num(name + 1, ARRAY_SIZE(env->gpr), ®num)) { |
120 | *pval = env->gpr[regnum]; | |
121 | return 0; | |
122 | } | |
123 | ||
124 | /* Floating point registers */ | |
95a5befc | 125 | if ((qemu_tolower(name[0]) == 'f') && |
0a9516c2 AK |
126 | ppc_cpu_get_reg_num(name + 1, ARRAY_SIZE(env->fpr), ®num)) { |
127 | *pval = env->fpr[regnum]; | |
128 | return 0; | |
129 | } | |
130 | ||
131 | /* Special purpose registers */ | |
132 | for (i = 0; i < ARRAY_SIZE(env->spr_cb); ++i) { | |
133 | ppc_spr_t *spr = &env->spr_cb[i]; | |
134 | ||
135 | if (spr->name && (strcasecmp(name, spr->name) == 0)) { | |
136 | *pval = env->spr[i]; | |
137 | return 0; | |
138 | } | |
139 | } | |
140 | ||
141 | /* Segment registers */ | |
142 | #if !defined(CONFIG_USER_ONLY) | |
143 | if ((strncasecmp(name, "sr", 2) == 0) && | |
144 | ppc_cpu_get_reg_num(name + 2, ARRAY_SIZE(env->sr), ®num)) { | |
145 | *pval = env->sr[regnum]; | |
146 | return 0; | |
147 | } | |
148 | #endif | |
149 | ||
150 | return -EINVAL; | |
151 | } |