[qemu.git] / hw / arm / pxa2xx_gpio.c

/*
 * Intel XScale PXA255/270 GPIO controller emulation.
 *
 * Copyright (c) 2006 Openedhand Ltd.
 * Written by Andrzej Zaborowski <[email protected]>
 *
 * This code is licensed under the GPL.
 */

#include "qemu/osdep.h"
#include "cpu.h"
#include "hw/hw.h"
#include "hw/sysbus.h"
#include "hw/arm/pxa.h"
#include "qemu/log.h"
#include "qemu/module.h"

#define PXA2XX_GPIO_BANKS	4

#define TYPE_PXA2XX_GPIO "pxa2xx-gpio"
#define PXA2XX_GPIO(obj) \
    OBJECT_CHECK(PXA2xxGPIOInfo, (obj), TYPE_PXA2XX_GPIO)

typedef struct PXA2xxGPIOInfo PXA2xxGPIOInfo;
struct PXA2xxGPIOInfo {
    /*< private >*/
    SysBusDevice parent_obj;
    /*< public >*/

    MemoryRegion iomem;
    qemu_irq irq0, irq1, irqX;
    int lines;
    int ncpu;
    ARMCPU *cpu;

    /* XXX: GNU C vectors are more suitable */
    uint32_t ilevel[PXA2XX_GPIO_BANKS];
    uint32_t olevel[PXA2XX_GPIO_BANKS];
    uint32_t dir[PXA2XX_GPIO_BANKS];
    uint32_t rising[PXA2XX_GPIO_BANKS];
    uint32_t falling[PXA2XX_GPIO_BANKS];
    uint32_t status[PXA2XX_GPIO_BANKS];
    uint32_t gafr[PXA2XX_GPIO_BANKS * 2];

    uint32_t prev_level[PXA2XX_GPIO_BANKS];
    qemu_irq handler[PXA2XX_GPIO_BANKS * 32];
    qemu_irq read_notify;
};

static struct {
    enum {
        GPIO_NONE,
        GPLR,
        GPSR,
        GPCR,
        GPDR,
        GRER,
        GFER,
        GEDR,
        GAFR_L,
        GAFR_U,
    } reg;
    int bank;
} pxa2xx_gpio_regs[0x200] = {
    [0 ... 0x1ff] = { GPIO_NONE, 0 },
#define PXA2XX_REG(reg, a0, a1, a2, a3)	\
    [a0] = { reg, 0 }, [a1] = { reg, 1 }, [a2] = { reg, 2 }, [a3] = { reg, 3 },

    PXA2XX_REG(GPLR, 0x000, 0x004, 0x008, 0x100)
    PXA2XX_REG(GPSR, 0x018, 0x01c, 0x020, 0x118)
    PXA2XX_REG(GPCR, 0x024, 0x028, 0x02c, 0x124)
    PXA2XX_REG(GPDR, 0x00c, 0x010, 0x014, 0x10c)
    PXA2XX_REG(GRER, 0x030, 0x034, 0x038, 0x130)
    PXA2XX_REG(GFER, 0x03c, 0x040, 0x044, 0x13c)
    PXA2XX_REG(GEDR, 0x048, 0x04c, 0x050, 0x148)
    PXA2XX_REG(GAFR_L, 0x054, 0x05c, 0x064, 0x06c)
    PXA2XX_REG(GAFR_U, 0x058, 0x060, 0x068, 0x070)
};

static void pxa2xx_gpio_irq_update(PXA2xxGPIOInfo *s)
{
    if (s->status[0] & (1 << 0))
        qemu_irq_raise(s->irq0);
    else
        qemu_irq_lower(s->irq0);

    if (s->status[0] & (1 << 1))
        qemu_irq_raise(s->irq1);
    else
        qemu_irq_lower(s->irq1);

    if ((s->status[0] & ~3) | s->status[1] | s->status[2] | s->status[3])
        qemu_irq_raise(s->irqX);
    else
        qemu_irq_lower(s->irqX);
}

/* Bitmap of pins used as standby and sleep wake-up sources.  */
static const int pxa2xx_gpio_wake[PXA2XX_GPIO_BANKS] = {
    0x8003fe1b, 0x002001fc, 0xec080000, 0x0012007f,
};

static void pxa2xx_gpio_set(void *opaque, int line, int level)
{
    PXA2xxGPIOInfo *s = (PXA2xxGPIOInfo *) opaque;
    CPUState *cpu = CPU(s->cpu);
    int bank;
    uint32_t mask;

    if (line >= s->lines) {
        printf("%s: No GPIO pin %i\n", __func__, line);
        return;
    }

    bank = line >> 5;
    mask = 1U << (line & 31);

    if (level) {
        s->status[bank] |= s->rising[bank] & mask &
                ~s->ilevel[bank] & ~s->dir[bank];
        s->ilevel[bank] |= mask;
    } else {
        s->status[bank] |= s->falling[bank] & mask &
                s->ilevel[bank] & ~s->dir[bank];
        s->ilevel[bank] &= ~mask;
    }

    if (s->status[bank] & mask)
        pxa2xx_gpio_irq_update(s);

    /* Wake-up GPIOs */
    if (cpu->halted && (mask & ~s->dir[bank] & pxa2xx_gpio_wake[bank])) {
        cpu_interrupt(cpu, CPU_INTERRUPT_EXITTB);
    }
}

static void pxa2xx_gpio_handler_update(PXA2xxGPIOInfo *s) {
    uint32_t level, diff;
    int i, bit, line;
    for (i = 0; i < PXA2XX_GPIO_BANKS; i ++) {
        level = s->olevel[i] & s->dir[i];

        for (diff = s->prev_level[i] ^ level; diff; diff ^= 1 << bit) {
            bit = ctz32(diff);
            line = bit + 32 * i;
            qemu_set_irq(s->handler[line], (level >> bit) & 1);
        }

        s->prev_level[i] = level;
    }
}

static uint64_t pxa2xx_gpio_read(void *opaque, hwaddr offset,
                                 unsigned size)
{
    PXA2xxGPIOInfo *s = (PXA2xxGPIOInfo *) opaque;
    uint32_t ret;
    int bank;
    if (offset >= 0x200)
        return 0;

    bank = pxa2xx_gpio_regs[offset].bank;
    switch (pxa2xx_gpio_regs[offset].reg) {
    case GPDR:		/* GPIO Pin-Direction registers */
        return s->dir[bank];

    case GPSR:		/* GPIO Pin-Output Set registers */
        qemu_log_mask(LOG_GUEST_ERROR,
                      "pxa2xx GPIO: read from write only register GPSR\n");
        return 0;

    case GPCR:		/* GPIO Pin-Output Clear registers */
        qemu_log_mask(LOG_GUEST_ERROR,
                      "pxa2xx GPIO: read from write only register GPCR\n");
        return 0;

    case GRER:		/* GPIO Rising-Edge Detect Enable registers */
        return s->rising[bank];

    case GFER:		/* GPIO Falling-Edge Detect Enable registers */
        return s->falling[bank];

    case GAFR_L:	/* GPIO Alternate Function registers */
        return s->gafr[bank * 2];

    case GAFR_U:	/* GPIO Alternate Function registers */
        return s->gafr[bank * 2 + 1];

    case GPLR:		/* GPIO Pin-Level registers */
        ret = (s->olevel[bank] & s->dir[bank]) |
                (s->ilevel[bank] & ~s->dir[bank]);
        qemu_irq_raise(s->read_notify);
        return ret;

    case GEDR:		/* GPIO Edge Detect Status registers */
        return s->status[bank];

    default:
        hw_error("%s: Bad offset " REG_FMT "\n", __func__, offset);
    }

    return 0;
}

static void pxa2xx_gpio_write(void *opaque, hwaddr offset,
                              uint64_t value, unsigned size)
{
    PXA2xxGPIOInfo *s = (PXA2xxGPIOInfo *) opaque;
    int bank;
    if (offset >= 0x200)
        return;

    bank = pxa2xx_gpio_regs[offset].bank;
    switch (pxa2xx_gpio_regs[offset].reg) {
    case GPDR:		/* GPIO Pin-Direction registers */
        s->dir[bank] = value;
        pxa2xx_gpio_handler_update(s);
        break;

    case GPSR:		/* GPIO Pin-Output Set registers */
        s->olevel[bank] |= value;
        pxa2xx_gpio_handler_update(s);
        break;

    case GPCR:		/* GPIO Pin-Output Clear registers */
        s->olevel[bank] &= ~value;
        pxa2xx_gpio_handler_update(s);
        break;

    case GRER:		/* GPIO Rising-Edge Detect Enable registers */
        s->rising[bank] = value;
        break;

    case GFER:		/* GPIO Falling-Edge Detect Enable registers */
        s->falling[bank] = value;
        break;

    case GAFR_L:	/* GPIO Alternate Function registers */
        s->gafr[bank * 2] = value;
        break;

    case GAFR_U:	/* GPIO Alternate Function registers */
        s->gafr[bank * 2 + 1] = value;
        break;

    case GEDR:		/* GPIO Edge Detect Status registers */
        s->status[bank] &= ~value;
        pxa2xx_gpio_irq_update(s);
        break;

    default:
        hw_error("%s: Bad offset " REG_FMT "\n", __func__, offset);
    }
}

static const MemoryRegionOps pxa_gpio_ops = {
    .read = pxa2xx_gpio_read,
    .write = pxa2xx_gpio_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
};

DeviceState *pxa2xx_gpio_init(hwaddr base,
                              ARMCPU *cpu, DeviceState *pic, int lines)
{
    CPUState *cs = CPU(cpu);
    DeviceState *dev;

    dev = qdev_create(NULL, TYPE_PXA2XX_GPIO);
    qdev_prop_set_int32(dev, "lines", lines);
    qdev_prop_set_int32(dev, "ncpu", cs->cpu_index);
    qdev_init_nofail(dev);

    sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
    sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0,
                    qdev_get_gpio_in(pic, PXA2XX_PIC_GPIO_0));
    sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1,
                    qdev_get_gpio_in(pic, PXA2XX_PIC_GPIO_1));
    sysbus_connect_irq(SYS_BUS_DEVICE(dev), 2,
                    qdev_get_gpio_in(pic, PXA2XX_PIC_GPIO_X));

    return dev;
}

static void pxa2xx_gpio_initfn(Object *obj)
{
    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
    DeviceState *dev = DEVICE(sbd);
    PXA2xxGPIOInfo *s = PXA2XX_GPIO(dev);

    memory_region_init_io(&s->iomem, obj, &pxa_gpio_ops,
                          s, "pxa2xx-gpio", 0x1000);
    sysbus_init_mmio(sbd, &s->iomem);
    sysbus_init_irq(sbd, &s->irq0);
    sysbus_init_irq(sbd, &s->irq1);
    sysbus_init_irq(sbd, &s->irqX);
}

static void pxa2xx_gpio_realize(DeviceState *dev, Error **errp)
{
    PXA2xxGPIOInfo *s = PXA2XX_GPIO(dev);

    s->cpu = ARM_CPU(qemu_get_cpu(s->ncpu));

    qdev_init_gpio_in(dev, pxa2xx_gpio_set, s->lines);
    qdev_init_gpio_out(dev, s->handler, s->lines);
}

/*
 * Registers a callback to notify on GPLR reads.  This normally
 * shouldn't be needed but it is used for the hack on Spitz machines.
 */
void pxa2xx_gpio_read_notifier(DeviceState *dev, qemu_irq handler)
{
    PXA2xxGPIOInfo *s = PXA2XX_GPIO(dev);

    s->read_notify = handler;
}

static const VMStateDescription vmstate_pxa2xx_gpio_regs = {
    .name = "pxa2xx-gpio",
    .version_id = 1,
    .minimum_version_id = 1,
    .fields = (VMStateField[]) {
        VMSTATE_UINT32_ARRAY(ilevel, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
        VMSTATE_UINT32_ARRAY(olevel, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
        VMSTATE_UINT32_ARRAY(dir, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
        VMSTATE_UINT32_ARRAY(rising, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
        VMSTATE_UINT32_ARRAY(falling, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
        VMSTATE_UINT32_ARRAY(status, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
        VMSTATE_UINT32_ARRAY(gafr, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS * 2),
        VMSTATE_UINT32_ARRAY(prev_level, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
        VMSTATE_END_OF_LIST(),
    },
};

static Property pxa2xx_gpio_properties[] = {
    DEFINE_PROP_INT32("lines", PXA2xxGPIOInfo, lines, 0),
    DEFINE_PROP_INT32("ncpu", PXA2xxGPIOInfo, ncpu, 0),
    DEFINE_PROP_END_OF_LIST(),
};

static void pxa2xx_gpio_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);

    dc->desc = "PXA2xx GPIO controller";
    dc->props = pxa2xx_gpio_properties;
    dc->vmsd = &vmstate_pxa2xx_gpio_regs;
    dc->realize = pxa2xx_gpio_realize;
}

static const TypeInfo pxa2xx_gpio_info = {
    .name          = TYPE_PXA2XX_GPIO,
    .parent        = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(PXA2xxGPIOInfo),
    .instance_init = pxa2xx_gpio_initfn,
    .class_init    = pxa2xx_gpio_class_init,
};

static void pxa2xx_gpio_register_types(void)
{
    type_register_static(&pxa2xx_gpio_info);
}

type_init(pxa2xx_gpio_register_types)
Commit	Line	Data
c1713132 AZ	1	/*
	2	* Intel XScale PXA255/270 GPIO controller emulation.
	3	*
	4	* Copyright (c) 2006 Openedhand Ltd.
	5	* Written by Andrzej Zaborowski <[email protected]>
	6	*
	7	* This code is licensed under the GPL.
	8	*/
	9
12b16722	10	#include "qemu/osdep.h"
33c11879	11	#include "cpu.h"
83c9f4ca PB	12	#include "hw/hw.h"
83c9f4ca PB	13	#include "hw/sysbus.h"
0d09e41a	14	#include "hw/arm/pxa.h"
03dd024f	15	#include "qemu/log.h"
0b8fa32f	16	#include "qemu/module.h"
c1713132 AZ	17
	18	#define PXA2XX_GPIO_BANKS 4
	19
922bb317 AF	20	#define TYPE_PXA2XX_GPIO "pxa2xx-gpio"
	21	#define PXA2XX_GPIO(obj) \
	22	OBJECT_CHECK(PXA2xxGPIOInfo, (obj), TYPE_PXA2XX_GPIO)
	23
0bb53337	24	typedef struct PXA2xxGPIOInfo PXA2xxGPIOInfo;
bc24a225	25	struct PXA2xxGPIOInfo {
922bb317 AF	26	/< private >/
	27	SysBusDevice parent_obj;
	28	/< public >/
	29
55a8b801	30	MemoryRegion iomem;
0bb53337	31	qemu_irq irq0, irq1, irqX;
c1713132	32	int lines;
0bb53337	33	int ncpu;
95d42bb5	34	ARMCPU *cpu;
c1713132 AZ	35
	36	/* XXX: GNU C vectors are more suitable */
	37	uint32_t ilevel[PXA2XX_GPIO_BANKS];
	38	uint32_t olevel[PXA2XX_GPIO_BANKS];
	39	uint32_t dir[PXA2XX_GPIO_BANKS];
	40	uint32_t rising[PXA2XX_GPIO_BANKS];
	41	uint32_t falling[PXA2XX_GPIO_BANKS];
	42	uint32_t status[PXA2XX_GPIO_BANKS];
	43	uint32_t gafr[PXA2XX_GPIO_BANKS * 2];
	44
	45	uint32_t prev_level[PXA2XX_GPIO_BANKS];
38641a52 AZ	46	qemu_irq handler[PXA2XX_GPIO_BANKS * 32];
38641a52 AZ	47	qemu_irq read_notify;
c1713132 AZ	48	};
	49
	50	static struct {
	51	enum {
	52	GPIO_NONE,
	53	GPLR,
	54	GPSR,
	55	GPCR,
	56	GPDR,
	57	GRER,
	58	GFER,
	59	GEDR,
	60	GAFR_L,
	61	GAFR_U,
	62	} reg;
	63	int bank;
	64	} pxa2xx_gpio_regs[0x200] = {
	65	[0 ... 0x1ff] = { GPIO_NONE, 0 },
	66	#define PXA2XX_REG(reg, a0, a1, a2, a3) \
5fafdf24	67	[a0] = { reg, 0 }, [a1] = { reg, 1 }, [a2] = { reg, 2 }, [a3] = { reg, 3 },
c1713132 AZ	68
	69	PXA2XX_REG(GPLR, 0x000, 0x004, 0x008, 0x100)
	70	PXA2XX_REG(GPSR, 0x018, 0x01c, 0x020, 0x118)
	71	PXA2XX_REG(GPCR, 0x024, 0x028, 0x02c, 0x124)
	72	PXA2XX_REG(GPDR, 0x00c, 0x010, 0x014, 0x10c)
	73	PXA2XX_REG(GRER, 0x030, 0x034, 0x038, 0x130)
	74	PXA2XX_REG(GFER, 0x03c, 0x040, 0x044, 0x13c)
	75	PXA2XX_REG(GEDR, 0x048, 0x04c, 0x050, 0x148)
	76	PXA2XX_REG(GAFR_L, 0x054, 0x05c, 0x064, 0x06c)
	77	PXA2XX_REG(GAFR_U, 0x058, 0x060, 0x068, 0x070)
	78	};
	79
bc24a225	80	static void pxa2xx_gpio_irq_update(PXA2xxGPIOInfo *s)
c1713132 AZ	81	{
c1713132 AZ	82	if (s->status[0] & (1 << 0))
0bb53337	83	qemu_irq_raise(s->irq0);
c1713132	84	else
0bb53337	85	qemu_irq_lower(s->irq0);
c1713132 AZ	86
c1713132 AZ	87	if (s->status[0] & (1 << 1))
0bb53337	88	qemu_irq_raise(s->irq1);
c1713132	89	else
0bb53337	90	qemu_irq_lower(s->irq1);
c1713132 AZ	91
c1713132 AZ	92	if ((s->status[0] & ~3) \| s->status[1] \| s->status[2] \| s->status[3])
0bb53337	93	qemu_irq_raise(s->irqX);
c1713132	94	else
0bb53337	95	qemu_irq_lower(s->irqX);
c1713132 AZ	96	}
	97
	98	/* Bitmap of pins used as standby and sleep wake-up sources. */
38641a52	99	static const int pxa2xx_gpio_wake[PXA2XX_GPIO_BANKS] = {
c1713132 AZ	100	0x8003fe1b, 0x002001fc, 0xec080000, 0x0012007f,
	101	};
	102
38641a52	103	static void pxa2xx_gpio_set(void *opaque, int line, int level)
c1713132	104	{
bc24a225	105	PXA2xxGPIOInfo s = (PXA2xxGPIOInfo ) opaque;
259186a7	106	CPUState *cpu = CPU(s->cpu);
c1713132 AZ	107	int bank;
	108	uint32_t mask;
	109
	110	if (line >= s->lines) {
a89f364a	111	printf("%s: No GPIO pin %i\n", __func__, line);
c1713132 AZ	112	return;
	113	}
	114
	115	bank = line >> 5;
43a32ed6	116	mask = 1U << (line & 31);
c1713132 AZ	117
	118	if (level) {
	119	s->status[bank] \|= s->rising[bank] & mask &
	120	~s->ilevel[bank] & ~s->dir[bank];
	121	s->ilevel[bank] \|= mask;
	122	} else {
	123	s->status[bank] \|= s->falling[bank] & mask &
	124	s->ilevel[bank] & ~s->dir[bank];
	125	s->ilevel[bank] &= ~mask;
	126	}
	127
	128	if (s->status[bank] & mask)
	129	pxa2xx_gpio_irq_update(s);
	130
	131	/* Wake-up GPIOs */
259186a7	132	if (cpu->halted && (mask & ~s->dir[bank] & pxa2xx_gpio_wake[bank])) {
c3affe56	133	cpu_interrupt(cpu, CPU_INTERRUPT_EXITTB);
95d42bb5	134	}
c1713132 AZ	135	}
c1713132 AZ	136
bc24a225	137	static void pxa2xx_gpio_handler_update(PXA2xxGPIOInfo *s) {
c1713132 AZ	138	uint32_t level, diff;
	139	int i, bit, line;
	140	for (i = 0; i < PXA2XX_GPIO_BANKS; i ++) {
	141	level = s->olevel[i] & s->dir[i];
	142
	143	for (diff = s->prev_level[i] ^ level; diff; diff ^= 1 << bit) {
786a4ea8	144	bit = ctz32(diff);
c1713132	145	line = bit + 32 * i;
38641a52	146	qemu_set_irq(s->handler[line], (level >> bit) & 1);
c1713132 AZ	147	}
	148
	149	s->prev_level[i] = level;
	150	}
	151	}
	152
a8170e5e	153	static uint64_t pxa2xx_gpio_read(void *opaque, hwaddr offset,
55a8b801	154	unsigned size)
c1713132	155	{
bc24a225	156	PXA2xxGPIOInfo s = (PXA2xxGPIOInfo ) opaque;
c1713132 AZ	157	uint32_t ret;
c1713132 AZ	158	int bank;
c1713132 AZ	159	if (offset >= 0x200)
	160	return 0;
	161
	162	bank = pxa2xx_gpio_regs[offset].bank;
	163	switch (pxa2xx_gpio_regs[offset].reg) {
	164	case GPDR: /* GPIO Pin-Direction registers */
	165	return s->dir[bank];
	166
2b76bdc9	167	case GPSR: /* GPIO Pin-Output Set registers */
ab7a0f0b PM	168	qemu_log_mask(LOG_GUEST_ERROR,
	169	"pxa2xx GPIO: read from write only register GPSR\n");
	170	return 0;
2b76bdc9	171
e1dad5a6	172	case GPCR: /* GPIO Pin-Output Clear registers */
ab7a0f0b PM	173	qemu_log_mask(LOG_GUEST_ERROR,
	174	"pxa2xx GPIO: read from write only register GPCR\n");
	175	return 0;
e1dad5a6	176
c1713132 AZ	177	case GRER: /* GPIO Rising-Edge Detect Enable registers */
	178	return s->rising[bank];
	179
	180	case GFER: /* GPIO Falling-Edge Detect Enable registers */
	181	return s->falling[bank];
	182
	183	case GAFR_L: /* GPIO Alternate Function registers */
	184	return s->gafr[bank * 2];
	185
	186	case GAFR_U: /* GPIO Alternate Function registers */
	187	return s->gafr[bank * 2 + 1];
	188
	189	case GPLR: /* GPIO Pin-Level registers */
	190	ret = (s->olevel[bank] & s->dir[bank]) \|
	191	(s->ilevel[bank] & ~s->dir[bank]);
38641a52	192	qemu_irq_raise(s->read_notify);
c1713132 AZ	193	return ret;
	194
	195	case GEDR: /* GPIO Edge Detect Status registers */
	196	return s->status[bank];
	197
	198	default:
a89f364a	199	hw_error("%s: Bad offset " REG_FMT "\n", __func__, offset);
c1713132 AZ	200	}
	201
	202	return 0;
	203	}
	204
a8170e5e	205	static void pxa2xx_gpio_write(void *opaque, hwaddr offset,
55a8b801	206	uint64_t value, unsigned size)
c1713132	207	{
bc24a225	208	PXA2xxGPIOInfo s = (PXA2xxGPIOInfo ) opaque;
c1713132	209	int bank;
c1713132 AZ	210	if (offset >= 0x200)
	211	return;
	212
	213	bank = pxa2xx_gpio_regs[offset].bank;
	214	switch (pxa2xx_gpio_regs[offset].reg) {
	215	case GPDR: /* GPIO Pin-Direction registers */
	216	s->dir[bank] = value;
	217	pxa2xx_gpio_handler_update(s);
	218	break;
	219
	220	case GPSR: /* GPIO Pin-Output Set registers */
	221	s->olevel[bank] \|= value;
	222	pxa2xx_gpio_handler_update(s);
	223	break;
	224
	225	case GPCR: /* GPIO Pin-Output Clear registers */
	226	s->olevel[bank] &= ~value;
	227	pxa2xx_gpio_handler_update(s);
	228	break;
	229
	230	case GRER: /* GPIO Rising-Edge Detect Enable registers */
	231	s->rising[bank] = value;
	232	break;
	233
	234	case GFER: /* GPIO Falling-Edge Detect Enable registers */
	235	s->falling[bank] = value;
	236	break;
	237
	238	case GAFR_L: /* GPIO Alternate Function registers */
	239	s->gafr[bank * 2] = value;
	240	break;
	241
	242	case GAFR_U: /* GPIO Alternate Function registers */
	243	s->gafr[bank * 2 + 1] = value;
	244	break;
	245
	246	case GEDR: /* GPIO Edge Detect Status registers */
	247	s->status[bank] &= ~value;
	248	pxa2xx_gpio_irq_update(s);
	249	break;
	250
	251	default:
a89f364a	252	hw_error("%s: Bad offset " REG_FMT "\n", __func__, offset);
c1713132 AZ	253	}
	254	}
	255
55a8b801 BC	256	static const MemoryRegionOps pxa_gpio_ops = {
	257	.read = pxa2xx_gpio_read,
	258	.write = pxa2xx_gpio_write,
	259	.endianness = DEVICE_NATIVE_ENDIAN,
c1713132 AZ	260	};
c1713132 AZ	261
a8170e5e	262	DeviceState *pxa2xx_gpio_init(hwaddr base,
55e5c285	263	ARMCPU cpu, DeviceState pic, int lines)
aa941b94	264	{
55e5c285	265	CPUState *cs = CPU(cpu);
0bb53337	266	DeviceState *dev;
aa941b94	267
922bb317	268	dev = qdev_create(NULL, TYPE_PXA2XX_GPIO);
0bb53337	269	qdev_prop_set_int32(dev, "lines", lines);
55e5c285	270	qdev_prop_set_int32(dev, "ncpu", cs->cpu_index);
0bb53337	271	qdev_init_nofail(dev);
aa941b94	272
1356b98d AF	273	sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
1356b98d AF	274	sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0,
e1f8c729	275	qdev_get_gpio_in(pic, PXA2XX_PIC_GPIO_0));
1356b98d	276	sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1,
e1f8c729	277	qdev_get_gpio_in(pic, PXA2XX_PIC_GPIO_1));
1356b98d	278	sysbus_connect_irq(SYS_BUS_DEVICE(dev), 2,
e1f8c729	279	qdev_get_gpio_in(pic, PXA2XX_PIC_GPIO_X));
aa941b94	280
0bb53337	281	return dev;
aa941b94 AZ	282	}
aa941b94 AZ	283
f79a7ff1	284	static void pxa2xx_gpio_initfn(Object *obj)
c1713132	285	{
f79a7ff1	286	SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
922bb317 AF	287	DeviceState *dev = DEVICE(sbd);
922bb317 AF	288	PXA2xxGPIOInfo *s = PXA2XX_GPIO(dev);
c1713132	289
f79a7ff1 XZ	290	memory_region_init_io(&s->iomem, obj, &pxa_gpio_ops,
f79a7ff1 XZ	291	s, "pxa2xx-gpio", 0x1000);
922bb317 AF	292	sysbus_init_mmio(sbd, &s->iomem);
	293	sysbus_init_irq(sbd, &s->irq0);
	294	sysbus_init_irq(sbd, &s->irq1);
	295	sysbus_init_irq(sbd, &s->irqX);
f79a7ff1	296	}
c1713132	297
f79a7ff1 XZ	298	static void pxa2xx_gpio_realize(DeviceState dev, Error *errp)
	299	{
	300	PXA2xxGPIOInfo *s = PXA2XX_GPIO(dev);
	301
	302	s->cpu = ARM_CPU(qemu_get_cpu(s->ncpu));
	303
	304	qdev_init_gpio_in(dev, pxa2xx_gpio_set, s->lines);
	305	qdev_init_gpio_out(dev, s->handler, s->lines);
c1713132 AZ	306	}
	307
	308	/*
	309	* Registers a callback to notify on GPLR reads. This normally
	310	* shouldn't be needed but it is used for the hack on Spitz machines.
	311	*/
0bb53337	312	void pxa2xx_gpio_read_notifier(DeviceState *dev, qemu_irq handler)
38641a52	313	{
922bb317 AF	314	PXA2xxGPIOInfo *s = PXA2XX_GPIO(dev);
922bb317 AF	315
c1713132	316	s->read_notify = handler;
c1713132	317	}
0bb53337 DES	318
	319	static const VMStateDescription vmstate_pxa2xx_gpio_regs = {
	320	.name = "pxa2xx-gpio",
	321	.version_id = 1,
	322	.minimum_version_id = 1,
8f1e884b	323	.fields = (VMStateField[]) {
0bb53337 DES	324	VMSTATE_UINT32_ARRAY(ilevel, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
	325	VMSTATE_UINT32_ARRAY(olevel, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
	326	VMSTATE_UINT32_ARRAY(dir, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
	327	VMSTATE_UINT32_ARRAY(rising, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
	328	VMSTATE_UINT32_ARRAY(falling, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
	329	VMSTATE_UINT32_ARRAY(status, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
	330	VMSTATE_UINT32_ARRAY(gafr, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS * 2),
166fa999	331	VMSTATE_UINT32_ARRAY(prev_level, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
0bb53337 DES	332	VMSTATE_END_OF_LIST(),
	333	},
	334	};
	335
999e12bb AL	336	static Property pxa2xx_gpio_properties[] = {
	337	DEFINE_PROP_INT32("lines", PXA2xxGPIOInfo, lines, 0),
	338	DEFINE_PROP_INT32("ncpu", PXA2xxGPIOInfo, ncpu, 0),
	339	DEFINE_PROP_END_OF_LIST(),
	340	};
	341
	342	static void pxa2xx_gpio_class_init(ObjectClass klass, void data)
	343	{
39bffca2	344	DeviceClass *dc = DEVICE_CLASS(klass);
999e12bb	345
39bffca2 AL	346	dc->desc = "PXA2xx GPIO controller";
39bffca2 AL	347	dc->props = pxa2xx_gpio_properties;
166fa999	348	dc->vmsd = &vmstate_pxa2xx_gpio_regs;
f79a7ff1	349	dc->realize = pxa2xx_gpio_realize;
999e12bb AL	350	}
999e12bb AL	351
8c43a6f0	352	static const TypeInfo pxa2xx_gpio_info = {
922bb317	353	.name = TYPE_PXA2XX_GPIO,
39bffca2 AL	354	.parent = TYPE_SYS_BUS_DEVICE,
39bffca2 AL	355	.instance_size = sizeof(PXA2xxGPIOInfo),
f79a7ff1	356	.instance_init = pxa2xx_gpio_initfn,
39bffca2	357	.class_init = pxa2xx_gpio_class_init,
0bb53337 DES	358	};
0bb53337 DES	359
83f7d43a	360	static void pxa2xx_gpio_register_types(void)
0bb53337	361	{
39bffca2	362	type_register_static(&pxa2xx_gpio_info);
0bb53337	363	}
83f7d43a AF	364
83f7d43a AF	365	type_init(pxa2xx_gpio_register_types)