[qemu.git] / hw / cris / axis_dev88.c

/*
 * QEMU model for the AXIS devboard 88.
 *
 * Copyright (c) 2009 Edgar E. Iglesias, Axis Communications AB.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */

#include "qemu/osdep.h"
#include "qapi/error.h"
#include "qemu-common.h"
#include "cpu.h"
#include "hw/sysbus.h"
#include "net/net.h"
#include "hw/block/flash.h"
#include "hw/boards.h"
#include "hw/cris/etraxfs.h"
#include "hw/loader.h"
#include "elf.h"
#include "boot.h"
#include "sysemu/block-backend.h"
#include "exec/address-spaces.h"
#include "sysemu/qtest.h"
#include "sysemu/sysemu.h"

#define D(x)
#define DNAND(x)

struct nand_state_t
{
    DeviceState *nand;
    MemoryRegion iomem;
    unsigned int rdy:1;
    unsigned int ale:1;
    unsigned int cle:1;
    unsigned int ce:1;
};

static struct nand_state_t nand_state;
static uint64_t nand_read(void *opaque, hwaddr addr, unsigned size)
{
    struct nand_state_t *s = opaque;
    uint32_t r;
    int rdy;

    r = nand_getio(s->nand);
    nand_getpins(s->nand, &rdy);
    s->rdy = rdy;

    DNAND(printf("%s addr=%x r=%x\n", __func__, addr, r));
    return r;
}

static void
nand_write(void *opaque, hwaddr addr, uint64_t value,
           unsigned size)
{
    struct nand_state_t *s = opaque;
    int rdy;

    DNAND(printf("%s addr=%x v=%x\n", __func__, addr, (unsigned)value));
    nand_setpins(s->nand, s->cle, s->ale, s->ce, 1, 0);
    nand_setio(s->nand, value);
    nand_getpins(s->nand, &rdy);
    s->rdy = rdy;
}

static const MemoryRegionOps nand_ops = {
    .read = nand_read,
    .write = nand_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
};

struct tempsensor_t
{
    unsigned int shiftreg;
    unsigned int count;
    enum {
        ST_OUT, ST_IN, ST_Z
    } state;

    uint16_t regs[3];
};

static void tempsensor_clkedge(struct tempsensor_t *s,
                               unsigned int clk, unsigned int data_in)
{
    D(printf("%s clk=%d state=%d sr=%x\n", __func__,
             clk, s->state, s->shiftreg));
    if (s->count == 0) {
        s->count = 16;
        s->state = ST_OUT;
    }
    switch (s->state) {
        case ST_OUT:
            /* Output reg is clocked at negedge.  */
            if (!clk) {
                s->count--;
                s->shiftreg <<= 1;
                if (s->count == 0) {
                    s->shiftreg = 0;
                    s->state = ST_IN;
                    s->count = 16;
                }
            }
            break;
        case ST_Z:
            if (clk) {
                s->count--;
                if (s->count == 0) {
                    s->shiftreg = 0;
                    s->state = ST_OUT;
                    s->count = 16;
                }
            }
            break;
        case ST_IN:
            /* Indata is sampled at posedge.  */
            if (clk) {
                s->count--;
                s->shiftreg <<= 1;
                s->shiftreg |= data_in & 1;
                if (s->count == 0) {
                    D(printf("%s cfgreg=%x\n", __func__, s->shiftreg));
                    s->regs[0] = s->shiftreg;
                    s->state = ST_OUT;
                    s->count = 16;

                    if ((s->regs[0] & 0xff) == 0) {
                        /* 25 degrees celsius.  */
                        s->shiftreg = 0x0b9f;
                    } else if ((s->regs[0] & 0xff) == 0xff) {
                        /* Sensor ID, 0x8100 LM70.  */
                        s->shiftreg = 0x8100;
                    } else
                        printf("Invalid tempsens state %x\n", s->regs[0]);
                }
            }
            break;
    }
}


#define RW_PA_DOUT    0x00
#define R_PA_DIN      0x01
#define RW_PA_OE      0x02
#define RW_PD_DOUT    0x10
#define R_PD_DIN      0x11
#define RW_PD_OE      0x12

static struct gpio_state_t
{
    MemoryRegion iomem;
    struct nand_state_t *nand;
    struct tempsensor_t tempsensor;
    uint32_t regs[0x5c / 4];
} gpio_state;

static uint64_t gpio_read(void *opaque, hwaddr addr, unsigned size)
{
    struct gpio_state_t *s = opaque;
    uint32_t r = 0;

    addr >>= 2;
    switch (addr)
    {
        case R_PA_DIN:
            r = s->regs[RW_PA_DOUT] & s->regs[RW_PA_OE];

            /* Encode pins from the nand.  */
            r |= s->nand->rdy << 7;
            break;
        case R_PD_DIN:
            r = s->regs[RW_PD_DOUT] & s->regs[RW_PD_OE];

            /* Encode temp sensor pins.  */
            r |= (!!(s->tempsensor.shiftreg & 0x10000)) << 4;
            break;

        default:
            r = s->regs[addr];
            break;
    }
    return r;
    D(printf("%s %x=%x\n", __func__, addr, r));
}

static void gpio_write(void *opaque, hwaddr addr, uint64_t value,
                       unsigned size)
{
    struct gpio_state_t *s = opaque;
    D(printf("%s %x=%x\n", __func__, addr, (unsigned)value));

    addr >>= 2;
    switch (addr)
    {
        case RW_PA_DOUT:
            /* Decode nand pins.  */
            s->nand->ale = !!(value & (1 << 6));
            s->nand->cle = !!(value & (1 << 5));
            s->nand->ce  = !!(value & (1 << 4));

            s->regs[addr] = value;
            break;

        case RW_PD_DOUT:
            /* Temp sensor clk.  */
            if ((s->regs[addr] ^ value) & 2)
                tempsensor_clkedge(&s->tempsensor, !!(value & 2),
                                   !!(value & 16));
            s->regs[addr] = value;
            break;

        default:
            s->regs[addr] = value;
            break;
    }
}

static const MemoryRegionOps gpio_ops = {
    .read = gpio_read,
    .write = gpio_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
    .valid = {
        .min_access_size = 4,
        .max_access_size = 4,
    },
};

#define INTMEM_SIZE (128 * 1024)

static struct cris_load_info li;

static
void axisdev88_init(MachineState *machine)
{
    ram_addr_t ram_size = machine->ram_size;
    const char *cpu_model = machine->cpu_model;
    const char *kernel_filename = machine->kernel_filename;
    const char *kernel_cmdline = machine->kernel_cmdline;
    CRISCPU *cpu;
    CPUCRISState *env;
    DeviceState *dev;
    SysBusDevice *s;
    DriveInfo *nand;
    qemu_irq irq[30], nmi[2];
    void *etraxfs_dmac;
    struct etraxfs_dma_client *dma_eth;
    int i;
    MemoryRegion *address_space_mem = get_system_memory();
    MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
    MemoryRegion *phys_intmem = g_new(MemoryRegion, 1);

    /* init CPUs */
    if (cpu_model == NULL) {
        cpu_model = "crisv32";
    }
    cpu = cpu_cris_init(cpu_model);
    env = &cpu->env;

    /* allocate RAM */
    memory_region_allocate_system_memory(phys_ram, NULL, "axisdev88.ram",
                                         ram_size);
    memory_region_add_subregion(address_space_mem, 0x40000000, phys_ram);

    /* The ETRAX-FS has 128Kb on chip ram, the docs refer to it as the 
       internal memory.  */
    memory_region_init_ram(phys_intmem, NULL, "axisdev88.chipram",
                           INTMEM_SIZE, &error_fatal);
    memory_region_add_subregion(address_space_mem, 0x38000000, phys_intmem);

      /* Attach a NAND flash to CS1.  */
    nand = drive_get(IF_MTD, 0, 0);
    nand_state.nand = nand_init(nand ? blk_by_legacy_dinfo(nand) : NULL,
                                NAND_MFR_STMICRO, 0x39);
    memory_region_init_io(&nand_state.iomem, NULL, &nand_ops, &nand_state,
                          "nand", 0x05000000);
    memory_region_add_subregion(address_space_mem, 0x10000000,
                                &nand_state.iomem);

    gpio_state.nand = &nand_state;
    memory_region_init_io(&gpio_state.iomem, NULL, &gpio_ops, &gpio_state,
                          "gpio", 0x5c);
    memory_region_add_subregion(address_space_mem, 0x3001a000,
                                &gpio_state.iomem);


    dev = qdev_create(NULL, "etraxfs,pic");
    /* FIXME: Is there a proper way to signal vectors to the CPU core?  */
    qdev_prop_set_ptr(dev, "interrupt_vector", &env->interrupt_vector);
    qdev_init_nofail(dev);
    s = SYS_BUS_DEVICE(dev);
    sysbus_mmio_map(s, 0, 0x3001c000);
    sysbus_connect_irq(s, 0, qdev_get_gpio_in(DEVICE(cpu), CRIS_CPU_IRQ));
    sysbus_connect_irq(s, 1, qdev_get_gpio_in(DEVICE(cpu), CRIS_CPU_NMI));
    for (i = 0; i < 30; i++) {
        irq[i] = qdev_get_gpio_in(dev, i);
    }
    nmi[0] = qdev_get_gpio_in(dev, 30);
    nmi[1] = qdev_get_gpio_in(dev, 31);

    etraxfs_dmac = etraxfs_dmac_init(0x30000000, 10);
    for (i = 0; i < 10; i++) {
        /* On ETRAX, odd numbered channels are inputs.  */
        etraxfs_dmac_connect(etraxfs_dmac, i, irq + 7 + i, i & 1);
    }

    /* Add the two ethernet blocks.  */
    dma_eth = g_malloc0(sizeof dma_eth[0] * 4); /* Allocate 4 channels.  */
    etraxfs_eth_init(&nd_table[0], 0x30034000, 1, &dma_eth[0], &dma_eth[1]);
    if (nb_nics > 1) {
        etraxfs_eth_init(&nd_table[1], 0x30036000, 2, &dma_eth[2], &dma_eth[3]);
    }

    /* The DMA Connector block is missing, hardwire things for now.  */
    etraxfs_dmac_connect_client(etraxfs_dmac, 0, &dma_eth[0]);
    etraxfs_dmac_connect_client(etraxfs_dmac, 1, &dma_eth[1]);
    if (nb_nics > 1) {
        etraxfs_dmac_connect_client(etraxfs_dmac, 6, &dma_eth[2]);
        etraxfs_dmac_connect_client(etraxfs_dmac, 7, &dma_eth[3]);
    }

    /* 2 timers.  */
    sysbus_create_varargs("etraxfs,timer", 0x3001e000, irq[0x1b], nmi[1], NULL);
    sysbus_create_varargs("etraxfs,timer", 0x3005e000, irq[0x1b], nmi[1], NULL);

    for (i = 0; i < 4; i++) {
        etraxfs_ser_create(0x30026000 + i * 0x2000, irq[0x14 + i], serial_hds[i]);
    }

    if (kernel_filename) {
        li.image_filename = kernel_filename;
        li.cmdline = kernel_cmdline;
        cris_load_image(cpu, &li);
    } else if (!qtest_enabled()) {
        fprintf(stderr, "Kernel image must be specified\n");
        exit(1);
    }
}

static void axisdev88_machine_init(MachineClass *mc)
{
    mc->desc = "AXIS devboard 88";
    mc->init = axisdev88_init;
    mc->is_default = 1;
}

DEFINE_MACHINE("axis-dev88", axisdev88_machine_init)
Commit	Line	Data
10c144e2 EI	1	/*
	2	* QEMU model for the AXIS devboard 88.
	3	*
	4	* Copyright (c) 2009 Edgar E. Iglesias, Axis Communications AB.
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
4b816985	24
23b0d7df	25	#include "qemu/osdep.h"
da34e65c	26	#include "qapi/error.h"
4771d756 PB	27	#include "qemu-common.h"
4771d756 PB	28	#include "cpu.h"
83c9f4ca	29	#include "hw/sysbus.h"
1422e32d	30	#include "net/net.h"
0d09e41a	31	#include "hw/block/flash.h"
83c9f4ca	32	#include "hw/boards.h"
0d09e41a	33	#include "hw/cris/etraxfs.h"
83c9f4ca	34	#include "hw/loader.h"
ca20cf32	35	#include "elf.h"
47b43a1f	36	#include "boot.h"
fa1d36df	37	#include "sysemu/block-backend.h"
022c62cb	38	#include "exec/address-spaces.h"
5efe843a	39	#include "sysemu/qtest.h"
8290de92	40	#include "sysemu/sysemu.h"
10c144e2 EI	41
	42	#define D(x)
	43	#define DNAND(x)
	44
	45	struct nand_state_t
	46	{
d4220389	47	DeviceState *nand;
838335ec	48	MemoryRegion iomem;
10c144e2 EI	49	unsigned int rdy:1;
	50	unsigned int ale:1;
	51	unsigned int cle:1;
	52	unsigned int ce:1;
	53	};
	54
	55	static struct nand_state_t nand_state;
a8170e5e	56	static uint64_t nand_read(void *opaque, hwaddr addr, unsigned size)
10c144e2 EI	57	{
	58	struct nand_state_t *s = opaque;
	59	uint32_t r;
	60	int rdy;
	61
	62	r = nand_getio(s->nand);
	63	nand_getpins(s->nand, &rdy);
	64	s->rdy = rdy;
	65
	66	DNAND(printf("%s addr=%x r=%x\n", __func__, addr, r));
	67	return r;
	68	}
	69
	70	static void
a8170e5e	71	nand_write(void *opaque, hwaddr addr, uint64_t value,
838335ec	72	unsigned size)
10c144e2 EI	73	{
	74	struct nand_state_t *s = opaque;
	75	int rdy;
	76
838335ec	77	DNAND(printf("%s addr=%x v=%x\n", __func__, addr, (unsigned)value));
10c144e2 EI	78	nand_setpins(s->nand, s->cle, s->ale, s->ce, 1, 0);
	79	nand_setio(s->nand, value);
	80	nand_getpins(s->nand, &rdy);
	81	s->rdy = rdy;
	82	}
	83
838335ec AK	84	static const MemoryRegionOps nand_ops = {
	85	.read = nand_read,
	86	.write = nand_write,
	87	.endianness = DEVICE_NATIVE_ENDIAN,
10c144e2 EI	88	};
10c144e2 EI	89
4a1e6bea EI	90	struct tempsensor_t
	91	{
	92	unsigned int shiftreg;
	93	unsigned int count;
	94	enum {
	95	ST_OUT, ST_IN, ST_Z
	96	} state;
	97
	98	uint16_t regs[3];
	99	};
	100
	101	static void tempsensor_clkedge(struct tempsensor_t *s,
	102	unsigned int clk, unsigned int data_in)
	103	{
	104	D(printf("%s clk=%d state=%d sr=%x\n", __func__,
	105	clk, s->state, s->shiftreg));
	106	if (s->count == 0) {
	107	s->count = 16;
	108	s->state = ST_OUT;
	109	}
	110	switch (s->state) {
	111	case ST_OUT:
	112	/* Output reg is clocked at negedge. */
	113	if (!clk) {
	114	s->count--;
	115	s->shiftreg <<= 1;
	116	if (s->count == 0) {
	117	s->shiftreg = 0;
	118	s->state = ST_IN;
	119	s->count = 16;
	120	}
	121	}
	122	break;
	123	case ST_Z:
	124	if (clk) {
	125	s->count--;
	126	if (s->count == 0) {
	127	s->shiftreg = 0;
	128	s->state = ST_OUT;
	129	s->count = 16;
	130	}
	131	}
	132	break;
	133	case ST_IN:
	134	/* Indata is sampled at posedge. */
	135	if (clk) {
	136	s->count--;
	137	s->shiftreg <<= 1;
	138	s->shiftreg \|= data_in & 1;
	139	if (s->count == 0) {
	140	D(printf("%s cfgreg=%x\n", __func__, s->shiftreg));
	141	s->regs[0] = s->shiftreg;
	142	s->state = ST_OUT;
	143	s->count = 16;
	144
	145	if ((s->regs[0] & 0xff) == 0) {
67cc32eb	146	/* 25 degrees celsius. */
4a1e6bea EI	147	s->shiftreg = 0x0b9f;
	148	} else if ((s->regs[0] & 0xff) == 0xff) {
	149	/* Sensor ID, 0x8100 LM70. */
	150	s->shiftreg = 0x8100;
	151	} else
	152	printf("Invalid tempsens state %x\n", s->regs[0]);
	153	}
	154	}
	155	break;
	156	}
	157	}
	158
	159
	160	#define RW_PA_DOUT 0x00
	161	#define R_PA_DIN 0x01
	162	#define RW_PA_OE 0x02
	163	#define RW_PD_DOUT 0x10
	164	#define R_PD_DIN 0x11
	165	#define RW_PD_OE 0x12
	166
	167	static struct gpio_state_t
10c144e2	168	{
838335ec	169	MemoryRegion iomem;
10c144e2	170	struct nand_state_t *nand;
4a1e6bea	171	struct tempsensor_t tempsensor;
10c144e2 EI	172	uint32_t regs[0x5c / 4];
	173	} gpio_state;
	174
a8170e5e	175	static uint64_t gpio_read(void *opaque, hwaddr addr, unsigned size)
10c144e2 EI	176	{
	177	struct gpio_state_t *s = opaque;
	178	uint32_t r = 0;
	179
	180	addr >>= 2;
	181	switch (addr)
	182	{
	183	case R_PA_DIN:
	184	r = s->regs[RW_PA_DOUT] & s->regs[RW_PA_OE];
	185
	186	/* Encode pins from the nand. */
	187	r \|= s->nand->rdy << 7;
	188	break;
4a1e6bea EI	189	case R_PD_DIN:
	190	r = s->regs[RW_PD_DOUT] & s->regs[RW_PD_OE];
	191
	192	/* Encode temp sensor pins. */
	193	r \|= (!!(s->tempsensor.shiftreg & 0x10000)) << 4;
	194	break;
	195
10c144e2 EI	196	default:
	197	r = s->regs[addr];
	198	break;
	199	}
	200	return r;
	201	D(printf("%s %x=%x\n", __func__, addr, r));
	202	}
	203
a8170e5e	204	static void gpio_write(void *opaque, hwaddr addr, uint64_t value,
838335ec	205	unsigned size)
10c144e2 EI	206	{
10c144e2 EI	207	struct gpio_state_t *s = opaque;
838335ec	208	D(printf("%s %x=%x\n", __func__, addr, (unsigned)value));
10c144e2 EI	209
	210	addr >>= 2;
	211	switch (addr)
	212	{
	213	case RW_PA_DOUT:
	214	/* Decode nand pins. */
	215	s->nand->ale = !!(value & (1 << 6));
	216	s->nand->cle = !!(value & (1 << 5));
	217	s->nand->ce = !!(value & (1 << 4));
	218
	219	s->regs[addr] = value;
	220	break;
4a1e6bea EI	221
	222	case RW_PD_DOUT:
	223	/* Temp sensor clk. */
	224	if ((s->regs[addr] ^ value) & 2)
	225	tempsensor_clkedge(&s->tempsensor, !!(value & 2),
	226	!!(value & 16));
	227	s->regs[addr] = value;
	228	break;
	229
10c144e2 EI	230	default:
	231	s->regs[addr] = value;
	232	break;
	233	}
	234	}
	235
838335ec AK	236	static const MemoryRegionOps gpio_ops = {
	237	.read = gpio_read,
	238	.write = gpio_write,
	239	.endianness = DEVICE_NATIVE_ENDIAN,
	240	.valid = {
	241	.min_access_size = 4,
	242	.max_access_size = 4,
	243	},
10c144e2 EI	244	};
	245
	246	#define INTMEM_SIZE (128 * 1024)
	247
77d4f95e	248	static struct cris_load_info li;
409dbce5	249
10c144e2	250	static
3ef96221	251	void axisdev88_init(MachineState *machine)
10c144e2	252	{
3ef96221 MA	253	ram_addr_t ram_size = machine->ram_size;
	254	const char *cpu_model = machine->cpu_model;
	255	const char *kernel_filename = machine->kernel_filename;
	256	const char *kernel_cmdline = machine->kernel_cmdline;
ddeb9ae5	257	CRISCPU *cpu;
fc9bb176	258	CPUCRISState *env;
fd6dc90b EI	259	DeviceState *dev;
fd6dc90b EI	260	SysBusDevice *s;
522f253c	261	DriveInfo *nand;
4a6da670	262	qemu_irq irq[30], nmi[2];
10c144e2	263	void *etraxfs_dmac;
1da005b3	264	struct etraxfs_dma_client *dma_eth;
10c144e2	265	int i;
b0e3d5ac AK	266	MemoryRegion *address_space_mem = get_system_memory();
	267	MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
	268	MemoryRegion *phys_intmem = g_new(MemoryRegion, 1);
10c144e2 EI	269
	270	/* init CPUs */
	271	if (cpu_model == NULL) {
	272	cpu_model = "crisv32";
	273	}
ddeb9ae5 AF	274	cpu = cpu_cris_init(cpu_model);
ddeb9ae5 AF	275	env = &cpu->env;
10c144e2 EI	276
10c144e2 EI	277	/* allocate RAM */
c0c85841 DM	278	memory_region_allocate_system_memory(phys_ram, NULL, "axisdev88.ram",
c0c85841 DM	279	ram_size);
b0e3d5ac	280	memory_region_add_subregion(address_space_mem, 0x40000000, phys_ram);
10c144e2 EI	281
	282	/* The ETRAX-FS has 128Kb on chip ram, the docs refer to it as the
	283	internal memory. */
98a99ce0 PM	284	memory_region_init_ram(phys_intmem, NULL, "axisdev88.chipram",
98a99ce0 PM	285	INTMEM_SIZE, &error_fatal);
b0e3d5ac	286	memory_region_add_subregion(address_space_mem, 0x38000000, phys_intmem);
10c144e2 EI	287
10c144e2 EI	288	/* Attach a NAND flash to CS1. */
522f253c	289	nand = drive_get(IF_MTD, 0, 0);
4be74634	290	nand_state.nand = nand_init(nand ? blk_by_legacy_dinfo(nand) : NULL,
522f253c	291	NAND_MFR_STMICRO, 0x39);
2c9b15ca	292	memory_region_init_io(&nand_state.iomem, NULL, &nand_ops, &nand_state,
838335ec AK	293	"nand", 0x05000000);
	294	memory_region_add_subregion(address_space_mem, 0x10000000,
	295	&nand_state.iomem);
10c144e2 EI	296
10c144e2 EI	297	gpio_state.nand = &nand_state;
2c9b15ca	298	memory_region_init_io(&gpio_state.iomem, NULL, &gpio_ops, &gpio_state,
838335ec AK	299	"gpio", 0x5c);
	300	memory_region_add_subregion(address_space_mem, 0x3001a000,
	301	&gpio_state.iomem);
10c144e2 EI	302
10c144e2 EI	303
fd6dc90b EI	304	dev = qdev_create(NULL, "etraxfs,pic");
fd6dc90b EI	305	/* FIXME: Is there a proper way to signal vectors to the CPU core? */
ee6847d1	306	qdev_prop_set_ptr(dev, "interrupt_vector", &env->interrupt_vector);
e23a1b33	307	qdev_init_nofail(dev);
1356b98d	308	s = SYS_BUS_DEVICE(dev);
fd6dc90b	309	sysbus_mmio_map(s, 0, 0x3001c000);
4a6da670 EI	310	sysbus_connect_irq(s, 0, qdev_get_gpio_in(DEVICE(cpu), CRIS_CPU_IRQ));
4a6da670 EI	311	sysbus_connect_irq(s, 1, qdev_get_gpio_in(DEVICE(cpu), CRIS_CPU_NMI));
fd6dc90b	312	for (i = 0; i < 30; i++) {
067a3ddc	313	irq[i] = qdev_get_gpio_in(dev, i);
fd6dc90b	314	}
067a3ddc PB	315	nmi[0] = qdev_get_gpio_in(dev, 30);
067a3ddc PB	316	nmi[1] = qdev_get_gpio_in(dev, 31);
73cfd29f	317
ba494313	318	etraxfs_dmac = etraxfs_dmac_init(0x30000000, 10);
10c144e2 EI	319	for (i = 0; i < 10; i++) {
10c144e2 EI	320	/* On ETRAX, odd numbered channels are inputs. */
73cfd29f	321	etraxfs_dmac_connect(etraxfs_dmac, i, irq + 7 + i, i & 1);
10c144e2 EI	322	}
	323
	324	/* Add the two ethernet blocks. */
7267c094	325	dma_eth = g_malloc0(sizeof dma_eth[0] * 4); /* Allocate 4 channels. */
1da005b3 EI	326	etraxfs_eth_init(&nd_table[0], 0x30034000, 1, &dma_eth[0], &dma_eth[1]);
	327	if (nb_nics > 1) {
	328	etraxfs_eth_init(&nd_table[1], 0x30036000, 2, &dma_eth[2], &dma_eth[3]);
	329	}
10c144e2 EI	330
10c144e2 EI	331	/* The DMA Connector block is missing, hardwire things for now. */
1da005b3 EI	332	etraxfs_dmac_connect_client(etraxfs_dmac, 0, &dma_eth[0]);
	333	etraxfs_dmac_connect_client(etraxfs_dmac, 1, &dma_eth[1]);
	334	if (nb_nics > 1) {
	335	etraxfs_dmac_connect_client(etraxfs_dmac, 6, &dma_eth[2]);
	336	etraxfs_dmac_connect_client(etraxfs_dmac, 7, &dma_eth[3]);
10c144e2 EI	337	}
	338
	339	/* 2 timers. */
3b1fd90e EI	340	sysbus_create_varargs("etraxfs,timer", 0x3001e000, irq[0x1b], nmi[1], NULL);
3b1fd90e EI	341	sysbus_create_varargs("etraxfs,timer", 0x3005e000, irq[0x1b], nmi[1], NULL);
10c144e2 EI	342
10c144e2 EI	343	for (i = 0; i < 4; i++) {
8290de92	344	etraxfs_ser_create(0x30026000 + i * 0x2000, irq[0x14 + i], serial_hds[i]);
10c144e2 EI	345	}
10c144e2 EI	346
5efe843a AF	347	if (kernel_filename) {
	348	li.image_filename = kernel_filename;
	349	li.cmdline = kernel_cmdline;
	350	cris_load_image(cpu, &li);
	351	} else if (!qtest_enabled()) {
77d4f95e EI	352	fprintf(stderr, "Kernel image must be specified\n");
77d4f95e EI	353	exit(1);
10c144e2	354	}
10c144e2 EI	355	}
10c144e2 EI	356
e264d29d	357	static void axisdev88_machine_init(MachineClass *mc)
f80f9ec9	358	{
e264d29d EH	359	mc->desc = "AXIS devboard 88";
	360	mc->init = axisdev88_init;
	361	mc->is_default = 1;
f80f9ec9 AL	362	}
f80f9ec9 AL	363
e264d29d	364	DEFINE_MACHINE("axis-dev88", axisdev88_machine_init)