[qemu.git] / target-cris / mmu.c

/*
 *  CRIS mmu emulation.
 *
 *  Copyright (c) 2007 AXIS Communications AB
 *  Written by Edgar E. Iglesias.
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */

#ifndef CONFIG_USER_ONLY

#include <stdio.h>
#include <string.h>
#include <stdlib.h>

#include "config.h"
#include "cpu.h"
#include "mmu.h"
#include "exec-all.h"

#ifdef DEBUG
#define D(x) x
#define D_LOG(...) qemu_log(__VA__ARGS__)
#else
#define D(x)
#define D_LOG(...) do { } while (0)
#endif

void cris_mmu_init(CPUState *env)
{
	env->mmu_rand_lfsr = 0xcccc;
}

#define SR_POLYNOM 0x8805
static inline unsigned int compute_polynom(unsigned int sr)
{
	unsigned int i;
	unsigned int f;

	f = 0;
	for (i = 0; i < 16; i++)
		f += ((SR_POLYNOM >> i) & 1) & ((sr >> i) & 1);

	return f;
}

static inline int cris_mmu_enabled(uint32_t rw_gc_cfg)
{
	return (rw_gc_cfg & 12) != 0;
}

static inline int cris_mmu_segmented_addr(int seg, uint32_t rw_mm_cfg)
{
	return (1 << seg) & rw_mm_cfg;
}

static uint32_t cris_mmu_translate_seg(CPUState *env, int seg)
{
	uint32_t base;
	int i;

	if (seg < 8)
		base = env->sregs[SFR_RW_MM_KBASE_LO];
	else
		base = env->sregs[SFR_RW_MM_KBASE_HI];

	i = seg & 7;
	base >>= i * 4;
	base &= 15;

	base <<= 28;
	return base;
}
/* Used by the tlb decoder.  */
#define EXTRACT_FIELD(src, start, end) \
	    (((src) >> start) & ((1 << (end - start + 1)) - 1))

static inline void set_field(uint32_t *dst, unsigned int val, 
			     unsigned int offset, unsigned int width)
{
	uint32_t mask;

	mask = (1 << width) - 1;
	mask <<= offset;
	val <<= offset;

	val &= mask;
	*dst &= ~(mask);
	*dst |= val;
}

#ifdef DEBUG
static void dump_tlb(CPUState *env, int mmu)
{
	int set;
	int idx;
	uint32_t hi, lo, tlb_vpn, tlb_pfn;

	for (set = 0; set < 4; set++) {
		for (idx = 0; idx < 16; idx++) {
			lo = env->tlbsets[mmu][set][idx].lo;
			hi = env->tlbsets[mmu][set][idx].hi;
			tlb_vpn = EXTRACT_FIELD(hi, 13, 31);
			tlb_pfn = EXTRACT_FIELD(lo, 13, 31);

			printf ("TLB: [%d][%d] hi=%x lo=%x v=%x p=%x\n", 
					set, idx, hi, lo, tlb_vpn, tlb_pfn);
		}
	}
}
#endif

/* rw 0 = read, 1 = write, 2 = exec.  */
static int cris_mmu_translate_page(struct cris_mmu_result *res,
				   CPUState *env, uint32_t vaddr,
				   int rw, int usermode)
{
	unsigned int vpage;
	unsigned int idx;
	uint32_t pid, lo, hi;
	uint32_t tlb_vpn, tlb_pfn = 0;
	int tlb_pid, tlb_g, tlb_v, tlb_k, tlb_w, tlb_x;
	int cfg_v, cfg_k, cfg_w, cfg_x;	
	int set, match = 0;
	uint32_t r_cause;
	uint32_t r_cfg;
	int rwcause;
	int mmu = 1; /* Data mmu is default.  */
	int vect_base;

	r_cause = env->sregs[SFR_R_MM_CAUSE];
	r_cfg = env->sregs[SFR_RW_MM_CFG];
	pid = env->pregs[PR_PID] & 0xff;

	switch (rw) {
		case 2: rwcause = CRIS_MMU_ERR_EXEC; mmu = 0; break;
		case 1: rwcause = CRIS_MMU_ERR_WRITE; break;
		default:
		case 0: rwcause = CRIS_MMU_ERR_READ; break;
	}

	/* I exception vectors 4 - 7, D 8 - 11.  */
	vect_base = (mmu + 1) * 4;

	vpage = vaddr >> 13;

	/* We know the index which to check on each set.
	   Scan both I and D.  */
#if 0
	for (set = 0; set < 4; set++) {
		for (idx = 0; idx < 16; idx++) {
			lo = env->tlbsets[mmu][set][idx].lo;
			hi = env->tlbsets[mmu][set][idx].hi;
			tlb_vpn = EXTRACT_FIELD(hi, 13, 31);
			tlb_pfn = EXTRACT_FIELD(lo, 13, 31);

			printf ("TLB: [%d][%d] hi=%x lo=%x v=%x p=%x\n", 
					set, idx, hi, lo, tlb_vpn, tlb_pfn);
		}
	}
#endif

	idx = vpage & 15;
	for (set = 0; set < 4; set++)
	{
		lo = env->tlbsets[mmu][set][idx].lo;
		hi = env->tlbsets[mmu][set][idx].hi;

		tlb_vpn = hi >> 13;
		tlb_pid = EXTRACT_FIELD(hi, 0, 7);
		tlb_g  = EXTRACT_FIELD(lo, 4, 4);

		D_LOG("TLB[%d][%d][%d] v=%x vpage=%x lo=%x hi=%x\n", 
			 mmu, set, idx, tlb_vpn, vpage, lo, hi);
		if ((tlb_g || (tlb_pid == pid))
		    && tlb_vpn == vpage) {
			match = 1;
			break;
		}
	}

	res->bf_vec = vect_base;
	if (match) {
		cfg_w  = EXTRACT_FIELD(r_cfg, 19, 19);
		cfg_k  = EXTRACT_FIELD(r_cfg, 18, 18);
		cfg_x  = EXTRACT_FIELD(r_cfg, 17, 17);
		cfg_v  = EXTRACT_FIELD(r_cfg, 16, 16);

		tlb_pfn = EXTRACT_FIELD(lo, 13, 31);
		tlb_v = EXTRACT_FIELD(lo, 3, 3);
		tlb_k = EXTRACT_FIELD(lo, 2, 2);
		tlb_w = EXTRACT_FIELD(lo, 1, 1);
		tlb_x = EXTRACT_FIELD(lo, 0, 0);

		/*
		set_exception_vector(0x04, i_mmu_refill);
		set_exception_vector(0x05, i_mmu_invalid);
		set_exception_vector(0x06, i_mmu_access);
		set_exception_vector(0x07, i_mmu_execute);
		set_exception_vector(0x08, d_mmu_refill);
		set_exception_vector(0x09, d_mmu_invalid);
		set_exception_vector(0x0a, d_mmu_access);
		set_exception_vector(0x0b, d_mmu_write);
		*/
		if (cfg_k && tlb_k && usermode) {
			D(printf ("tlb: kernel protected %x lo=%x pc=%x\n", 
				  vaddr, lo, env->pc));
			match = 0;
			res->bf_vec = vect_base + 2;
		} else if (rw == 1 && cfg_w && !tlb_w) {
			D(printf ("tlb: write protected %x lo=%x pc=%x\n", 
				  vaddr, lo, env->pc));
			match = 0;
			/* write accesses never go through the I mmu.  */
			res->bf_vec = vect_base + 3;
		} else if (rw == 2 && cfg_x && !tlb_x) {
			D(printf ("tlb: exec protected %x lo=%x pc=%x\n", 
				 vaddr, lo, env->pc));
			match = 0;
			res->bf_vec = vect_base + 3;
		} else if (cfg_v && !tlb_v) {
			D(printf ("tlb: invalid %x\n", vaddr));
			match = 0;
			res->bf_vec = vect_base + 1;
		}

		res->prot = 0;
		if (match) {
			res->prot |= PAGE_READ;
			if (tlb_w)
				res->prot |= PAGE_WRITE;
			if (tlb_x)
				res->prot |= PAGE_EXEC;
		}
		else
			D(dump_tlb(env, mmu));
	} else {
		/* If refill, provide a randomized set.  */
		set = env->mmu_rand_lfsr & 3;
	}

	if (!match) {
		unsigned int f;

		/* Update lfsr at every fault.  */
		f = compute_polynom(env->mmu_rand_lfsr);
		env->mmu_rand_lfsr >>= 1;
		env->mmu_rand_lfsr |= (f << 15);
		env->mmu_rand_lfsr &= 0xffff;
		
		/* Compute index.  */
		idx = vpage & 15;

		/* Update RW_MM_TLB_SEL.  */
		env->sregs[SFR_RW_MM_TLB_SEL] = 0;
		set_field(&env->sregs[SFR_RW_MM_TLB_SEL], idx, 0, 4);
		set_field(&env->sregs[SFR_RW_MM_TLB_SEL], set, 4, 2);

		/* Update RW_MM_CAUSE.  */
		set_field(&r_cause, rwcause, 8, 2);
		set_field(&r_cause, vpage, 13, 19);
		set_field(&r_cause, pid, 0, 8);
		env->sregs[SFR_R_MM_CAUSE] = r_cause;
		D(printf("refill vaddr=%x pc=%x\n", vaddr, env->pc));
	}

	D(printf ("%s rw=%d mtch=%d pc=%x va=%x vpn=%x tlbvpn=%x pfn=%x pid=%x"
		  " %x cause=%x sel=%x sp=%x %x %x\n",
		  __func__, rw, match, env->pc,
		  vaddr, vpage,
		  tlb_vpn, tlb_pfn, tlb_pid, 
		  pid,
		  r_cause,
		  env->sregs[SFR_RW_MM_TLB_SEL],
		  env->regs[R_SP], env->pregs[PR_USP], env->ksp));

	res->phy = tlb_pfn << TARGET_PAGE_BITS;
	return !match;
}

void cris_mmu_flush_pid(CPUState *env, uint32_t pid)
{
	target_ulong vaddr;
	unsigned int idx;
	uint32_t lo, hi;
	uint32_t tlb_vpn;
	int tlb_pid, tlb_g, tlb_v;
	unsigned int set;
	unsigned int mmu;

	pid &= 0xff;
	for (mmu = 0; mmu < 2; mmu++) {
		for (set = 0; set < 4; set++)
		{
			for (idx = 0; idx < 16; idx++) {
				lo = env->tlbsets[mmu][set][idx].lo;
				hi = env->tlbsets[mmu][set][idx].hi;
				
				tlb_vpn = EXTRACT_FIELD(hi, 13, 31);
				tlb_pid = EXTRACT_FIELD(hi, 0, 7);
				tlb_g  = EXTRACT_FIELD(lo, 4, 4);
				tlb_v = EXTRACT_FIELD(lo, 3, 3);

				if (tlb_v && !tlb_g && (tlb_pid == pid)) {
					vaddr = tlb_vpn << TARGET_PAGE_BITS;
					D_LOG("flush pid=%x vaddr=%x\n", 
						  pid, vaddr);
					tlb_flush_page(env, vaddr);
				}
			}
		}
	}
}

int cris_mmu_translate(struct cris_mmu_result *res,
		       CPUState *env, uint32_t vaddr,
		       int rw, int mmu_idx)
{
	uint32_t phy = vaddr;
	int seg;
	int miss = 0;
	int is_user = mmu_idx == MMU_USER_IDX;
	uint32_t old_srs;

	old_srs= env->pregs[PR_SRS];

	/* rw == 2 means exec, map the access to the insn mmu.  */
	env->pregs[PR_SRS] = rw == 2 ? 1 : 2;

	if (!cris_mmu_enabled(env->sregs[SFR_RW_GC_CFG])) {
		res->phy = vaddr;
		res->prot = PAGE_BITS;
		goto done;
	}

	seg = vaddr >> 28;
	if (cris_mmu_segmented_addr(seg, env->sregs[SFR_RW_MM_CFG]))
	{
		uint32_t base;

		miss = 0;
		base = cris_mmu_translate_seg(env, seg);
		phy = base | (0x0fffffff & vaddr);
		res->phy = phy;
		res->prot = PAGE_BITS;
	}
	else
		miss = cris_mmu_translate_page(res, env, vaddr, rw, is_user);
  done:
	env->pregs[PR_SRS] = old_srs;
	return miss;
}
#endif
Commit	Line	Data
94cff60a TS	1	/*
	2	* CRIS mmu emulation.
	3	*
	4	* Copyright (c) 2007 AXIS Communications AB
	5	* Written by Edgar E. Iglesias.
	6	*
	7	* This library is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU Lesser General Public
	9	* License as published by the Free Software Foundation; either
	10	* version 2 of the License, or (at your option) any later version.
	11	*
	12	* This library is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	15	* Lesser General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU Lesser General Public
8167ee88	18	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
94cff60a TS	19	*/
	20
	21	#ifndef CONFIG_USER_ONLY
	22
	23	#include <stdio.h>
	24	#include <string.h>
	25	#include <stdlib.h>
	26
	27	#include "config.h"
	28	#include "cpu.h"
	29	#include "mmu.h"
	30	#include "exec-all.h"
	31
d297f464 EI	32	#ifdef DEBUG
d297f464 EI	33	#define D(x) x
93fcfe39	34	#define D_LOG(...) qemu_log(__VA__ARGS__)
d297f464	35	#else
786c02f1	36	#define D(x)
d12d51d5	37	#define D_LOG(...) do { } while (0)
d297f464	38	#endif
94cff60a	39
44cd42ee EI	40	void cris_mmu_init(CPUState *env)
	41	{
	42	env->mmu_rand_lfsr = 0xcccc;
	43	}
	44
	45	#define SR_POLYNOM 0x8805
	46	static inline unsigned int compute_polynom(unsigned int sr)
	47	{
	48	unsigned int i;
	49	unsigned int f;
	50
	51	f = 0;
	52	for (i = 0; i < 16; i++)
	53	f += ((SR_POLYNOM >> i) & 1) & ((sr >> i) & 1);
	54
	55	return f;
	56	}
	57
ef29a70d	58	static inline int cris_mmu_enabled(uint32_t rw_gc_cfg)
94cff60a TS	59	{
	60	return (rw_gc_cfg & 12) != 0;
	61	}
	62
ef29a70d	63	static inline int cris_mmu_segmented_addr(int seg, uint32_t rw_mm_cfg)
94cff60a TS	64	{
	65	return (1 << seg) & rw_mm_cfg;
	66	}
	67
	68	static uint32_t cris_mmu_translate_seg(CPUState *env, int seg)
	69	{
	70	uint32_t base;
	71	int i;
	72
	73	if (seg < 8)
	74	base = env->sregs[SFR_RW_MM_KBASE_LO];
	75	else
	76	base = env->sregs[SFR_RW_MM_KBASE_HI];
	77
	78	i = seg & 7;
	79	base >>= i * 4;
	80	base &= 15;
	81
	82	base <<= 28;
	83	return base;
	84	}
	85	/* Used by the tlb decoder. */
	86	#define EXTRACT_FIELD(src, start, end) \
786c02f1 EI	87	(((src) >> start) & ((1 << (end - start + 1)) - 1))
	88
	89	static inline void set_field(uint32_t *dst, unsigned int val,
	90	unsigned int offset, unsigned int width)
	91	{
	92	uint32_t mask;
	93
	94	mask = (1 << width) - 1;
	95	mask <<= offset;
	96	val <<= offset;
	97
	98	val &= mask;
786c02f1 EI	99	*dst &= ~(mask);
	100	*dst \|= val;
	101	}
94cff60a	102
d297f464	103	#ifdef DEBUG
b41f7df0 EI	104	static void dump_tlb(CPUState *env, int mmu)
	105	{
	106	int set;
	107	int idx;
	108	uint32_t hi, lo, tlb_vpn, tlb_pfn;
	109
	110	for (set = 0; set < 4; set++) {
	111	for (idx = 0; idx < 16; idx++) {
	112	lo = env->tlbsets[mmu][set][idx].lo;
	113	hi = env->tlbsets[mmu][set][idx].hi;
	114	tlb_vpn = EXTRACT_FIELD(hi, 13, 31);
	115	tlb_pfn = EXTRACT_FIELD(lo, 13, 31);
	116
	117	printf ("TLB: [%d][%d] hi=%x lo=%x v=%x p=%x\n",
	118	set, idx, hi, lo, tlb_vpn, tlb_pfn);
	119	}
	120	}
	121	}
d297f464	122	#endif
b41f7df0 EI	123
b41f7df0 EI	124	/* rw 0 = read, 1 = write, 2 = exec. */
2fa73ec8	125	static int cris_mmu_translate_page(struct cris_mmu_result *res,
94cff60a TS	126	CPUState *env, uint32_t vaddr,
	127	int rw, int usermode)
	128	{
	129	unsigned int vpage;
	130	unsigned int idx;
b23761f9	131	uint32_t pid, lo, hi;
786c02f1 EI	132	uint32_t tlb_vpn, tlb_pfn = 0;
	133	int tlb_pid, tlb_g, tlb_v, tlb_k, tlb_w, tlb_x;
	134	int cfg_v, cfg_k, cfg_w, cfg_x;
b41f7df0	135	int set, match = 0;
786c02f1 EI	136	uint32_t r_cause;
	137	uint32_t r_cfg;
	138	int rwcause;
b41f7df0 EI	139	int mmu = 1; /* Data mmu is default. */
b41f7df0 EI	140	int vect_base;
786c02f1 EI	141
	142	r_cause = env->sregs[SFR_R_MM_CAUSE];
	143	r_cfg = env->sregs[SFR_RW_MM_CFG];
28de16da	144	pid = env->pregs[PR_PID] & 0xff;
b41f7df0 EI	145
	146	switch (rw) {
	147	case 2: rwcause = CRIS_MMU_ERR_EXEC; mmu = 0; break;
	148	case 1: rwcause = CRIS_MMU_ERR_WRITE; break;
	149	default:
	150	case 0: rwcause = CRIS_MMU_ERR_READ; break;
	151	}
	152
	153	/* I exception vectors 4 - 7, D 8 - 11. */
	154	vect_base = (mmu + 1) * 4;
94cff60a TS	155
94cff60a TS	156	vpage = vaddr >> 13;
94cff60a TS	157
	158	/* We know the index which to check on each set.
	159	Scan both I and D. */
786c02f1	160	#if 0
b41f7df0 EI	161	for (set = 0; set < 4; set++) {
	162	for (idx = 0; idx < 16; idx++) {
	163	lo = env->tlbsets[mmu][set][idx].lo;
	164	hi = env->tlbsets[mmu][set][idx].hi;
786c02f1 EI	165	tlb_vpn = EXTRACT_FIELD(hi, 13, 31);
	166	tlb_pfn = EXTRACT_FIELD(lo, 13, 31);
	167
	168	printf ("TLB: [%d][%d] hi=%x lo=%x v=%x p=%x\n",
b41f7df0	169	set, idx, hi, lo, tlb_vpn, tlb_pfn);
786c02f1 EI	170	}
	171	}
	172	#endif
b41f7df0 EI	173
	174	idx = vpage & 15;
	175	for (set = 0; set < 4; set++)
94cff60a	176	{
b41f7df0 EI	177	lo = env->tlbsets[mmu][set][idx].lo;
b41f7df0 EI	178	hi = env->tlbsets[mmu][set][idx].hi;
94cff60a	179
b23761f9	180	tlb_vpn = hi >> 13;
44cd42ee	181	tlb_pid = EXTRACT_FIELD(hi, 0, 7);
44cd42ee	182	tlb_g = EXTRACT_FIELD(lo, 4, 4);
94cff60a	183
d12d51d5 AL	184	D_LOG("TLB[%d][%d][%d] v=%x vpage=%x lo=%x hi=%x\n",
d12d51d5 AL	185	mmu, set, idx, tlb_vpn, vpage, lo, hi);
b23761f9	186	if ((tlb_g \|\| (tlb_pid == pid))
44cd42ee	187	&& tlb_vpn == vpage) {
94cff60a TS	188	match = 1;
	189	break;
	190	}
	191	}
	192
b41f7df0	193	res->bf_vec = vect_base;
94cff60a	194	if (match) {
786c02f1 EI	195	cfg_w = EXTRACT_FIELD(r_cfg, 19, 19);
	196	cfg_k = EXTRACT_FIELD(r_cfg, 18, 18);
	197	cfg_x = EXTRACT_FIELD(r_cfg, 17, 17);
	198	cfg_v = EXTRACT_FIELD(r_cfg, 16, 16);
	199
786c02f1	200	tlb_pfn = EXTRACT_FIELD(lo, 13, 31);
786c02f1 EI	201	tlb_v = EXTRACT_FIELD(lo, 3, 3);
	202	tlb_k = EXTRACT_FIELD(lo, 2, 2);
	203	tlb_w = EXTRACT_FIELD(lo, 1, 1);
	204	tlb_x = EXTRACT_FIELD(lo, 0, 0);
	205
	206	/*
	207	set_exception_vector(0x04, i_mmu_refill);
	208	set_exception_vector(0x05, i_mmu_invalid);
	209	set_exception_vector(0x06, i_mmu_access);
	210	set_exception_vector(0x07, i_mmu_execute);
	211	set_exception_vector(0x08, d_mmu_refill);
	212	set_exception_vector(0x09, d_mmu_invalid);
	213	set_exception_vector(0x0a, d_mmu_access);
	214	set_exception_vector(0x0b, d_mmu_write);
	215	*/
44cd42ee	216	if (cfg_k && tlb_k && usermode) {
ef29a70d EI	217	D(printf ("tlb: kernel protected %x lo=%x pc=%x\n",
	218	vaddr, lo, env->pc));
	219	match = 0;
	220	res->bf_vec = vect_base + 2;
b41f7df0	221	} else if (rw == 1 && cfg_w && !tlb_w) {
ef29a70d EI	222	D(printf ("tlb: write protected %x lo=%x pc=%x\n",
	223	vaddr, lo, env->pc));
	224	match = 0;
	225	/* write accesses never go through the I mmu. */
	226	res->bf_vec = vect_base + 3;
	227	} else if (rw == 2 && cfg_x && !tlb_x) {
	228	D(printf ("tlb: exec protected %x lo=%x pc=%x\n",
	229	vaddr, lo, env->pc));
786c02f1	230	match = 0;
b41f7df0 EI	231	res->bf_vec = vect_base + 3;
	232	} else if (cfg_v && !tlb_v) {
	233	D(printf ("tlb: invalid %x\n", vaddr));
786c02f1	234	match = 0;
b41f7df0	235	res->bf_vec = vect_base + 1;
786c02f1	236	}
786c02f1	237
b41f7df0 EI	238	res->prot = 0;
	239	if (match) {
	240	res->prot \|= PAGE_READ;
	241	if (tlb_w)
	242	res->prot \|= PAGE_WRITE;
	243	if (tlb_x)
	244	res->prot \|= PAGE_EXEC;
	245	}
	246	else
	247	D(dump_tlb(env, mmu));
44cd42ee EI	248	} else {
	249	/* If refill, provide a randomized set. */
	250	set = env->mmu_rand_lfsr & 3;
786c02f1 EI	251	}
	252
	253	if (!match) {
44cd42ee EI	254	unsigned int f;
	255
	256	/* Update lfsr at every fault. */
	257	f = compute_polynom(env->mmu_rand_lfsr);
	258	env->mmu_rand_lfsr >>= 1;
	259	env->mmu_rand_lfsr \|= (f << 15);
	260	env->mmu_rand_lfsr &= 0xffff;
	261
	262	/* Compute index. */
b41f7df0	263	idx = vpage & 15;
b41f7df0 EI	264
	265	/* Update RW_MM_TLB_SEL. */
	266	env->sregs[SFR_RW_MM_TLB_SEL] = 0;
	267	set_field(&env->sregs[SFR_RW_MM_TLB_SEL], idx, 0, 4);
44cd42ee	268	set_field(&env->sregs[SFR_RW_MM_TLB_SEL], set, 4, 2);
b41f7df0 EI	269
	270	/* Update RW_MM_CAUSE. */
	271	set_field(&r_cause, rwcause, 8, 2);
786c02f1	272	set_field(&r_cause, vpage, 13, 19);
28de16da	273	set_field(&r_cause, pid, 0, 8);
786c02f1	274	env->sregs[SFR_R_MM_CAUSE] = r_cause;
b41f7df0	275	D(printf("refill vaddr=%x pc=%x\n", vaddr, env->pc));
94cff60a	276	}
b41f7df0	277
b41f7df0 EI	278	D(printf ("%s rw=%d mtch=%d pc=%x va=%x vpn=%x tlbvpn=%x pfn=%x pid=%x"
	279	" %x cause=%x sel=%x sp=%x %x %x\n",
	280	__func__, rw, match, env->pc,
786c02f1 EI	281	vaddr, vpage,
786c02f1 EI	282	tlb_vpn, tlb_pfn, tlb_pid,
28de16da	283	pid,
786c02f1 EI	284	r_cause,
786c02f1 EI	285	env->sregs[SFR_RW_MM_TLB_SEL],
b41f7df0	286	env->regs[R_SP], env->pregs[PR_USP], env->ksp));
786c02f1	287
bf91ada5	288	res->phy = tlb_pfn << TARGET_PAGE_BITS;
94cff60a TS	289	return !match;
	290	}
	291
cf1d97f0	292	void cris_mmu_flush_pid(CPUState *env, uint32_t pid)
786c02f1	293	{
cf1d97f0 EI	294	target_ulong vaddr;
	295	unsigned int idx;
	296	uint32_t lo, hi;
	297	uint32_t tlb_vpn;
80e1b265	298	int tlb_pid, tlb_g, tlb_v;
cf1d97f0 EI	299	unsigned int set;
	300	unsigned int mmu;
	301
	302	pid &= 0xff;
	303	for (mmu = 0; mmu < 2; mmu++) {
	304	for (set = 0; set < 4; set++)
	305	{
	306	for (idx = 0; idx < 16; idx++) {
	307	lo = env->tlbsets[mmu][set][idx].lo;
	308	hi = env->tlbsets[mmu][set][idx].hi;
	309
	310	tlb_vpn = EXTRACT_FIELD(hi, 13, 31);
	311	tlb_pid = EXTRACT_FIELD(hi, 0, 7);
	312	tlb_g = EXTRACT_FIELD(lo, 4, 4);
	313	tlb_v = EXTRACT_FIELD(lo, 3, 3);
cf1d97f0	314
80e1b265	315	if (tlb_v && !tlb_g && (tlb_pid == pid)) {
cf1d97f0	316	vaddr = tlb_vpn << TARGET_PAGE_BITS;
d12d51d5 AL	317	D_LOG("flush pid=%x vaddr=%x\n",
d12d51d5 AL	318	pid, vaddr);
cf1d97f0 EI	319	tlb_flush_page(env, vaddr);
	320	}
	321	}
	322	}
	323	}
786c02f1 EI	324	}
786c02f1 EI	325
2fa73ec8	326	int cris_mmu_translate(struct cris_mmu_result *res,
94cff60a	327	CPUState *env, uint32_t vaddr,
6ebbf390	328	int rw, int mmu_idx)
94cff60a TS	329	{
	330	uint32_t phy = vaddr;
	331	int seg;
	332	int miss = 0;
786c02f1	333	int is_user = mmu_idx == MMU_USER_IDX;
b41f7df0 EI	334	uint32_t old_srs;
	335
	336	old_srs= env->pregs[PR_SRS];
	337
	338	/* rw == 2 means exec, map the access to the insn mmu. */
	339	env->pregs[PR_SRS] = rw == 2 ? 1 : 2;
94cff60a TS	340
	341	if (!cris_mmu_enabled(env->sregs[SFR_RW_GC_CFG])) {
	342	res->phy = vaddr;
b23761f9	343	res->prot = PAGE_BITS;
b41f7df0	344	goto done;
94cff60a TS	345	}
	346
	347	seg = vaddr >> 28;
	348	if (cris_mmu_segmented_addr(seg, env->sregs[SFR_RW_MM_CFG]))
	349	{
	350	uint32_t base;
	351
	352	miss = 0;
	353	base = cris_mmu_translate_seg(env, seg);
	354	phy = base \| (0x0fffffff & vaddr);
	355	res->phy = phy;
b23761f9	356	res->prot = PAGE_BITS;
94cff60a TS	357	}
94cff60a TS	358	else
94cff60a	359	miss = cris_mmu_translate_page(res, env, vaddr, rw, is_user);
b41f7df0 EI	360	done:
b41f7df0 EI	361	env->pregs[PR_SRS] = old_srs;
94cff60a TS	362	return miss;
	363	}
	364	#endif