[qemu.git] / hw / vga_int.h

/*
 * QEMU internal VGA defines.
 *
 * Copyright (c) 2003-2004 Fabrice Bellard
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */

#include <hw/hw.h>

#define MSR_COLOR_EMULATION 0x01
#define MSR_PAGE_SELECT     0x20

#define ST01_V_RETRACE      0x08
#define ST01_DISP_ENABLE    0x01

/* bochs VBE support */
#define CONFIG_BOCHS_VBE

#define VBE_DISPI_MAX_XRES              1600
#define VBE_DISPI_MAX_YRES              1200
#define VBE_DISPI_MAX_BPP               32

#define VBE_DISPI_INDEX_ID              0x0
#define VBE_DISPI_INDEX_XRES            0x1
#define VBE_DISPI_INDEX_YRES            0x2
#define VBE_DISPI_INDEX_BPP             0x3
#define VBE_DISPI_INDEX_ENABLE          0x4
#define VBE_DISPI_INDEX_BANK            0x5
#define VBE_DISPI_INDEX_VIRT_WIDTH      0x6
#define VBE_DISPI_INDEX_VIRT_HEIGHT     0x7
#define VBE_DISPI_INDEX_X_OFFSET        0x8
#define VBE_DISPI_INDEX_Y_OFFSET        0x9
#define VBE_DISPI_INDEX_NB              0xa /* size of vbe_regs[] */
#define VBE_DISPI_INDEX_VIDEO_MEMORY_64K 0xa /* read-only, not in vbe_regs */

#define VBE_DISPI_ID0                   0xB0C0
#define VBE_DISPI_ID1                   0xB0C1
#define VBE_DISPI_ID2                   0xB0C2
#define VBE_DISPI_ID3                   0xB0C3
#define VBE_DISPI_ID4                   0xB0C4
#define VBE_DISPI_ID5                   0xB0C5

#define VBE_DISPI_DISABLED              0x00
#define VBE_DISPI_ENABLED               0x01
#define VBE_DISPI_GETCAPS               0x02
#define VBE_DISPI_8BIT_DAC              0x20
#define VBE_DISPI_LFB_ENABLED           0x40
#define VBE_DISPI_NOCLEARMEM            0x80

#define VBE_DISPI_LFB_PHYSICAL_ADDRESS  0xE0000000

#ifdef CONFIG_BOCHS_VBE

#define VGA_STATE_COMMON_BOCHS_VBE              \
    uint16_t vbe_index;                         \
    uint16_t vbe_regs[VBE_DISPI_INDEX_NB];      \
    uint32_t vbe_start_addr;                    \
    uint32_t vbe_line_offset;                   \
    uint32_t vbe_bank_mask;			\
    int vbe_mapped;
#else

#define VGA_STATE_COMMON_BOCHS_VBE

#endif /* !CONFIG_BOCHS_VBE */

#define CH_ATTR_SIZE (160 * 100)
#define VGA_MAX_HEIGHT 2048

struct vga_precise_retrace {
    int64_t ticks_per_char;
    int64_t total_chars;
    int htotal;
    int hstart;
    int hend;
    int vstart;
    int vend;
    int freq;
};

union vga_retrace {
    struct vga_precise_retrace precise;
};

struct VGACommonState;
typedef uint8_t (* vga_retrace_fn)(struct VGACommonState *s);
typedef void (* vga_update_retrace_info_fn)(struct VGACommonState *s);

typedef struct VGACommonState {
    uint8_t *vram_ptr;
    ram_addr_t vram_offset;
    target_phys_addr_t lfb_addr;
    target_phys_addr_t lfb_end;
    target_phys_addr_t map_addr;
    target_phys_addr_t map_end;
    uint32_t vram_size;
    uint32_t latch;
    uint32_t lfb_vram_mapped; /* whether 0xa0000 is mapped as ram */
    uint8_t sr_index;
    uint8_t sr[256];
    uint8_t gr_index;
    uint8_t gr[256];
    uint8_t ar_index;
    uint8_t ar[21];
    int ar_flip_flop;
    uint8_t cr_index;
    uint8_t cr[256]; /* CRT registers */
    uint8_t msr; /* Misc Output Register */
    uint8_t fcr; /* Feature Control Register */
    uint8_t st00; /* status 0 */
    uint8_t st01; /* status 1 */
    uint8_t dac_state;
    uint8_t dac_sub_index;
    uint8_t dac_read_index;
    uint8_t dac_write_index;
    uint8_t dac_cache[3]; /* used when writing */
    int dac_8bit;
    uint8_t palette[768];
    int32_t bank_offset;
    int vga_io_memory;
    int (*get_bpp)(struct VGACommonState *s);
    void (*get_offsets)(struct VGACommonState *s,
                        uint32_t *pline_offset,
                        uint32_t *pstart_addr,
                        uint32_t *pline_compare);
    void (*get_resolution)(struct VGACommonState *s,
                        int *pwidth,
                        int *pheight);
    VGA_STATE_COMMON_BOCHS_VBE
    /* display refresh support */
    DisplayState *ds;
    uint32_t font_offsets[2];
    int graphic_mode;
    uint8_t shift_control;
    uint8_t double_scan;
    uint32_t line_offset;
    uint32_t line_compare;
    uint32_t start_addr;
    uint32_t plane_updated;
    uint32_t last_line_offset;
    uint8_t last_cw, last_ch;
    uint32_t last_width, last_height; /* in chars or pixels */
    uint32_t last_scr_width, last_scr_height; /* in pixels */
    uint32_t last_depth; /* in bits */
    uint8_t cursor_start, cursor_end;
    uint32_t cursor_offset;
    unsigned int (*rgb_to_pixel)(unsigned int r,
                                 unsigned int g, unsigned b);
    vga_hw_update_ptr update;
    vga_hw_invalidate_ptr invalidate;
    vga_hw_screen_dump_ptr screen_dump;
    vga_hw_text_update_ptr text_update;
    /* hardware mouse cursor support */
    uint32_t invalidated_y_table[VGA_MAX_HEIGHT / 32];
    void (*cursor_invalidate)(struct VGACommonState *s);
    void (*cursor_draw_line)(struct VGACommonState *s, uint8_t *d, int y);
    /* tell for each page if it has been updated since the last time */
    uint32_t last_palette[256];
    uint32_t last_ch_attr[CH_ATTR_SIZE]; /* XXX: make it dynamic */
    /* retrace */
    vga_retrace_fn retrace;
    vga_update_retrace_info_fn update_retrace_info;
    union vga_retrace retrace_info;
    uint8_t is_vbe_vmstate;
} VGACommonState;

static inline int c6_to_8(int v)
{
    int b;
    v &= 0x3f;
    b = v & 1;
    return (v << 2) | (b << 1) | b;
}

void vga_common_init(VGACommonState *s, int vga_ram_size);
void vga_init(VGACommonState *s);
int vga_init_io(VGACommonState *s);
void vga_common_reset(VGACommonState *s);

void vga_dirty_log_start(VGACommonState *s);
void vga_dirty_log_stop(VGACommonState *s);
void vga_dirty_log_restart(VGACommonState *s);

extern const VMStateDescription vmstate_vga_common;
uint32_t vga_ioport_read(void *opaque, uint32_t addr);
void vga_ioport_write(void *opaque, uint32_t addr, uint32_t val);
uint32_t vga_mem_readb(void *opaque, target_phys_addr_t addr);
void vga_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val);
void vga_invalidate_scanlines(VGACommonState *s, int y1, int y2);
int ppm_save(const char *filename, struct DisplaySurface *ds);

void vga_draw_cursor_line_8(uint8_t *d1, const uint8_t *src1,
                            int poffset, int w,
                            unsigned int color0, unsigned int color1,
                            unsigned int color_xor);
void vga_draw_cursor_line_16(uint8_t *d1, const uint8_t *src1,
                             int poffset, int w,
                             unsigned int color0, unsigned int color1,
                             unsigned int color_xor);
void vga_draw_cursor_line_32(uint8_t *d1, const uint8_t *src1,
                             int poffset, int w,
                             unsigned int color0, unsigned int color1,
                             unsigned int color_xor);

int vga_ioport_invalid(VGACommonState *s, uint32_t addr);
void vga_init_vbe(VGACommonState *s);

extern const uint8_t sr_mask[8];
extern const uint8_t gr_mask[16];

#define VGA_RAM_SIZE (8192 * 1024)
#define VGABIOS_FILENAME "vgabios.bin"
#define VGABIOS_CIRRUS_FILENAME "vgabios-cirrus.bin"

extern CPUReadMemoryFunc * const vga_mem_read[3];
extern CPUWriteMemoryFunc * const vga_mem_write[3];
Commit	Line	Data
798b0c25 FB	1	/*
798b0c25 FB	2	* QEMU internal VGA defines.
5fafdf24	3	*
798b0c25	4	* Copyright (c) 2003-2004 Fabrice Bellard
5fafdf24	5	*
798b0c25 FB	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
11b6b345 JQ	24
	25	#include <hw/hw.h>
	26
798b0c25 FB	27	#define MSR_COLOR_EMULATION 0x01
	28	#define MSR_PAGE_SELECT 0x20
	29
	30	#define ST01_V_RETRACE 0x08
	31	#define ST01_DISP_ENABLE 0x01
	32
	33	/* bochs VBE support */
	34	#define CONFIG_BOCHS_VBE
	35
8454df8b FB	36	#define VBE_DISPI_MAX_XRES 1600
	37	#define VBE_DISPI_MAX_YRES 1200
	38	#define VBE_DISPI_MAX_BPP 32
798b0c25 FB	39
	40	#define VBE_DISPI_INDEX_ID 0x0
	41	#define VBE_DISPI_INDEX_XRES 0x1
	42	#define VBE_DISPI_INDEX_YRES 0x2
	43	#define VBE_DISPI_INDEX_BPP 0x3
	44	#define VBE_DISPI_INDEX_ENABLE 0x4
	45	#define VBE_DISPI_INDEX_BANK 0x5
	46	#define VBE_DISPI_INDEX_VIRT_WIDTH 0x6
	47	#define VBE_DISPI_INDEX_VIRT_HEIGHT 0x7
	48	#define VBE_DISPI_INDEX_X_OFFSET 0x8
	49	#define VBE_DISPI_INDEX_Y_OFFSET 0x9
af92284b GH	50	#define VBE_DISPI_INDEX_NB 0xa /* size of vbe_regs[] */
af92284b GH	51	#define VBE_DISPI_INDEX_VIDEO_MEMORY_64K 0xa /* read-only, not in vbe_regs */
3b46e624	52
798b0c25 FB	53	#define VBE_DISPI_ID0 0xB0C0
	54	#define VBE_DISPI_ID1 0xB0C1
	55	#define VBE_DISPI_ID2 0xB0C2
37dd208d FB	56	#define VBE_DISPI_ID3 0xB0C3
37dd208d FB	57	#define VBE_DISPI_ID4 0xB0C4
af92284b	58	#define VBE_DISPI_ID5 0xB0C5
3b46e624	59
798b0c25 FB	60	#define VBE_DISPI_DISABLED 0x00
798b0c25 FB	61	#define VBE_DISPI_ENABLED 0x01
8454df8b FB	62	#define VBE_DISPI_GETCAPS 0x02
8454df8b FB	63	#define VBE_DISPI_8BIT_DAC 0x20
798b0c25 FB	64	#define VBE_DISPI_LFB_ENABLED 0x40
798b0c25 FB	65	#define VBE_DISPI_NOCLEARMEM 0x80
3b46e624	66
798b0c25 FB	67	#define VBE_DISPI_LFB_PHYSICAL_ADDRESS 0xE0000000
798b0c25 FB	68
798b0c25	69	#ifdef CONFIG_BOCHS_VBE
4e3e9d0b FB	70
	71	#define VGA_STATE_COMMON_BOCHS_VBE \
	72	uint16_t vbe_index; \
	73	uint16_t vbe_regs[VBE_DISPI_INDEX_NB]; \
	74	uint32_t vbe_start_addr; \
	75	uint32_t vbe_line_offset; \
f0138a63 AL	76	uint32_t vbe_bank_mask; \
f0138a63 AL	77	int vbe_mapped;
4e3e9d0b FB	78	#else
	79
	80	#define VGA_STATE_COMMON_BOCHS_VBE
	81
	82	#endif /* !CONFIG_BOCHS_VBE */
	83
798b0c25	84	#define CH_ATTR_SIZE (160 * 100)
8454df8b	85	#define VGA_MAX_HEIGHT 2048
4e3e9d0b	86
cb5a7aa8	87	struct vga_precise_retrace {
	88	int64_t ticks_per_char;
	89	int64_t total_chars;
	90	int htotal;
	91	int hstart;
	92	int hend;
	93	int vstart;
	94	int vend;
	95	int freq;
	96	};
	97
	98	union vga_retrace {
	99	struct vga_precise_retrace precise;
	100	};
	101
4e12cd94 AK	102	struct VGACommonState;
	103	typedef uint8_t (* vga_retrace_fn)(struct VGACommonState *s);
	104	typedef void (* vga_update_retrace_info_fn)(struct VGACommonState *s);
	105
	106	typedef struct VGACommonState {
	107	uint8_t *vram_ptr;
c227f099	108	ram_addr_t vram_offset;
0fe28e0d RH	109	target_phys_addr_t lfb_addr;
	110	target_phys_addr_t lfb_end;
	111	target_phys_addr_t map_addr;
	112	target_phys_addr_t map_end;
a19cbfb3	113	uint32_t vram_size;
4e12cd94	114	uint32_t latch;
0fe28e0d	115	uint32_t lfb_vram_mapped; /* whether 0xa0000 is mapped as ram */
4e12cd94 AK	116	uint8_t sr_index;
	117	uint8_t sr[256];
	118	uint8_t gr_index;
	119	uint8_t gr[256];
	120	uint8_t ar_index;
	121	uint8_t ar[21];
	122	int ar_flip_flop;
	123	uint8_t cr_index;
	124	uint8_t cr[256]; /* CRT registers */
	125	uint8_t msr; /* Misc Output Register */
	126	uint8_t fcr; /* Feature Control Register */
	127	uint8_t st00; /* status 0 */
	128	uint8_t st01; /* status 1 */
	129	uint8_t dac_state;
	130	uint8_t dac_sub_index;
	131	uint8_t dac_read_index;
	132	uint8_t dac_write_index;
	133	uint8_t dac_cache[3]; /* used when writing */
	134	int dac_8bit;
	135	uint8_t palette[768];
	136	int32_t bank_offset;
	137	int vga_io_memory;
	138	int (get_bpp)(struct VGACommonState s);
	139	void (get_offsets)(struct VGACommonState s,
	140	uint32_t *pline_offset,
	141	uint32_t *pstart_addr,
	142	uint32_t *pline_compare);
	143	void (get_resolution)(struct VGACommonState s,
	144	int *pwidth,
	145	int *pheight);
	146	VGA_STATE_COMMON_BOCHS_VBE
	147	/* display refresh support */
	148	DisplayState *ds;
	149	uint32_t font_offsets[2];
	150	int graphic_mode;
	151	uint8_t shift_control;
	152	uint8_t double_scan;
	153	uint32_t line_offset;
	154	uint32_t line_compare;
	155	uint32_t start_addr;
	156	uint32_t plane_updated;
	157	uint32_t last_line_offset;
	158	uint8_t last_cw, last_ch;
	159	uint32_t last_width, last_height; /* in chars or pixels */
	160	uint32_t last_scr_width, last_scr_height; /* in pixels */
	161	uint32_t last_depth; /* in bits */
	162	uint8_t cursor_start, cursor_end;
	163	uint32_t cursor_offset;
	164	unsigned int (*rgb_to_pixel)(unsigned int r,
	165	unsigned int g, unsigned b);
	166	vga_hw_update_ptr update;
	167	vga_hw_invalidate_ptr invalidate;
	168	vga_hw_screen_dump_ptr screen_dump;
	169	vga_hw_text_update_ptr text_update;
	170	/* hardware mouse cursor support */
	171	uint32_t invalidated_y_table[VGA_MAX_HEIGHT / 32];
	172	void (cursor_invalidate)(struct VGACommonState s);
	173	void (cursor_draw_line)(struct VGACommonState s, uint8_t *d, int y);
	174	/* tell for each page if it has been updated since the last time */
	175	uint32_t last_palette[256];
	176	uint32_t last_ch_attr[CH_ATTR_SIZE]; /* XXX: make it dynamic */
	177	/* retrace */
	178	vga_retrace_fn retrace;
	179	vga_update_retrace_info_fn update_retrace_info;
cb5a7aa8	180	union vga_retrace retrace_info;
2a3138ab	181	uint8_t is_vbe_vmstate;
4e12cd94	182	} VGACommonState;
4e3e9d0b	183
a8aa669b FB	184	static inline int c6_to_8(int v)
	185	{
	186	int b;
	187	v &= 0x3f;
	188	b = v & 1;
	189	return (v << 2) \| (b << 1) \| b;
	190	}
	191
a4a2f59c JQ	192	void vga_common_init(VGACommonState *s, int vga_ram_size);
a4a2f59c JQ	193	void vga_init(VGACommonState *s);
7435b791	194	int vga_init_io(VGACommonState *s);
03a3e7ba	195	void vga_common_reset(VGACommonState *s);
2bec46dc	196
a4a2f59c	197	void vga_dirty_log_start(VGACommonState *s);
b5cc6e32 AL	198	void vga_dirty_log_stop(VGACommonState *s);
b5cc6e32 AL	199	void vga_dirty_log_restart(VGACommonState *s);
2bec46dc	200
11b6b345	201	extern const VMStateDescription vmstate_vga_common;
43bf782b JQ	202	uint32_t vga_ioport_read(void *opaque, uint32_t addr);
43bf782b JQ	203	void vga_ioport_write(void *opaque, uint32_t addr, uint32_t val);
c227f099 AL	204	uint32_t vga_mem_readb(void *opaque, target_phys_addr_t addr);
c227f099 AL	205	void vga_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val);
a4a2f59c	206	void vga_invalidate_scanlines(VGACommonState *s, int y1, int y2);
e07d630a	207	int ppm_save(const char filename, struct DisplaySurface ds);
a8aa669b	208
5fafdf24 TS	209	void vga_draw_cursor_line_8(uint8_t d1, const uint8_t src1,
5fafdf24 TS	210	int poffset, int w,
a8aa669b FB	211	unsigned int color0, unsigned int color1,
a8aa669b FB	212	unsigned int color_xor);
5fafdf24 TS	213	void vga_draw_cursor_line_16(uint8_t d1, const uint8_t src1,
5fafdf24 TS	214	int poffset, int w,
a8aa669b FB	215	unsigned int color0, unsigned int color1,
a8aa669b FB	216	unsigned int color_xor);
5fafdf24 TS	217	void vga_draw_cursor_line_32(uint8_t d1, const uint8_t src1,
5fafdf24 TS	218	int poffset, int w,
a8aa669b FB	219	unsigned int color0, unsigned int color1,
a8aa669b FB	220	unsigned int color_xor);
798b0c25	221
25a18cbd	222	int vga_ioport_invalid(VGACommonState *s, uint32_t addr);
f0138a63	223	void vga_init_vbe(VGACommonState *s);
25a18cbd	224
798b0c25 FB	225	extern const uint8_t sr_mask[8];
798b0c25 FB	226	extern const uint8_t gr_mask[16];
fbe1b595 PB	227
fbe1b595 PB	228	#define VGA_RAM_SIZE (8192 * 1024)
5245d57a GH	229	#define VGABIOS_FILENAME "vgabios.bin"
5245d57a GH	230	#define VGABIOS_CIRRUS_FILENAME "vgabios-cirrus.bin"
fbe1b595	231
f97e36b9 JQ	232	extern CPUReadMemoryFunc * const vga_mem_read[3];
f97e36b9 JQ	233	extern CPUWriteMemoryFunc * const vga_mem_write[3];