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1 | /* |
2 | * x86 condition code helpers | |
3 | * | |
4 | * Copyright (c) 2003 Fabrice Bellard | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
20 | #include "cpu.h" | |
5918fffb BS |
21 | #include "helper.h" |
22 | ||
23 | const uint8_t parity_table[256] = { | |
24 | CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0, | |
25 | 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P, | |
26 | 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P, | |
27 | CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0, | |
28 | 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P, | |
29 | CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0, | |
30 | CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0, | |
31 | 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P, | |
32 | 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P, | |
33 | CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0, | |
34 | CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0, | |
35 | 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P, | |
36 | CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0, | |
37 | 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P, | |
38 | 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P, | |
39 | CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0, | |
40 | 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P, | |
41 | CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0, | |
42 | CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0, | |
43 | 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P, | |
44 | CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0, | |
45 | 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P, | |
46 | 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P, | |
47 | CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0, | |
48 | CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0, | |
49 | 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P, | |
50 | 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P, | |
51 | CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0, | |
52 | 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P, | |
53 | CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0, | |
54 | CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0, | |
55 | 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P, | |
56 | }; | |
57 | ||
58 | #define SHIFT 0 | |
59 | #include "cc_helper_template.h" | |
60 | #undef SHIFT | |
61 | ||
62 | #define SHIFT 1 | |
63 | #include "cc_helper_template.h" | |
64 | #undef SHIFT | |
65 | ||
66 | #define SHIFT 2 | |
67 | #include "cc_helper_template.h" | |
68 | #undef SHIFT | |
69 | ||
70 | #ifdef TARGET_X86_64 | |
71 | ||
72 | #define SHIFT 3 | |
73 | #include "cc_helper_template.h" | |
74 | #undef SHIFT | |
75 | ||
76 | #endif | |
77 | ||
f0967a1a | 78 | static int compute_all_eflags(CPUX86State *env) |
5918fffb BS |
79 | { |
80 | return CC_SRC; | |
81 | } | |
82 | ||
f0967a1a | 83 | static int compute_c_eflags(CPUX86State *env) |
5918fffb BS |
84 | { |
85 | return CC_SRC & CC_C; | |
86 | } | |
87 | ||
f0967a1a | 88 | uint32_t helper_cc_compute_all(CPUX86State *env, int op) |
5918fffb BS |
89 | { |
90 | switch (op) { | |
91 | default: /* should never happen */ | |
92 | return 0; | |
93 | ||
94 | case CC_OP_EFLAGS: | |
f0967a1a | 95 | return compute_all_eflags(env); |
5918fffb BS |
96 | |
97 | case CC_OP_MULB: | |
f0967a1a | 98 | return compute_all_mulb(env); |
5918fffb | 99 | case CC_OP_MULW: |
f0967a1a | 100 | return compute_all_mulw(env); |
5918fffb | 101 | case CC_OP_MULL: |
f0967a1a | 102 | return compute_all_mull(env); |
5918fffb BS |
103 | |
104 | case CC_OP_ADDB: | |
f0967a1a | 105 | return compute_all_addb(env); |
5918fffb | 106 | case CC_OP_ADDW: |
f0967a1a | 107 | return compute_all_addw(env); |
5918fffb | 108 | case CC_OP_ADDL: |
f0967a1a | 109 | return compute_all_addl(env); |
5918fffb BS |
110 | |
111 | case CC_OP_ADCB: | |
f0967a1a | 112 | return compute_all_adcb(env); |
5918fffb | 113 | case CC_OP_ADCW: |
f0967a1a | 114 | return compute_all_adcw(env); |
5918fffb | 115 | case CC_OP_ADCL: |
f0967a1a | 116 | return compute_all_adcl(env); |
5918fffb BS |
117 | |
118 | case CC_OP_SUBB: | |
f0967a1a | 119 | return compute_all_subb(env); |
5918fffb | 120 | case CC_OP_SUBW: |
f0967a1a | 121 | return compute_all_subw(env); |
5918fffb | 122 | case CC_OP_SUBL: |
f0967a1a | 123 | return compute_all_subl(env); |
5918fffb BS |
124 | |
125 | case CC_OP_SBBB: | |
f0967a1a | 126 | return compute_all_sbbb(env); |
5918fffb | 127 | case CC_OP_SBBW: |
f0967a1a | 128 | return compute_all_sbbw(env); |
5918fffb | 129 | case CC_OP_SBBL: |
f0967a1a | 130 | return compute_all_sbbl(env); |
5918fffb BS |
131 | |
132 | case CC_OP_LOGICB: | |
f0967a1a | 133 | return compute_all_logicb(env); |
5918fffb | 134 | case CC_OP_LOGICW: |
f0967a1a | 135 | return compute_all_logicw(env); |
5918fffb | 136 | case CC_OP_LOGICL: |
f0967a1a | 137 | return compute_all_logicl(env); |
5918fffb BS |
138 | |
139 | case CC_OP_INCB: | |
f0967a1a | 140 | return compute_all_incb(env); |
5918fffb | 141 | case CC_OP_INCW: |
f0967a1a | 142 | return compute_all_incw(env); |
5918fffb | 143 | case CC_OP_INCL: |
f0967a1a | 144 | return compute_all_incl(env); |
5918fffb BS |
145 | |
146 | case CC_OP_DECB: | |
f0967a1a | 147 | return compute_all_decb(env); |
5918fffb | 148 | case CC_OP_DECW: |
f0967a1a | 149 | return compute_all_decw(env); |
5918fffb | 150 | case CC_OP_DECL: |
f0967a1a | 151 | return compute_all_decl(env); |
5918fffb BS |
152 | |
153 | case CC_OP_SHLB: | |
f0967a1a | 154 | return compute_all_shlb(env); |
5918fffb | 155 | case CC_OP_SHLW: |
f0967a1a | 156 | return compute_all_shlw(env); |
5918fffb | 157 | case CC_OP_SHLL: |
f0967a1a | 158 | return compute_all_shll(env); |
5918fffb BS |
159 | |
160 | case CC_OP_SARB: | |
f0967a1a | 161 | return compute_all_sarb(env); |
5918fffb | 162 | case CC_OP_SARW: |
f0967a1a | 163 | return compute_all_sarw(env); |
5918fffb | 164 | case CC_OP_SARL: |
f0967a1a | 165 | return compute_all_sarl(env); |
5918fffb BS |
166 | |
167 | #ifdef TARGET_X86_64 | |
168 | case CC_OP_MULQ: | |
f0967a1a | 169 | return compute_all_mulq(env); |
5918fffb BS |
170 | |
171 | case CC_OP_ADDQ: | |
f0967a1a | 172 | return compute_all_addq(env); |
5918fffb BS |
173 | |
174 | case CC_OP_ADCQ: | |
f0967a1a | 175 | return compute_all_adcq(env); |
5918fffb BS |
176 | |
177 | case CC_OP_SUBQ: | |
f0967a1a | 178 | return compute_all_subq(env); |
5918fffb BS |
179 | |
180 | case CC_OP_SBBQ: | |
f0967a1a | 181 | return compute_all_sbbq(env); |
5918fffb BS |
182 | |
183 | case CC_OP_LOGICQ: | |
f0967a1a | 184 | return compute_all_logicq(env); |
5918fffb BS |
185 | |
186 | case CC_OP_INCQ: | |
f0967a1a | 187 | return compute_all_incq(env); |
5918fffb BS |
188 | |
189 | case CC_OP_DECQ: | |
f0967a1a | 190 | return compute_all_decq(env); |
5918fffb BS |
191 | |
192 | case CC_OP_SHLQ: | |
f0967a1a | 193 | return compute_all_shlq(env); |
5918fffb BS |
194 | |
195 | case CC_OP_SARQ: | |
f0967a1a | 196 | return compute_all_sarq(env); |
5918fffb BS |
197 | #endif |
198 | } | |
199 | } | |
200 | ||
f0967a1a | 201 | uint32_t cpu_cc_compute_all(CPUX86State *env, int op) |
5918fffb | 202 | { |
f0967a1a | 203 | return helper_cc_compute_all(env, op); |
5918fffb BS |
204 | } |
205 | ||
f0967a1a | 206 | uint32_t helper_cc_compute_c(CPUX86State *env, int op) |
5918fffb BS |
207 | { |
208 | switch (op) { | |
209 | default: /* should never happen */ | |
210 | return 0; | |
211 | ||
212 | case CC_OP_EFLAGS: | |
f0967a1a | 213 | return compute_c_eflags(env); |
5918fffb BS |
214 | |
215 | case CC_OP_MULB: | |
f0967a1a | 216 | return compute_c_mull(env); |
5918fffb | 217 | case CC_OP_MULW: |
f0967a1a | 218 | return compute_c_mull(env); |
5918fffb | 219 | case CC_OP_MULL: |
f0967a1a | 220 | return compute_c_mull(env); |
5918fffb BS |
221 | |
222 | case CC_OP_ADDB: | |
f0967a1a | 223 | return compute_c_addb(env); |
5918fffb | 224 | case CC_OP_ADDW: |
f0967a1a | 225 | return compute_c_addw(env); |
5918fffb | 226 | case CC_OP_ADDL: |
f0967a1a | 227 | return compute_c_addl(env); |
5918fffb BS |
228 | |
229 | case CC_OP_ADCB: | |
f0967a1a | 230 | return compute_c_adcb(env); |
5918fffb | 231 | case CC_OP_ADCW: |
f0967a1a | 232 | return compute_c_adcw(env); |
5918fffb | 233 | case CC_OP_ADCL: |
f0967a1a | 234 | return compute_c_adcl(env); |
5918fffb BS |
235 | |
236 | case CC_OP_SUBB: | |
f0967a1a | 237 | return compute_c_subb(env); |
5918fffb | 238 | case CC_OP_SUBW: |
f0967a1a | 239 | return compute_c_subw(env); |
5918fffb | 240 | case CC_OP_SUBL: |
f0967a1a | 241 | return compute_c_subl(env); |
5918fffb BS |
242 | |
243 | case CC_OP_SBBB: | |
f0967a1a | 244 | return compute_c_sbbb(env); |
5918fffb | 245 | case CC_OP_SBBW: |
f0967a1a | 246 | return compute_c_sbbw(env); |
5918fffb | 247 | case CC_OP_SBBL: |
f0967a1a | 248 | return compute_c_sbbl(env); |
5918fffb BS |
249 | |
250 | case CC_OP_LOGICB: | |
251 | return compute_c_logicb(); | |
252 | case CC_OP_LOGICW: | |
253 | return compute_c_logicw(); | |
254 | case CC_OP_LOGICL: | |
255 | return compute_c_logicl(); | |
256 | ||
257 | case CC_OP_INCB: | |
f0967a1a | 258 | return compute_c_incl(env); |
5918fffb | 259 | case CC_OP_INCW: |
f0967a1a | 260 | return compute_c_incl(env); |
5918fffb | 261 | case CC_OP_INCL: |
f0967a1a | 262 | return compute_c_incl(env); |
5918fffb BS |
263 | |
264 | case CC_OP_DECB: | |
f0967a1a | 265 | return compute_c_incl(env); |
5918fffb | 266 | case CC_OP_DECW: |
f0967a1a | 267 | return compute_c_incl(env); |
5918fffb | 268 | case CC_OP_DECL: |
f0967a1a | 269 | return compute_c_incl(env); |
5918fffb BS |
270 | |
271 | case CC_OP_SHLB: | |
f0967a1a | 272 | return compute_c_shlb(env); |
5918fffb | 273 | case CC_OP_SHLW: |
f0967a1a | 274 | return compute_c_shlw(env); |
5918fffb | 275 | case CC_OP_SHLL: |
f0967a1a | 276 | return compute_c_shll(env); |
5918fffb BS |
277 | |
278 | case CC_OP_SARB: | |
f0967a1a | 279 | return compute_c_sarl(env); |
5918fffb | 280 | case CC_OP_SARW: |
f0967a1a | 281 | return compute_c_sarl(env); |
5918fffb | 282 | case CC_OP_SARL: |
f0967a1a | 283 | return compute_c_sarl(env); |
5918fffb BS |
284 | |
285 | #ifdef TARGET_X86_64 | |
286 | case CC_OP_MULQ: | |
f0967a1a | 287 | return compute_c_mull(env); |
5918fffb BS |
288 | |
289 | case CC_OP_ADDQ: | |
f0967a1a | 290 | return compute_c_addq(env); |
5918fffb BS |
291 | |
292 | case CC_OP_ADCQ: | |
f0967a1a | 293 | return compute_c_adcq(env); |
5918fffb BS |
294 | |
295 | case CC_OP_SUBQ: | |
f0967a1a | 296 | return compute_c_subq(env); |
5918fffb BS |
297 | |
298 | case CC_OP_SBBQ: | |
f0967a1a | 299 | return compute_c_sbbq(env); |
5918fffb BS |
300 | |
301 | case CC_OP_LOGICQ: | |
302 | return compute_c_logicq(); | |
303 | ||
304 | case CC_OP_INCQ: | |
f0967a1a | 305 | return compute_c_incl(env); |
5918fffb BS |
306 | |
307 | case CC_OP_DECQ: | |
f0967a1a | 308 | return compute_c_incl(env); |
5918fffb BS |
309 | |
310 | case CC_OP_SHLQ: | |
f0967a1a | 311 | return compute_c_shlq(env); |
5918fffb BS |
312 | |
313 | case CC_OP_SARQ: | |
f0967a1a | 314 | return compute_c_sarl(env); |
5918fffb BS |
315 | #endif |
316 | } | |
317 | } | |
318 | ||
f0967a1a BS |
319 | void helper_write_eflags(CPUX86State *env, target_ulong t0, |
320 | uint32_t update_mask) | |
5918fffb BS |
321 | { |
322 | cpu_load_eflags(env, t0, update_mask); | |
323 | } | |
324 | ||
f0967a1a | 325 | target_ulong helper_read_eflags(CPUX86State *env) |
5918fffb BS |
326 | { |
327 | uint32_t eflags; | |
328 | ||
f0967a1a | 329 | eflags = helper_cc_compute_all(env, CC_OP); |
5918fffb BS |
330 | eflags |= (DF & DF_MASK); |
331 | eflags |= env->eflags & ~(VM_MASK | RF_MASK); | |
332 | return eflags; | |
333 | } | |
334 | ||
f0967a1a | 335 | void helper_clts(CPUX86State *env) |
5918fffb BS |
336 | { |
337 | env->cr[0] &= ~CR0_TS_MASK; | |
338 | env->hflags &= ~HF_TS_MASK; | |
339 | } | |
340 | ||
f0967a1a | 341 | void helper_reset_rf(CPUX86State *env) |
5918fffb BS |
342 | { |
343 | env->eflags &= ~RF_MASK; | |
344 | } | |
345 | ||
f0967a1a | 346 | void helper_cli(CPUX86State *env) |
5918fffb BS |
347 | { |
348 | env->eflags &= ~IF_MASK; | |
349 | } | |
350 | ||
f0967a1a | 351 | void helper_sti(CPUX86State *env) |
5918fffb BS |
352 | { |
353 | env->eflags |= IF_MASK; | |
354 | } | |
355 | ||
a9321a4d PA |
356 | void helper_clac(CPUX86State *env) |
357 | { | |
358 | env->eflags &= ~AC_MASK; | |
359 | } | |
360 | ||
361 | void helper_stac(CPUX86State *env) | |
362 | { | |
363 | env->eflags |= AC_MASK; | |
364 | } | |
365 | ||
5918fffb BS |
366 | #if 0 |
367 | /* vm86plus instructions */ | |
f0967a1a | 368 | void helper_cli_vm(CPUX86State *env) |
5918fffb BS |
369 | { |
370 | env->eflags &= ~VIF_MASK; | |
371 | } | |
372 | ||
f0967a1a | 373 | void helper_sti_vm(CPUX86State *env) |
5918fffb BS |
374 | { |
375 | env->eflags |= VIF_MASK; | |
376 | if (env->eflags & VIP_MASK) { | |
377 | raise_exception(env, EXCP0D_GPF); | |
378 | } | |
379 | } | |
380 | #endif | |
381 | ||
f0967a1a | 382 | void helper_set_inhibit_irq(CPUX86State *env) |
5918fffb BS |
383 | { |
384 | env->hflags |= HF_INHIBIT_IRQ_MASK; | |
385 | } | |
386 | ||
f0967a1a | 387 | void helper_reset_inhibit_irq(CPUX86State *env) |
5918fffb BS |
388 | { |
389 | env->hflags &= ~HF_INHIBIT_IRQ_MASK; | |
390 | } |