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Include hw/hw.h exactly where needed
[qemu.git] / hw / riscv / spike.c
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5b4beba1
MC		 1/*
2 * QEMU RISC-V Spike Board
3 *
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5 * Copyright (c) 2017-2018 SiFive, Inc.
6 *
7 * This provides a RISC-V Board with the following devices:
8 *
9 * 0) HTIF Console and Poweroff
10 * 1) CLINT (Timer and IPI)
11 * 2) PLIC (Platform Level Interrupt Controller)
12 *
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms and conditions of the GNU General Public License,
15 * version 2 or later, as published by the Free Software Foundation.
16 *
17 * This program is distributed in the hope it will be useful, but WITHOUT
18 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
19 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
20 * more details.
21 *
22 * You should have received a copy of the GNU General Public License along with
23 * this program. If not, see <http://www.gnu.org/licenses/>.
24 */
25
26#include "qemu/osdep.h"
27#include "qemu/log.h"
28#include "qemu/error-report.h"
29#include "qapi/error.h"
5b4beba1
MC		 30#include "hw/boards.h"
31#include "hw/loader.h"
32#include "hw/sysbus.h"
33#include "target/riscv/cpu.h"
34#include "hw/riscv/riscv_htif.h"
35#include "hw/riscv/riscv_hart.h"
36#include "hw/riscv/sifive_clint.h"
37#include "hw/riscv/spike.h"
0ac24d56 38#include "hw/riscv/boot.h"
5b4beba1
MC		 39#include "chardev/char.h"
40#include "sysemu/arch_init.h"
41#include "sysemu/device_tree.h"
cd69e3a6 42#include "sysemu/qtest.h"
5b4beba1 43#include "exec/address-spaces.h"
5b4beba1 44
5aec3247
MC		 45#include <libfdt.h>
46
5b4beba1
MC		 47static const struct MemmapEntry {
48 hwaddr base;
49 hwaddr size;
50} spike_memmap[] = {
5aec3247 51 [SPIKE_MROM] = { 0x1000, 0x11000 },
5b4beba1
MC		 52 [SPIKE_CLINT] = { 0x2000000, 0x10000 },
53 [SPIKE_DRAM] = { 0x80000000, 0x0 },
54};
55
5b4beba1
MC		 56static void create_fdt(SpikeState *s, const struct MemmapEntry *memmap,
57 uint64_t mem_size, const char *cmdline)
58{
59 void *fdt;
60 int cpu;
61 uint32_t *cells;
62 char *nodename;
63
64 fdt = s->fdt = create_device_tree(&s->fdt_size);
65 if (!fdt) {
66 error_report("create_device_tree() failed");
67 exit(1);
68 }
69
70 qemu_fdt_setprop_string(fdt, "/", "model", "ucbbar,spike-bare,qemu");
71 qemu_fdt_setprop_string(fdt, "/", "compatible", "ucbbar,spike-bare-dev");
72 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2);
73 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);
74
75 qemu_fdt_add_subnode(fdt, "/htif");
76 qemu_fdt_setprop_string(fdt, "/htif", "compatible", "ucb,htif0");
77
78 qemu_fdt_add_subnode(fdt, "/soc");
79 qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0);
117caacf 80 qemu_fdt_setprop_string(fdt, "/soc", "compatible", "simple-bus");
5b4beba1
MC		 81 qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2);
82 qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2);
83
84 nodename = g_strdup_printf("/memory@%lx",
85 (long)memmap[SPIKE_DRAM].base);
86 qemu_fdt_add_subnode(fdt, nodename);
87 qemu_fdt_setprop_cells(fdt, nodename, "reg",
88 memmap[SPIKE_DRAM].base >> 32, memmap[SPIKE_DRAM].base,
89 mem_size >> 32, mem_size);
90 qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory");
91 g_free(nodename);
92
93 qemu_fdt_add_subnode(fdt, "/cpus");
2a8756ed
MC		 94 qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency",
95 SIFIVE_CLINT_TIMEBASE_FREQ);
5b4beba1
MC		 96 qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0);
97 qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1);
98
99 for (cpu = s->soc.num_harts - 1; cpu >= 0; cpu--) {
100 nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
101 char *intc = g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
102 char *isa = riscv_isa_string(&s->soc.harts[cpu]);
103 qemu_fdt_add_subnode(fdt, nodename);
2a8756ed
MC		 104 qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency",
105 SPIKE_CLOCK_FREQ);
5b4beba1
MC		 106 qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48");
107 qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa);
108 qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv");
109 qemu_fdt_setprop_string(fdt, nodename, "status", "okay");
110 qemu_fdt_setprop_cell(fdt, nodename, "reg", cpu);
111 qemu_fdt_setprop_string(fdt, nodename, "device_type", "cpu");
112 qemu_fdt_add_subnode(fdt, intc);
113 qemu_fdt_setprop_cell(fdt, intc, "phandle", 1);
114 qemu_fdt_setprop_cell(fdt, intc, "linux,phandle", 1);
115 qemu_fdt_setprop_string(fdt, intc, "compatible", "riscv,cpu-intc");
116 qemu_fdt_setprop(fdt, intc, "interrupt-controller", NULL, 0);
117 qemu_fdt_setprop_cell(fdt, intc, "#interrupt-cells", 1);
118 g_free(isa);
119 g_free(intc);
120 g_free(nodename);
121 }
122
123 cells = g_new0(uint32_t, s->soc.num_harts * 4);
124 for (cpu = 0; cpu < s->soc.num_harts; cpu++) {
125 nodename =
126 g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
127 uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename);
128 cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
129 cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT);
130 cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle);
131 cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER);
132 g_free(nodename);
133 }
134 nodename = g_strdup_printf("/soc/clint@%lx",
135 (long)memmap[SPIKE_CLINT].base);
136 qemu_fdt_add_subnode(fdt, nodename);
137 qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,clint0");
138 qemu_fdt_setprop_cells(fdt, nodename, "reg",
139 0x0, memmap[SPIKE_CLINT].base,
140 0x0, memmap[SPIKE_CLINT].size);
141 qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
142 cells, s->soc.num_harts * sizeof(uint32_t) * 4);
143 g_free(cells);
144 g_free(nodename);
145
7c28f4da
MC		 146 if (cmdline) {
147 qemu_fdt_add_subnode(fdt, "/chosen");
148 qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
149 }
cd69e3a6
AF		 150}
151
152static void spike_board_init(MachineState *machine)
153{
154 const struct MemmapEntry *memmap = spike_memmap;
155
156 SpikeState *s = g_new0(SpikeState, 1);
157 MemoryRegion *system_memory = get_system_memory();
158 MemoryRegion *main_mem = g_new(MemoryRegion, 1);
159 MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
160 int i;
c4473127 161 unsigned int smp_cpus = machine->smp.cpus;
cd69e3a6
AF		 162
163 /* Initialize SOC */
164 object_initialize_child(OBJECT(machine), "soc", &s->soc, sizeof(s->soc),
165 TYPE_RISCV_HART_ARRAY, &error_abort, NULL);
166 object_property_set_str(OBJECT(&s->soc), machine->cpu_type, "cpu-type",
167 &error_abort);
168 object_property_set_int(OBJECT(&s->soc), smp_cpus, "num-harts",
169 &error_abort);
170 object_property_set_bool(OBJECT(&s->soc), true, "realized",
171 &error_abort);
172
173 /* register system main memory (actual RAM) */
174 memory_region_init_ram(main_mem, NULL, "riscv.spike.ram",
175 machine->ram_size, &error_fatal);
176 memory_region_add_subregion(system_memory, memmap[SPIKE_DRAM].base,
177 main_mem);
178
179 /* create device tree */
180 create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline);
181
182 /* boot rom */
183 memory_region_init_rom(mask_rom, NULL, "riscv.spike.mrom",
184 memmap[SPIKE_MROM].size, &error_fatal);
185 memory_region_add_subregion(system_memory, memmap[SPIKE_MROM].base,
186 mask_rom);
187
188 if (machine->kernel_filename) {
0ac24d56 189 riscv_load_kernel(machine->kernel_filename);
cd69e3a6
AF		 190 }
191
192 /* reset vector */
193 uint32_t reset_vec[8] = {
194 0x00000297, /* 1: auipc t0, %pcrel_hi(dtb) */
195 0x02028593, /* addi a1, t0, %pcrel_lo(1b) */
196 0xf1402573, /* csrr a0, mhartid */
197#if defined(TARGET_RISCV32)
198 0x0182a283, /* lw t0, 24(t0) */
199#elif defined(TARGET_RISCV64)
200 0x0182b283, /* ld t0, 24(t0) */
201#endif
202 0x00028067, /* jr t0 */
203 0x00000000,
204 memmap[SPIKE_DRAM].base, /* start: .dword DRAM_BASE */
205 0x00000000,
206 /* dtb: */
207 };
208
209 /* copy in the reset vector in little_endian byte order */
210 for (i = 0; i < sizeof(reset_vec) >> 2; i++) {
211 reset_vec[i] = cpu_to_le32(reset_vec[i]);
212 }
213 rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
214 memmap[SPIKE_MROM].base, &address_space_memory);
215
216 /* copy in the device tree */
217 if (fdt_pack(s->fdt) || fdt_totalsize(s->fdt) >
218 memmap[SPIKE_MROM].size - sizeof(reset_vec)) {
219 error_report("not enough space to store device-tree");
220 exit(1);
221 }
222 qemu_fdt_dumpdtb(s->fdt, fdt_totalsize(s->fdt));
223 rom_add_blob_fixed_as("mrom.fdt", s->fdt, fdt_totalsize(s->fdt),
224 memmap[SPIKE_MROM].base + sizeof(reset_vec),
225 &address_space_memory);
226
227 /* initialize HTIF using symbols found in load_kernel */
228 htif_mm_init(system_memory, mask_rom, &s->soc.harts[0].env, serial_hd(0));
229
230 /* Core Local Interruptor (timer and IPI) */
231 sifive_clint_create(memmap[SPIKE_CLINT].base, memmap[SPIKE_CLINT].size,
232 smp_cpus, SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE);
233}
5b4beba1
MC		 234
235static void spike_v1_10_0_board_init(MachineState *machine)
236{
237 const struct MemmapEntry *memmap = spike_memmap;
238
239 SpikeState *s = g_new0(SpikeState, 1);
240 MemoryRegion *system_memory = get_system_memory();
241 MemoryRegion *main_mem = g_new(MemoryRegion, 1);
5aec3247
MC		 242 MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
243 int i;
c4473127 244 unsigned int smp_cpus = machine->smp.cpus;
5b4beba1 245
cd69e3a6
AF		 246 if (!qtest_enabled()) {
247 info_report("The Spike v1.10.0 machine has been deprecated. "
248 "Please use the generic spike machine and specify the ISA "
249 "versions using -cpu.");
250 }
251
5b4beba1 252 /* Initialize SOC */
8ff62f6a
AF		 253 object_initialize_child(OBJECT(machine), "soc", &s->soc, sizeof(s->soc),
254 TYPE_RISCV_HART_ARRAY, &error_abort, NULL);
5b4beba1
MC		 255 object_property_set_str(OBJECT(&s->soc), SPIKE_V1_10_0_CPU, "cpu-type",
256 &error_abort);
257 object_property_set_int(OBJECT(&s->soc), smp_cpus, "num-harts",
258 &error_abort);
259 object_property_set_bool(OBJECT(&s->soc), true, "realized",
260 &error_abort);
261
262 /* register system main memory (actual RAM) */
263 memory_region_init_ram(main_mem, NULL, "riscv.spike.ram",
264 machine->ram_size, &error_fatal);
265 memory_region_add_subregion(system_memory, memmap[SPIKE_DRAM].base,
266 main_mem);
267
268 /* create device tree */
269 create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline);
270
271 /* boot rom */
5aec3247
MC		 272 memory_region_init_rom(mask_rom, NULL, "riscv.spike.mrom",
273 memmap[SPIKE_MROM].size, &error_fatal);
274 memory_region_add_subregion(system_memory, memmap[SPIKE_MROM].base,
275 mask_rom);
5b4beba1
MC		 276
277 if (machine->kernel_filename) {
0ac24d56 278 riscv_load_kernel(machine->kernel_filename);
5b4beba1
MC		 279 }
280
281 /* reset vector */
282 uint32_t reset_vec[8] = {
283 0x00000297, /* 1: auipc t0, %pcrel_hi(dtb) */
284 0x02028593, /* addi a1, t0, %pcrel_lo(1b) */
285 0xf1402573, /* csrr a0, mhartid */
286#if defined(TARGET_RISCV32)
287 0x0182a283, /* lw t0, 24(t0) */
288#elif defined(TARGET_RISCV64)
289 0x0182b283, /* ld t0, 24(t0) */
290#endif
291 0x00028067, /* jr t0 */
292 0x00000000,
293 memmap[SPIKE_DRAM].base, /* start: .dword DRAM_BASE */
294 0x00000000,
295 /* dtb: */
296 };
297
5aec3247
MC		 298 /* copy in the reset vector in little_endian byte order */
299 for (i = 0; i < sizeof(reset_vec) >> 2; i++) {
300 reset_vec[i] = cpu_to_le32(reset_vec[i]);
301 }
302 rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
303 memmap[SPIKE_MROM].base, &address_space_memory);
5b4beba1
MC		 304
305 /* copy in the device tree */
5aec3247
MC		 306 if (fdt_pack(s->fdt) || fdt_totalsize(s->fdt) >
307 memmap[SPIKE_MROM].size - sizeof(reset_vec)) {
308 error_report("not enough space to store device-tree");
309 exit(1);
310 }
311 qemu_fdt_dumpdtb(s->fdt, fdt_totalsize(s->fdt));
312 rom_add_blob_fixed_as("mrom.fdt", s->fdt, fdt_totalsize(s->fdt),
313 memmap[SPIKE_MROM].base + sizeof(reset_vec),
314 &address_space_memory);
5b4beba1
MC		 315
316 /* initialize HTIF using symbols found in load_kernel */
5aec3247 317 htif_mm_init(system_memory, mask_rom, &s->soc.harts[0].env, serial_hd(0));
5b4beba1
MC		 318
319 /* Core Local Interruptor (timer and IPI) */
320 sifive_clint_create(memmap[SPIKE_CLINT].base, memmap[SPIKE_CLINT].size,
321 smp_cpus, SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE);
322}
323
324static void spike_v1_09_1_board_init(MachineState *machine)
325{
326 const struct MemmapEntry *memmap = spike_memmap;
327
328 SpikeState *s = g_new0(SpikeState, 1);
329 MemoryRegion *system_memory = get_system_memory();
330 MemoryRegion *main_mem = g_new(MemoryRegion, 1);
5aec3247
MC		 331 MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
332 int i;
c4473127 333 unsigned int smp_cpus = machine->smp.cpus;
5b4beba1 334
cd69e3a6
AF		 335 if (!qtest_enabled()) {
336 info_report("The Spike v1.09.1 machine has been deprecated. "
337 "Please use the generic spike machine and specify the ISA "
338 "versions using -cpu.");
339 }
340
5b4beba1 341 /* Initialize SOC */
8ff62f6a
AF		 342 object_initialize_child(OBJECT(machine), "soc", &s->soc, sizeof(s->soc),
343 TYPE_RISCV_HART_ARRAY, &error_abort, NULL);
5b4beba1
MC		 344 object_property_set_str(OBJECT(&s->soc), SPIKE_V1_09_1_CPU, "cpu-type",
345 &error_abort);
346 object_property_set_int(OBJECT(&s->soc), smp_cpus, "num-harts",
347 &error_abort);
348 object_property_set_bool(OBJECT(&s->soc), true, "realized",
349 &error_abort);
350
351 /* register system main memory (actual RAM) */
352 memory_region_init_ram(main_mem, NULL, "riscv.spike.ram",
353 machine->ram_size, &error_fatal);
354 memory_region_add_subregion(system_memory, memmap[SPIKE_DRAM].base,
355 main_mem);
356
357 /* boot rom */
5aec3247
MC		 358 memory_region_init_rom(mask_rom, NULL, "riscv.spike.mrom",
359 memmap[SPIKE_MROM].size, &error_fatal);
360 memory_region_add_subregion(system_memory, memmap[SPIKE_MROM].base,
361 mask_rom);
5b4beba1
MC		 362
363 if (machine->kernel_filename) {
0ac24d56 364 riscv_load_kernel(machine->kernel_filename);
5b4beba1
MC		 365 }
366
367 /* reset vector */
368 uint32_t reset_vec[8] = {
369 0x297 + memmap[SPIKE_DRAM].base - memmap[SPIKE_MROM].base, /* lui */
370 0x00028067, /* jump to DRAM_BASE */
371 0x00000000, /* reserved */
372 memmap[SPIKE_MROM].base + sizeof(reset_vec), /* config string pointer */
373 0, 0, 0, 0 /* trap vector */
374 };
375
376 /* part one of config string - before memory size specified */
377 const char *config_string_tmpl =
378 "platform {\n"
379 " vendor ucb;\n"
380 " arch spike;\n"
381 "};\n"
382 "rtc {\n"
383 " addr 0x%" PRIx64 "x;\n"
384 "};\n"
385 "ram {\n"
386 " 0 {\n"
387 " addr 0x%" PRIx64 "x;\n"
388 " size 0x%" PRIx64 "x;\n"
389 " };\n"
390 "};\n"
391 "core {\n"
392 " 0" " {\n"
393 " " "0 {\n"
394 " isa %s;\n"
395 " timecmp 0x%" PRIx64 "x;\n"
396 " ipi 0x%" PRIx64 "x;\n"
397 " };\n"
398 " };\n"
399 "};\n";
400
401 /* build config string with supplied memory size */
402 char *isa = riscv_isa_string(&s->soc.harts[0]);
00a014ac 403 char *config_string = g_strdup_printf(config_string_tmpl,
5b4beba1
MC		 404 (uint64_t)memmap[SPIKE_CLINT].base + SIFIVE_TIME_BASE,
405 (uint64_t)memmap[SPIKE_DRAM].base,
406 (uint64_t)ram_size, isa,
407 (uint64_t)memmap[SPIKE_CLINT].base + SIFIVE_TIMECMP_BASE,
408 (uint64_t)memmap[SPIKE_CLINT].base + SIFIVE_SIP_BASE);
409 g_free(isa);
410 size_t config_string_len = strlen(config_string);
411
5aec3247
MC		 412 /* copy in the reset vector in little_endian byte order */
413 for (i = 0; i < sizeof(reset_vec) >> 2; i++) {
414 reset_vec[i] = cpu_to_le32(reset_vec[i]);
415 }
416 rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
417 memmap[SPIKE_MROM].base, &address_space_memory);
5b4beba1
MC		 418
419 /* copy in the config string */
5aec3247
MC		 420 rom_add_blob_fixed_as("mrom.reset", config_string, config_string_len,
421 memmap[SPIKE_MROM].base + sizeof(reset_vec),
422 &address_space_memory);
5b4beba1
MC		 423
424 /* initialize HTIF using symbols found in load_kernel */
5aec3247 425 htif_mm_init(system_memory, mask_rom, &s->soc.harts[0].env, serial_hd(0));
5b4beba1
MC		 426
427 /* Core Local Interruptor (timer and IPI) */
428 sifive_clint_create(memmap[SPIKE_CLINT].base, memmap[SPIKE_CLINT].size,
429 smp_cpus, SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE);
00a014ac
AF		 430
431 g_free(config_string);
5b4beba1
MC		 432}
433
5b4beba1
MC		 434static void spike_v1_09_1_machine_init(MachineClass *mc)
435{
436 mc->desc = "RISC-V Spike Board (Privileged ISA v1.9.1)";
437 mc->init = spike_v1_09_1_board_init;
438 mc->max_cpus = 1;
439}
440
441static void spike_v1_10_0_machine_init(MachineClass *mc)
442{
443 mc->desc = "RISC-V Spike Board (Privileged ISA v1.10)";
444 mc->init = spike_v1_10_0_board_init;
445 mc->max_cpus = 1;
cd69e3a6
AF		 446}
447
448static void spike_machine_init(MachineClass *mc)
449{
450 mc->desc = "RISC-V Spike Board";
451 mc->init = spike_board_init;
452 mc->max_cpus = 1;
5b4beba1 453 mc->is_default = 1;
cd69e3a6 454 mc->default_cpu_type = SPIKE_V1_10_0_CPU;
5b4beba1
MC		 455}
456
457DEFINE_MACHINE("spike_v1.9.1", spike_v1_09_1_machine_init)
458DEFINE_MACHINE("spike_v1.10", spike_v1_10_0_machine_init)
cd69e3a6 459DEFINE_MACHINE("spike", spike_machine_init)
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