[qemu.git] / hw / intc / xics_spapr.c

/*
 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
 *
 * PAPR Virtualized Interrupt System, aka ICS/ICP aka xics
 *
 * Copyright (c) 2010,2011 David Gibson, IBM Corporation.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 *
 */

#include "qemu/osdep.h"
#include "cpu.h"
#include "trace.h"
#include "qemu/timer.h"
#include "hw/ppc/spapr.h"
#include "hw/ppc/spapr_cpu_core.h"
#include "hw/ppc/xics.h"
#include "hw/ppc/xics_spapr.h"
#include "hw/ppc/fdt.h"
#include "qapi/visitor.h"

/*
 * Guest interfaces
 */

static bool check_emulated_xics(SpaprMachineState *spapr, const char *func)
{
    if (spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT) ||
        kvm_irqchip_in_kernel()) {
        error_report("pseries: %s must only be called for emulated XICS",
                     func);
        return false;
    }

    return true;
}

#define CHECK_EMULATED_XICS_HCALL(spapr)               \
    do {                                               \
        if (!check_emulated_xics((spapr), __func__)) { \
            return H_HARDWARE;                         \
        }                                              \
    } while (0)

static target_ulong h_cppr(PowerPCCPU *cpu, SpaprMachineState *spapr,
                           target_ulong opcode, target_ulong *args)
{
    target_ulong cppr = args[0];

    CHECK_EMULATED_XICS_HCALL(spapr);

    icp_set_cppr(spapr_cpu_state(cpu)->icp, cppr);
    return H_SUCCESS;
}

static target_ulong h_ipi(PowerPCCPU *cpu, SpaprMachineState *spapr,
                          target_ulong opcode, target_ulong *args)
{
    target_ulong mfrr = args[1];
    ICPState *icp = xics_icp_get(XICS_FABRIC(spapr), args[0]);

    CHECK_EMULATED_XICS_HCALL(spapr);

    if (!icp) {
        return H_PARAMETER;
    }

    icp_set_mfrr(icp, mfrr);
    return H_SUCCESS;
}

static target_ulong h_xirr(PowerPCCPU *cpu, SpaprMachineState *spapr,
                           target_ulong opcode, target_ulong *args)
{
    uint32_t xirr = icp_accept(spapr_cpu_state(cpu)->icp);

    CHECK_EMULATED_XICS_HCALL(spapr);

    args[0] = xirr;
    return H_SUCCESS;
}

static target_ulong h_xirr_x(PowerPCCPU *cpu, SpaprMachineState *spapr,
                             target_ulong opcode, target_ulong *args)
{
    uint32_t xirr = icp_accept(spapr_cpu_state(cpu)->icp);

    CHECK_EMULATED_XICS_HCALL(spapr);

    args[0] = xirr;
    args[1] = cpu_get_host_ticks();
    return H_SUCCESS;
}

static target_ulong h_eoi(PowerPCCPU *cpu, SpaprMachineState *spapr,
                          target_ulong opcode, target_ulong *args)
{
    target_ulong xirr = args[0];

    CHECK_EMULATED_XICS_HCALL(spapr);

    icp_eoi(spapr_cpu_state(cpu)->icp, xirr);
    return H_SUCCESS;
}

static target_ulong h_ipoll(PowerPCCPU *cpu, SpaprMachineState *spapr,
                            target_ulong opcode, target_ulong *args)
{
    ICPState *icp = xics_icp_get(XICS_FABRIC(spapr), args[0]);
    uint32_t mfrr;
    uint32_t xirr;

    CHECK_EMULATED_XICS_HCALL(spapr);

    if (!icp) {
        return H_PARAMETER;
    }

    xirr = icp_ipoll(icp, &mfrr);

    args[0] = xirr;
    args[1] = mfrr;

    return H_SUCCESS;
}

#define CHECK_EMULATED_XICS_RTAS(spapr, rets)          \
    do {                                               \
        if (!check_emulated_xics((spapr), __func__)) { \
            rtas_st((rets), 0, RTAS_OUT_HW_ERROR);     \
            return;                                    \
        }                                              \
    } while (0)

static void rtas_set_xive(PowerPCCPU *cpu, SpaprMachineState *spapr,
                          uint32_t token,
                          uint32_t nargs, target_ulong args,
                          uint32_t nret, target_ulong rets)
{
    ICSState *ics = spapr->ics;
    uint32_t nr, srcno, server, priority;

    CHECK_EMULATED_XICS_RTAS(spapr, rets);

    if ((nargs != 3) || (nret != 1)) {
        rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
        return;
    }
    if (!ics) {
        rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
        return;
    }

    nr = rtas_ld(args, 0);
    server = rtas_ld(args, 1);
    priority = rtas_ld(args, 2);

    if (!ics_valid_irq(ics, nr) || !xics_icp_get(XICS_FABRIC(spapr), server)
        || (priority > 0xff)) {
        rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
        return;
    }

    srcno = nr - ics->offset;
    ics_simple_write_xive(ics, srcno, server, priority, priority);

    rtas_st(rets, 0, RTAS_OUT_SUCCESS);
}

static void rtas_get_xive(PowerPCCPU *cpu, SpaprMachineState *spapr,
                          uint32_t token,
                          uint32_t nargs, target_ulong args,
                          uint32_t nret, target_ulong rets)
{
    ICSState *ics = spapr->ics;
    uint32_t nr, srcno;

    CHECK_EMULATED_XICS_RTAS(spapr, rets);

    if ((nargs != 1) || (nret != 3)) {
        rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
        return;
    }
    if (!ics) {
        rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
        return;
    }

    nr = rtas_ld(args, 0);

    if (!ics_valid_irq(ics, nr)) {
        rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
        return;
    }

    rtas_st(rets, 0, RTAS_OUT_SUCCESS);
    srcno = nr - ics->offset;
    rtas_st(rets, 1, ics->irqs[srcno].server);
    rtas_st(rets, 2, ics->irqs[srcno].priority);
}

static void rtas_int_off(PowerPCCPU *cpu, SpaprMachineState *spapr,
                         uint32_t token,
                         uint32_t nargs, target_ulong args,
                         uint32_t nret, target_ulong rets)
{
    ICSState *ics = spapr->ics;
    uint32_t nr, srcno;

    CHECK_EMULATED_XICS_RTAS(spapr, rets);

    if ((nargs != 1) || (nret != 1)) {
        rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
        return;
    }
    if (!ics) {
        rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
        return;
    }

    nr = rtas_ld(args, 0);

    if (!ics_valid_irq(ics, nr)) {
        rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
        return;
    }

    srcno = nr - ics->offset;
    ics_simple_write_xive(ics, srcno, ics->irqs[srcno].server, 0xff,
                          ics->irqs[srcno].priority);

    rtas_st(rets, 0, RTAS_OUT_SUCCESS);
}

static void rtas_int_on(PowerPCCPU *cpu, SpaprMachineState *spapr,
                        uint32_t token,
                        uint32_t nargs, target_ulong args,
                        uint32_t nret, target_ulong rets)
{
    ICSState *ics = spapr->ics;
    uint32_t nr, srcno;

    CHECK_EMULATED_XICS_RTAS(spapr, rets);

    if ((nargs != 1) || (nret != 1)) {
        rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
        return;
    }
    if (!ics) {
        rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
        return;
    }

    nr = rtas_ld(args, 0);

    if (!ics_valid_irq(ics, nr)) {
        rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
        return;
    }

    srcno = nr - ics->offset;
    ics_simple_write_xive(ics, srcno, ics->irqs[srcno].server,
                          ics->irqs[srcno].saved_priority,
                          ics->irqs[srcno].saved_priority);

    rtas_st(rets, 0, RTAS_OUT_SUCCESS);
}

void xics_spapr_init(SpaprMachineState *spapr)
{
    spapr_rtas_register(RTAS_IBM_SET_XIVE, "ibm,set-xive", rtas_set_xive);
    spapr_rtas_register(RTAS_IBM_GET_XIVE, "ibm,get-xive", rtas_get_xive);
    spapr_rtas_register(RTAS_IBM_INT_OFF, "ibm,int-off", rtas_int_off);
    spapr_rtas_register(RTAS_IBM_INT_ON, "ibm,int-on", rtas_int_on);

    spapr_register_hypercall(H_CPPR, h_cppr);
    spapr_register_hypercall(H_IPI, h_ipi);
    spapr_register_hypercall(H_XIRR, h_xirr);
    spapr_register_hypercall(H_XIRR_X, h_xirr_x);
    spapr_register_hypercall(H_EOI, h_eoi);
    spapr_register_hypercall(H_IPOLL, h_ipoll);
}

void spapr_dt_xics(SpaprMachineState *spapr, uint32_t nr_servers, void *fdt,
                   uint32_t phandle)
{
    uint32_t interrupt_server_ranges_prop[] = {
        0, cpu_to_be32(nr_servers),
    };
    int node;

    _FDT(node = fdt_add_subnode(fdt, 0, XICS_NODENAME));

    _FDT(fdt_setprop_string(fdt, node, "device_type",
                            "PowerPC-External-Interrupt-Presentation"));
    _FDT(fdt_setprop_string(fdt, node, "compatible", "IBM,ppc-xicp"));
    _FDT(fdt_setprop(fdt, node, "interrupt-controller", NULL, 0));
    _FDT(fdt_setprop(fdt, node, "ibm,interrupt-server-ranges",
                     interrupt_server_ranges_prop,
                     sizeof(interrupt_server_ranges_prop)));
    _FDT(fdt_setprop_cell(fdt, node, "#interrupt-cells", 2));
    _FDT(fdt_setprop_cell(fdt, node, "linux,phandle", phandle));
    _FDT(fdt_setprop_cell(fdt, node, "phandle", phandle));
}
Commit	Line	Data
9c7027ba BH	1	/*
	2	* QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
	3	*
	4	* PAPR Virtualized Interrupt System, aka ICS/ICP aka xics
	5	*
	6	* Copyright (c) 2010,2011 David Gibson, IBM Corporation.
	7	*
	8	* Permission is hereby granted, free of charge, to any person obtaining a copy
	9	* of this software and associated documentation files (the "Software"), to deal
	10	* in the Software without restriction, including without limitation the rights
	11	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	12	* copies of the Software, and to permit persons to whom the Software is
	13	* furnished to do so, subject to the following conditions:
	14	*
	15	* The above copyright notice and this permission notice shall be included in
	16	* all copies or substantial portions of the Software.
	17	*
	18	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	19	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	20	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	21	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	22	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	23	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	24	* THE SOFTWARE.
	25	*
	26	*/
	27
	28	#include "qemu/osdep.h"
	29	#include "cpu.h"
9c7027ba BH	30	#include "trace.h"
	31	#include "qemu/timer.h"
	32	#include "hw/ppc/spapr.h"
a28b9a5a	33	#include "hw/ppc/spapr_cpu_core.h"
9c7027ba	34	#include "hw/ppc/xics.h"
a51d5afc	35	#include "hw/ppc/xics_spapr.h"
9b9a1908	36	#include "hw/ppc/fdt.h"
9c7027ba	37	#include "qapi/visitor.h"
9c7027ba BH	38
	39	/*
	40	* Guest interfaces
	41	*/
	42
25c79a30	43	static bool check_emulated_xics(SpaprMachineState spapr, const char func)
d9715d67	44	{
25c79a30 GK	45	if (spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT) \|\|
	46	kvm_irqchip_in_kernel()) {
	47	error_report("pseries: %s must only be called for emulated XICS",
d9715d67	48	func);
25c79a30	49	return false;
d9715d67 GK	50	}
d9715d67 GK	51
25c79a30	52	return true;
d9715d67 GK	53	}
d9715d67 GK	54
25c79a30 GK	55	#define CHECK_EMULATED_XICS_HCALL(spapr) \
	56	do { \
	57	if (!check_emulated_xics((spapr), __func__)) { \
	58	return H_HARDWARE; \
	59	} \
d9715d67 GK	60	} while (0)
d9715d67 GK	61
ce2918cb	62	static target_ulong h_cppr(PowerPCCPU cpu, SpaprMachineState spapr,
9c7027ba BH	63	target_ulong opcode, target_ulong *args)
9c7027ba BH	64	{
9c7027ba BH	65	target_ulong cppr = args[0];
9c7027ba BH	66
25c79a30	67	CHECK_EMULATED_XICS_HCALL(spapr);
d9715d67	68
a28b9a5a	69	icp_set_cppr(spapr_cpu_state(cpu)->icp, cppr);
9c7027ba BH	70	return H_SUCCESS;
	71	}
	72
ce2918cb	73	static target_ulong h_ipi(PowerPCCPU cpu, SpaprMachineState spapr,
9c7027ba BH	74	target_ulong opcode, target_ulong *args)
9c7027ba BH	75	{
9c7027ba	76	target_ulong mfrr = args[1];
06747ba6	77	ICPState *icp = xics_icp_get(XICS_FABRIC(spapr), args[0]);
9c7027ba	78
25c79a30	79	CHECK_EMULATED_XICS_HCALL(spapr);
d9715d67	80
b4f27d71	81	if (!icp) {
9c7027ba BH	82	return H_PARAMETER;
	83	}
	84
b4f27d71	85	icp_set_mfrr(icp, mfrr);
9c7027ba BH	86	return H_SUCCESS;
	87	}
	88
ce2918cb	89	static target_ulong h_xirr(PowerPCCPU cpu, SpaprMachineState spapr,
9c7027ba BH	90	target_ulong opcode, target_ulong *args)
9c7027ba BH	91	{
a28b9a5a	92	uint32_t xirr = icp_accept(spapr_cpu_state(cpu)->icp);
9c7027ba	93
25c79a30	94	CHECK_EMULATED_XICS_HCALL(spapr);
d9715d67	95
9c7027ba BH	96	args[0] = xirr;
	97	return H_SUCCESS;
	98	}
	99
ce2918cb	100	static target_ulong h_xirr_x(PowerPCCPU cpu, SpaprMachineState spapr,
9c7027ba BH	101	target_ulong opcode, target_ulong *args)
9c7027ba BH	102	{
a28b9a5a	103	uint32_t xirr = icp_accept(spapr_cpu_state(cpu)->icp);
9c7027ba	104
25c79a30	105	CHECK_EMULATED_XICS_HCALL(spapr);
d9715d67	106
9c7027ba BH	107	args[0] = xirr;
	108	args[1] = cpu_get_host_ticks();
	109	return H_SUCCESS;
	110	}
	111
ce2918cb	112	static target_ulong h_eoi(PowerPCCPU cpu, SpaprMachineState spapr,
9c7027ba BH	113	target_ulong opcode, target_ulong *args)
9c7027ba BH	114	{
9c7027ba BH	115	target_ulong xirr = args[0];
9c7027ba BH	116
25c79a30	117	CHECK_EMULATED_XICS_HCALL(spapr);
d9715d67	118
a28b9a5a	119	icp_eoi(spapr_cpu_state(cpu)->icp, xirr);
9c7027ba BH	120	return H_SUCCESS;
	121	}
	122
ce2918cb	123	static target_ulong h_ipoll(PowerPCCPU cpu, SpaprMachineState spapr,
9c7027ba BH	124	target_ulong opcode, target_ulong *args)
9c7027ba BH	125	{
ebc184be	126	ICPState *icp = xics_icp_get(XICS_FABRIC(spapr), args[0]);
1cbd2220	127	uint32_t mfrr;
ebc184be BH	128	uint32_t xirr;
ebc184be BH	129
25c79a30	130	CHECK_EMULATED_XICS_HCALL(spapr);
d9715d67	131
ebc184be BH	132	if (!icp) {
	133	return H_PARAMETER;
	134	}
	135
	136	xirr = icp_ipoll(icp, &mfrr);
9c7027ba	137
1cbd2220 BH	138	args[0] = xirr;
1cbd2220 BH	139	args[1] = mfrr;
9c7027ba BH	140
	141	return H_SUCCESS;
	142	}
	143
25c79a30 GK	144	#define CHECK_EMULATED_XICS_RTAS(spapr, rets) \
	145	do { \
	146	if (!check_emulated_xics((spapr), __func__)) { \
	147	rtas_st((rets), 0, RTAS_OUT_HW_ERROR); \
	148	return; \
	149	} \
d9715d67 GK	150	} while (0)
d9715d67 GK	151
ce2918cb	152	static void rtas_set_xive(PowerPCCPU cpu, SpaprMachineState spapr,
9c7027ba BH	153	uint32_t token,
	154	uint32_t nargs, target_ulong args,
	155	uint32_t nret, target_ulong rets)
	156	{
681bfade	157	ICSState *ics = spapr->ics;
d4d7a59a	158	uint32_t nr, srcno, server, priority;
9c7027ba	159
25c79a30	160	CHECK_EMULATED_XICS_RTAS(spapr, rets);
d9715d67	161
9c7027ba BH	162	if ((nargs != 3) \|\| (nret != 1)) {
	163	rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
	164	return;
	165	}
cc706a53 BH	166	if (!ics) {
	167	rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
	168	return;
	169	}
9c7027ba BH	170
9c7027ba BH	171	nr = rtas_ld(args, 0);
06747ba6	172	server = rtas_ld(args, 1);
9c7027ba BH	173	priority = rtas_ld(args, 2);
9c7027ba BH	174
b4f27d71	175	if (!ics_valid_irq(ics, nr) \|\| !xics_icp_get(XICS_FABRIC(spapr), server)
9c7027ba BH	176	\|\| (priority > 0xff)) {
	177	rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
	178	return;
	179	}
	180
d4d7a59a BH	181	srcno = nr - ics->offset;
d4d7a59a BH	182	ics_simple_write_xive(ics, srcno, server, priority, priority);
9c7027ba BH	183
	184	rtas_st(rets, 0, RTAS_OUT_SUCCESS);
	185	}
	186
ce2918cb	187	static void rtas_get_xive(PowerPCCPU cpu, SpaprMachineState spapr,
9c7027ba BH	188	uint32_t token,
	189	uint32_t nargs, target_ulong args,
	190	uint32_t nret, target_ulong rets)
	191	{
681bfade	192	ICSState *ics = spapr->ics;
d4d7a59a	193	uint32_t nr, srcno;
9c7027ba	194
25c79a30	195	CHECK_EMULATED_XICS_RTAS(spapr, rets);
d9715d67	196
9c7027ba BH	197	if ((nargs != 1) \|\| (nret != 3)) {
	198	rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
	199	return;
	200	}
cc706a53 BH	201	if (!ics) {
	202	rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
	203	return;
	204	}
9c7027ba BH	205
	206	nr = rtas_ld(args, 0);
	207
	208	if (!ics_valid_irq(ics, nr)) {
	209	rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
	210	return;
	211	}
	212
	213	rtas_st(rets, 0, RTAS_OUT_SUCCESS);
d4d7a59a BH	214	srcno = nr - ics->offset;
	215	rtas_st(rets, 1, ics->irqs[srcno].server);
	216	rtas_st(rets, 2, ics->irqs[srcno].priority);
9c7027ba BH	217	}
9c7027ba BH	218
ce2918cb	219	static void rtas_int_off(PowerPCCPU cpu, SpaprMachineState spapr,
9c7027ba BH	220	uint32_t token,
	221	uint32_t nargs, target_ulong args,
	222	uint32_t nret, target_ulong rets)
	223	{
681bfade	224	ICSState *ics = spapr->ics;
d4d7a59a	225	uint32_t nr, srcno;
9c7027ba	226
25c79a30	227	CHECK_EMULATED_XICS_RTAS(spapr, rets);
d9715d67	228
9c7027ba BH	229	if ((nargs != 1) \|\| (nret != 1)) {
	230	rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
	231	return;
	232	}
cc706a53 BH	233	if (!ics) {
	234	rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
	235	return;
	236	}
9c7027ba BH	237
	238	nr = rtas_ld(args, 0);
	239
	240	if (!ics_valid_irq(ics, nr)) {
	241	rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
	242	return;
	243	}
	244
d4d7a59a BH	245	srcno = nr - ics->offset;
	246	ics_simple_write_xive(ics, srcno, ics->irqs[srcno].server, 0xff,
	247	ics->irqs[srcno].priority);
9c7027ba BH	248
	249	rtas_st(rets, 0, RTAS_OUT_SUCCESS);
	250	}
	251
ce2918cb	252	static void rtas_int_on(PowerPCCPU cpu, SpaprMachineState spapr,
9c7027ba BH	253	uint32_t token,
	254	uint32_t nargs, target_ulong args,
	255	uint32_t nret, target_ulong rets)
	256	{
681bfade	257	ICSState *ics = spapr->ics;
d4d7a59a	258	uint32_t nr, srcno;
9c7027ba	259
25c79a30	260	CHECK_EMULATED_XICS_RTAS(spapr, rets);
d9715d67	261
9c7027ba BH	262	if ((nargs != 1) \|\| (nret != 1)) {
	263	rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
	264	return;
	265	}
cc706a53 BH	266	if (!ics) {
	267	rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
	268	return;
	269	}
9c7027ba BH	270
	271	nr = rtas_ld(args, 0);
	272
	273	if (!ics_valid_irq(ics, nr)) {
	274	rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
	275	return;
	276	}
	277
d4d7a59a BH	278	srcno = nr - ics->offset;
	279	ics_simple_write_xive(ics, srcno, ics->irqs[srcno].server,
	280	ics->irqs[srcno].saved_priority,
	281	ics->irqs[srcno].saved_priority);
9c7027ba BH	282
	283	rtas_st(rets, 0, RTAS_OUT_SUCCESS);
	284	}
	285
ce2918cb	286	void xics_spapr_init(SpaprMachineState *spapr)
9c7027ba	287	{
9c7027ba BH	288	spapr_rtas_register(RTAS_IBM_SET_XIVE, "ibm,set-xive", rtas_set_xive);
	289	spapr_rtas_register(RTAS_IBM_GET_XIVE, "ibm,get-xive", rtas_get_xive);
	290	spapr_rtas_register(RTAS_IBM_INT_OFF, "ibm,int-off", rtas_int_off);
	291	spapr_rtas_register(RTAS_IBM_INT_ON, "ibm,int-on", rtas_int_on);
	292
	293	spapr_register_hypercall(H_CPPR, h_cppr);
	294	spapr_register_hypercall(H_IPI, h_ipi);
	295	spapr_register_hypercall(H_XIRR, h_xirr);
	296	spapr_register_hypercall(H_XIRR_X, h_xirr_x);
	297	spapr_register_hypercall(H_EOI, h_eoi);
	298	spapr_register_hypercall(H_IPOLL, h_ipoll);
9c7027ba BH	299	}
9c7027ba BH	300
ce2918cb	301	void spapr_dt_xics(SpaprMachineState spapr, uint32_t nr_servers, void fdt,
6e21de4a	302	uint32_t phandle)
9b9a1908 DG	303	{
9b9a1908 DG	304	uint32_t interrupt_server_ranges_prop[] = {
b0ec3129	305	0, cpu_to_be32(nr_servers),
9b9a1908 DG	306	};
	307	int node;
	308
743ed566	309	_FDT(node = fdt_add_subnode(fdt, 0, XICS_NODENAME));
9b9a1908 DG	310
	311	_FDT(fdt_setprop_string(fdt, node, "device_type",
	312	"PowerPC-External-Interrupt-Presentation"));
	313	_FDT(fdt_setprop_string(fdt, node, "compatible", "IBM,ppc-xicp"));
	314	_FDT(fdt_setprop(fdt, node, "interrupt-controller", NULL, 0));
	315	_FDT(fdt_setprop(fdt, node, "ibm,interrupt-server-ranges",
	316	interrupt_server_ranges_prop,
	317	sizeof(interrupt_server_ranges_prop)));
	318	_FDT(fdt_setprop_cell(fdt, node, "#interrupt-cells", 2));
	319	_FDT(fdt_setprop_cell(fdt, node, "linux,phandle", phandle));
	320	_FDT(fdt_setprop_cell(fdt, node, "phandle", phandle));
	321	}