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Commit | Line | Data |
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bbfc2efe AF |
1 | /* |
2 | * QTest testcase for ivshmem | |
3 | * | |
4 | * Copyright (c) 2014 SUSE LINUX Products GmbH | |
ddef6a0d | 5 | * Copyright (c) 2015 Red Hat, Inc. |
bbfc2efe AF |
6 | * |
7 | * This work is licensed under the terms of the GNU GPL, version 2 or later. | |
8 | * See the COPYING file in the top-level directory. | |
9 | */ | |
10 | ||
681c28a3 | 11 | #include "qemu/osdep.h" |
ddef6a0d | 12 | #include <glib/gstdio.h> |
ddef6a0d | 13 | #include "contrib/ivshmem-server/ivshmem-server.h" |
d69487d5 | 14 | #include "libqos/libqos-pc.h" |
2bf25e07 | 15 | #include "libqos/libqos-spapr.h" |
bbfc2efe | 16 | #include "libqtest.h" |
ddef6a0d | 17 | #include "qemu-common.h" |
bbfc2efe | 18 | |
ddef6a0d MAL |
19 | #define TMPSHMSIZE (1 << 20) |
20 | static char *tmpshm; | |
21 | static void *tmpshmem; | |
22 | static char *tmpdir; | |
23 | static char *tmpserver; | |
bbfc2efe | 24 | |
ddef6a0d | 25 | static void save_fn(QPCIDevice *dev, int devfn, void *data) |
bbfc2efe | 26 | { |
ddef6a0d MAL |
27 | QPCIDevice **pdev = (QPCIDevice **) data; |
28 | ||
29 | *pdev = dev; | |
30 | } | |
31 | ||
1760048a | 32 | static QPCIDevice *get_device(QPCIBus *pcibus) |
ddef6a0d MAL |
33 | { |
34 | QPCIDevice *dev; | |
ddef6a0d | 35 | |
16130947 | 36 | dev = NULL; |
ddef6a0d MAL |
37 | qpci_device_foreach(pcibus, 0x1af4, 0x1110, save_fn, &dev); |
38 | g_assert(dev != NULL); | |
39 | ||
40 | return dev; | |
41 | } | |
42 | ||
43 | typedef struct _IVState { | |
d69487d5 | 44 | QOSState *qs; |
b4ba67d9 | 45 | QPCIBar reg_bar, mem_bar; |
ddef6a0d MAL |
46 | QPCIDevice *dev; |
47 | } IVState; | |
48 | ||
49 | enum Reg { | |
50 | INTRMASK = 0, | |
51 | INTRSTATUS = 4, | |
52 | IVPOSITION = 8, | |
53 | DOORBELL = 12, | |
54 | }; | |
55 | ||
56 | static const char* reg2str(enum Reg reg) { | |
57 | switch (reg) { | |
58 | case INTRMASK: | |
59 | return "IntrMask"; | |
60 | case INTRSTATUS: | |
61 | return "IntrStatus"; | |
62 | case IVPOSITION: | |
63 | return "IVPosition"; | |
64 | case DOORBELL: | |
65 | return "DoorBell"; | |
66 | default: | |
67 | return NULL; | |
68 | } | |
69 | } | |
70 | ||
71 | static inline unsigned in_reg(IVState *s, enum Reg reg) | |
72 | { | |
73 | const char *name = reg2str(reg); | |
ddef6a0d MAL |
74 | unsigned res; |
75 | ||
b4ba67d9 | 76 | res = qpci_io_readl(s->dev, s->reg_bar, reg); |
13ee9e30 | 77 | g_test_message("*%s -> %x", name, res); |
ddef6a0d MAL |
78 | |
79 | return res; | |
80 | } | |
81 | ||
82 | static inline void out_reg(IVState *s, enum Reg reg, unsigned v) | |
83 | { | |
84 | const char *name = reg2str(reg); | |
ddef6a0d | 85 | |
13ee9e30 | 86 | g_test_message("%x -> *%s", v, name); |
b4ba67d9 | 87 | qpci_io_writel(s->dev, s->reg_bar, reg, v); |
ddef6a0d MAL |
88 | } |
89 | ||
204e54b8 DG |
90 | static inline void read_mem(IVState *s, uint64_t off, void *buf, size_t len) |
91 | { | |
b4ba67d9 | 92 | qpci_memread(s->dev, s->mem_bar, off, buf, len); |
204e54b8 DG |
93 | } |
94 | ||
95 | static inline void write_mem(IVState *s, uint64_t off, | |
96 | const void *buf, size_t len) | |
97 | { | |
b4ba67d9 | 98 | qpci_memwrite(s->dev, s->mem_bar, off, buf, len); |
204e54b8 DG |
99 | } |
100 | ||
1760048a MAL |
101 | static void cleanup_vm(IVState *s) |
102 | { | |
103 | g_free(s->dev); | |
d69487d5 | 104 | qtest_shutdown(s->qs); |
1760048a MAL |
105 | } |
106 | ||
ddef6a0d MAL |
107 | static void setup_vm_cmd(IVState *s, const char *cmd, bool msix) |
108 | { | |
109 | uint64_t barsize; | |
d69487d5 | 110 | const char *arch = qtest_get_arch(); |
ddef6a0d | 111 | |
d69487d5 LV |
112 | if (strcmp(arch, "i386") == 0 || strcmp(arch, "x86_64") == 0) { |
113 | s->qs = qtest_pc_boot(cmd); | |
2bf25e07 LV |
114 | } else if (strcmp(arch, "ppc64") == 0) { |
115 | s->qs = qtest_spapr_boot(cmd); | |
d69487d5 | 116 | } else { |
2bf25e07 | 117 | g_printerr("ivshmem-test tests are only available on x86 or ppc64\n"); |
d69487d5 LV |
118 | exit(EXIT_FAILURE); |
119 | } | |
120 | s->dev = get_device(s->qs->pcibus); | |
ddef6a0d | 121 | |
b4ba67d9 | 122 | s->reg_bar = qpci_iomap(s->dev, 0, &barsize); |
99826172 | 123 | g_assert_cmpuint(barsize, ==, 256); |
ddef6a0d MAL |
124 | |
125 | if (msix) { | |
126 | qpci_msix_enable(s->dev); | |
127 | } | |
128 | ||
b4ba67d9 | 129 | s->mem_bar = qpci_iomap(s->dev, 2, &barsize); |
99826172 | 130 | g_assert_cmpuint(barsize, ==, TMPSHMSIZE); |
ddef6a0d MAL |
131 | |
132 | qpci_device_enable(s->dev); | |
133 | } | |
134 | ||
135 | static void setup_vm(IVState *s) | |
136 | { | |
5400c02b MA |
137 | char *cmd = g_strdup_printf("-object memory-backend-file" |
138 | ",id=mb1,size=1M,share,mem-path=/dev/shm%s" | |
139 | " -device ivshmem-plain,memdev=mb1", tmpshm); | |
ddef6a0d MAL |
140 | |
141 | setup_vm_cmd(s, cmd, false); | |
142 | ||
143 | g_free(cmd); | |
144 | } | |
145 | ||
146 | static void test_ivshmem_single(void) | |
147 | { | |
148 | IVState state, *s; | |
149 | uint32_t data[1024]; | |
150 | int i; | |
151 | ||
152 | setup_vm(&state); | |
153 | s = &state; | |
154 | ||
4958fe5d MA |
155 | /* initial state of readable registers */ |
156 | g_assert_cmpuint(in_reg(s, INTRMASK), ==, 0); | |
157 | g_assert_cmpuint(in_reg(s, INTRSTATUS), ==, 0); | |
158 | g_assert_cmpuint(in_reg(s, IVPOSITION), ==, 0); | |
ddef6a0d | 159 | |
4958fe5d | 160 | /* trigger interrupt via registers */ |
ddef6a0d MAL |
161 | out_reg(s, INTRMASK, 0xffffffff); |
162 | g_assert_cmpuint(in_reg(s, INTRMASK), ==, 0xffffffff); | |
163 | out_reg(s, INTRSTATUS, 1); | |
4958fe5d | 164 | /* check interrupt status */ |
ddef6a0d | 165 | g_assert_cmpuint(in_reg(s, INTRSTATUS), ==, 1); |
4958fe5d MA |
166 | /* reading clears */ |
167 | g_assert_cmpuint(in_reg(s, INTRSTATUS), ==, 0); | |
168 | /* TODO intercept actual interrupt (needs qtest work) */ | |
ddef6a0d | 169 | |
4958fe5d | 170 | /* invalid register access */ |
ddef6a0d | 171 | out_reg(s, IVPOSITION, 1); |
4958fe5d MA |
172 | in_reg(s, DOORBELL); |
173 | ||
174 | /* ring the (non-functional) doorbell */ | |
ddef6a0d MAL |
175 | out_reg(s, DOORBELL, 8 << 16); |
176 | ||
4958fe5d | 177 | /* write shared memory */ |
ddef6a0d MAL |
178 | for (i = 0; i < G_N_ELEMENTS(data); i++) { |
179 | data[i] = i; | |
180 | } | |
204e54b8 | 181 | write_mem(s, 0, data, sizeof(data)); |
ddef6a0d | 182 | |
4958fe5d | 183 | /* verify write */ |
ddef6a0d MAL |
184 | for (i = 0; i < G_N_ELEMENTS(data); i++) { |
185 | g_assert_cmpuint(((uint32_t *)tmpshmem)[i], ==, i); | |
186 | } | |
187 | ||
4958fe5d | 188 | /* read it back and verify read */ |
ddef6a0d | 189 | memset(data, 0, sizeof(data)); |
204e54b8 | 190 | read_mem(s, 0, data, sizeof(data)); |
ddef6a0d MAL |
191 | for (i = 0; i < G_N_ELEMENTS(data); i++) { |
192 | g_assert_cmpuint(data[i], ==, i); | |
193 | } | |
194 | ||
1760048a | 195 | cleanup_vm(s); |
ddef6a0d MAL |
196 | } |
197 | ||
198 | static void test_ivshmem_pair(void) | |
199 | { | |
200 | IVState state1, state2, *s1, *s2; | |
201 | char *data; | |
202 | int i; | |
203 | ||
204 | setup_vm(&state1); | |
205 | s1 = &state1; | |
206 | setup_vm(&state2); | |
207 | s2 = &state2; | |
208 | ||
209 | data = g_malloc0(TMPSHMSIZE); | |
210 | ||
211 | /* host write, guest 1 & 2 read */ | |
212 | memset(tmpshmem, 0x42, TMPSHMSIZE); | |
204e54b8 | 213 | read_mem(s1, 0, data, TMPSHMSIZE); |
ddef6a0d MAL |
214 | for (i = 0; i < TMPSHMSIZE; i++) { |
215 | g_assert_cmpuint(data[i], ==, 0x42); | |
216 | } | |
204e54b8 | 217 | read_mem(s2, 0, data, TMPSHMSIZE); |
ddef6a0d MAL |
218 | for (i = 0; i < TMPSHMSIZE; i++) { |
219 | g_assert_cmpuint(data[i], ==, 0x42); | |
220 | } | |
221 | ||
222 | /* guest 1 write, guest 2 read */ | |
223 | memset(data, 0x43, TMPSHMSIZE); | |
204e54b8 | 224 | write_mem(s1, 0, data, TMPSHMSIZE); |
ddef6a0d | 225 | memset(data, 0, TMPSHMSIZE); |
204e54b8 | 226 | read_mem(s2, 0, data, TMPSHMSIZE); |
ddef6a0d MAL |
227 | for (i = 0; i < TMPSHMSIZE; i++) { |
228 | g_assert_cmpuint(data[i], ==, 0x43); | |
229 | } | |
230 | ||
231 | /* guest 2 write, guest 1 read */ | |
232 | memset(data, 0x44, TMPSHMSIZE); | |
204e54b8 | 233 | write_mem(s2, 0, data, TMPSHMSIZE); |
ddef6a0d | 234 | memset(data, 0, TMPSHMSIZE); |
204e54b8 | 235 | read_mem(s1, 0, data, TMPSHMSIZE); |
ddef6a0d MAL |
236 | for (i = 0; i < TMPSHMSIZE; i++) { |
237 | g_assert_cmpuint(data[i], ==, 0x44); | |
238 | } | |
239 | ||
1760048a MAL |
240 | cleanup_vm(s1); |
241 | cleanup_vm(s2); | |
ddef6a0d MAL |
242 | g_free(data); |
243 | } | |
244 | ||
245 | typedef struct ServerThread { | |
246 | GThread *thread; | |
247 | IvshmemServer *server; | |
248 | int pipe[2]; /* to handle quit */ | |
249 | } ServerThread; | |
250 | ||
251 | static void *server_thread(void *data) | |
252 | { | |
253 | ServerThread *t = data; | |
254 | IvshmemServer *server = t->server; | |
255 | ||
256 | while (true) { | |
257 | fd_set fds; | |
258 | int maxfd, ret; | |
259 | ||
260 | FD_ZERO(&fds); | |
261 | FD_SET(t->pipe[0], &fds); | |
262 | maxfd = t->pipe[0] + 1; | |
263 | ||
264 | ivshmem_server_get_fds(server, &fds, &maxfd); | |
265 | ||
266 | ret = select(maxfd, &fds, NULL, NULL, NULL); | |
267 | ||
268 | if (ret < 0) { | |
269 | if (errno == EINTR) { | |
270 | continue; | |
271 | } | |
272 | ||
273 | g_critical("select error: %s\n", strerror(errno)); | |
274 | break; | |
275 | } | |
276 | if (ret == 0) { | |
277 | continue; | |
278 | } | |
279 | ||
280 | if (FD_ISSET(t->pipe[0], &fds)) { | |
281 | break; | |
282 | } | |
283 | ||
284 | if (ivshmem_server_handle_fds(server, &fds, maxfd) < 0) { | |
285 | g_critical("ivshmem_server_handle_fds() failed\n"); | |
286 | break; | |
287 | } | |
288 | } | |
289 | ||
290 | return NULL; | |
291 | } | |
292 | ||
5a0e75f0 | 293 | static void setup_vm_with_server(IVState *s, int nvectors) |
ddef6a0d | 294 | { |
5a0e75f0 | 295 | char *cmd; |
ddef6a0d | 296 | |
767abe7f | 297 | cmd = g_strdup_printf("-chardev socket,id=chr0,path=%s " |
5a0e75f0 TH |
298 | "-device ivshmem-doorbell,chardev=chr0,vectors=%d", |
299 | tmpserver, nvectors); | |
300 | ||
301 | setup_vm_cmd(s, cmd, true); | |
ddef6a0d MAL |
302 | |
303 | g_free(cmd); | |
304 | } | |
305 | ||
5a0e75f0 | 306 | static void test_ivshmem_server(void) |
ddef6a0d MAL |
307 | { |
308 | IVState state1, state2, *s1, *s2; | |
309 | ServerThread thread; | |
310 | IvshmemServer server; | |
311 | int ret, vm1, vm2; | |
312 | int nvectors = 2; | |
313 | guint64 end_time = g_get_monotonic_time() + 5 * G_TIME_SPAN_SECOND; | |
314 | ||
3625c739 | 315 | ret = ivshmem_server_init(&server, tmpserver, tmpshm, true, |
ddef6a0d MAL |
316 | TMPSHMSIZE, nvectors, |
317 | g_test_verbose()); | |
318 | g_assert_cmpint(ret, ==, 0); | |
319 | ||
320 | ret = ivshmem_server_start(&server); | |
321 | g_assert_cmpint(ret, ==, 0); | |
322 | ||
ddef6a0d MAL |
323 | thread.server = &server; |
324 | ret = pipe(thread.pipe); | |
325 | g_assert_cmpint(ret, ==, 0); | |
326 | thread.thread = g_thread_new("ivshmem-server", server_thread, &thread); | |
327 | g_assert(thread.thread != NULL); | |
328 | ||
5a0e75f0 | 329 | setup_vm_with_server(&state1, nvectors); |
3a55fc0f | 330 | s1 = &state1; |
5a0e75f0 | 331 | setup_vm_with_server(&state2, nvectors); |
3a55fc0f | 332 | s2 = &state2; |
ddef6a0d MAL |
333 | |
334 | /* check got different VM ids */ | |
335 | vm1 = in_reg(s1, IVPOSITION); | |
336 | vm2 = in_reg(s2, IVPOSITION); | |
3a55fc0f MA |
337 | g_assert_cmpint(vm1, >=, 0); |
338 | g_assert_cmpint(vm2, >=, 0); | |
339 | g_assert_cmpint(vm1, !=, vm2); | |
ddef6a0d | 340 | |
41b65e5e | 341 | /* check number of MSI-X vectors */ |
5a0e75f0 TH |
342 | ret = qpci_msix_table_size(s1->dev); |
343 | g_assert_cmpuint(ret, ==, nvectors); | |
ddef6a0d | 344 | |
41b65e5e MA |
345 | /* TODO test behavior before MSI-X is enabled */ |
346 | ||
347 | /* ping vm2 -> vm1 on vector 0 */ | |
5a0e75f0 TH |
348 | ret = qpci_msix_pending(s1->dev, 0); |
349 | g_assert_cmpuint(ret, ==, 0); | |
ddef6a0d MAL |
350 | out_reg(s2, DOORBELL, vm1 << 16); |
351 | do { | |
352 | g_usleep(10000); | |
5a0e75f0 | 353 | ret = qpci_msix_pending(s1->dev, 0); |
ddef6a0d MAL |
354 | } while (ret == 0 && g_get_monotonic_time() < end_time); |
355 | g_assert_cmpuint(ret, !=, 0); | |
356 | ||
41b65e5e | 357 | /* ping vm1 -> vm2 on vector 1 */ |
5a0e75f0 TH |
358 | ret = qpci_msix_pending(s2->dev, 1); |
359 | g_assert_cmpuint(ret, ==, 0); | |
41b65e5e | 360 | out_reg(s1, DOORBELL, vm2 << 16 | 1); |
ddef6a0d MAL |
361 | do { |
362 | g_usleep(10000); | |
5a0e75f0 | 363 | ret = qpci_msix_pending(s2->dev, 1); |
ddef6a0d MAL |
364 | } while (ret == 0 && g_get_monotonic_time() < end_time); |
365 | g_assert_cmpuint(ret, !=, 0); | |
366 | ||
1760048a MAL |
367 | cleanup_vm(s2); |
368 | cleanup_vm(s1); | |
ddef6a0d MAL |
369 | |
370 | if (qemu_write_full(thread.pipe[1], "q", 1) != 1) { | |
371 | g_error("qemu_write_full: %s", g_strerror(errno)); | |
372 | } | |
373 | ||
374 | g_thread_join(thread.thread); | |
375 | ||
376 | ivshmem_server_close(&server); | |
377 | close(thread.pipe[1]); | |
378 | close(thread.pipe[0]); | |
379 | } | |
380 | ||
381 | #define PCI_SLOT_HP 0x06 | |
382 | ||
383 | static void test_ivshmem_hotplug(void) | |
384 | { | |
6ebb8d2a | 385 | QTestState *qts; |
2bf25e07 | 386 | const char *arch = qtest_get_arch(); |
ddef6a0d | 387 | |
6ebb8d2a | 388 | qts = qtest_init("-object memory-backend-ram,size=1M,id=mb1"); |
ddef6a0d | 389 | |
e5758de4 | 390 | qtest_qmp_device_add(qts, "ivshmem-plain", "iv1", |
5a0e75f0 TH |
391 | "{'addr': %s, 'memdev': 'mb1'}", |
392 | stringify(PCI_SLOT_HP)); | |
2bf25e07 | 393 | if (strcmp(arch, "ppc64") != 0) { |
6ebb8d2a | 394 | qpci_unplug_acpi_device_test(qts, "iv1", PCI_SLOT_HP); |
2bf25e07 | 395 | } |
ddef6a0d | 396 | |
6ebb8d2a | 397 | qtest_quit(qts); |
ddef6a0d MAL |
398 | } |
399 | ||
d9453c93 MAL |
400 | static void test_ivshmem_memdev(void) |
401 | { | |
402 | IVState state; | |
403 | ||
404 | /* just for the sake of checking memory-backend property */ | |
405 | setup_vm_cmd(&state, "-object memory-backend-ram,size=1M,id=mb1" | |
5400c02b | 406 | " -device ivshmem-plain,memdev=mb1", false); |
d9453c93 | 407 | |
1760048a | 408 | cleanup_vm(&state); |
d9453c93 MAL |
409 | } |
410 | ||
ddef6a0d MAL |
411 | static void cleanup(void) |
412 | { | |
413 | if (tmpshmem) { | |
414 | munmap(tmpshmem, TMPSHMSIZE); | |
415 | tmpshmem = NULL; | |
416 | } | |
417 | ||
418 | if (tmpshm) { | |
419 | shm_unlink(tmpshm); | |
420 | g_free(tmpshm); | |
421 | tmpshm = NULL; | |
422 | } | |
423 | ||
424 | if (tmpserver) { | |
425 | g_unlink(tmpserver); | |
426 | g_free(tmpserver); | |
427 | tmpserver = NULL; | |
428 | } | |
429 | ||
430 | if (tmpdir) { | |
431 | g_rmdir(tmpdir); | |
432 | tmpdir = NULL; | |
433 | } | |
434 | } | |
435 | ||
436 | static void abrt_handler(void *data) | |
437 | { | |
438 | cleanup(); | |
439 | } | |
440 | ||
441 | static gchar *mktempshm(int size, int *fd) | |
442 | { | |
443 | while (true) { | |
444 | gchar *name; | |
445 | ||
0f555602 | 446 | name = g_strdup_printf("/qtest-%u-%u", getpid(), g_test_rand_int()); |
ddef6a0d MAL |
447 | *fd = shm_open(name, O_CREAT|O_RDWR|O_EXCL, |
448 | S_IRWXU|S_IRWXG|S_IRWXO); | |
449 | if (*fd > 0) { | |
450 | g_assert(ftruncate(*fd, size) == 0); | |
451 | return name; | |
452 | } | |
453 | ||
454 | g_free(name); | |
455 | ||
456 | if (errno != EEXIST) { | |
457 | perror("shm_open"); | |
458 | return NULL; | |
459 | } | |
460 | } | |
bbfc2efe AF |
461 | } |
462 | ||
463 | int main(int argc, char **argv) | |
464 | { | |
bbfc2efe | 465 | int ret, fd; |
2bf25e07 | 466 | const char *arch = qtest_get_arch(); |
ddef6a0d MAL |
467 | gchar dir[] = "/tmp/ivshmem-test.XXXXXX"; |
468 | ||
bbfc2efe | 469 | g_test_init(&argc, &argv, NULL); |
bbfc2efe | 470 | |
ddef6a0d MAL |
471 | qtest_add_abrt_handler(abrt_handler, NULL); |
472 | /* shm */ | |
473 | tmpshm = mktempshm(TMPSHMSIZE, &fd); | |
474 | if (!tmpshm) { | |
4848cb3d | 475 | goto out; |
ddef6a0d MAL |
476 | } |
477 | tmpshmem = mmap(0, TMPSHMSIZE, PROT_READ|PROT_WRITE, MAP_SHARED, fd, 0); | |
478 | g_assert(tmpshmem != MAP_FAILED); | |
479 | /* server */ | |
480 | if (mkdtemp(dir) == NULL) { | |
481 | g_error("mkdtemp: %s", g_strerror(errno)); | |
482 | } | |
483 | tmpdir = dir; | |
484 | tmpserver = g_strconcat(tmpdir, "/server", NULL); | |
bbfc2efe | 485 | |
ddef6a0d | 486 | qtest_add_func("/ivshmem/single", test_ivshmem_single); |
ddef6a0d | 487 | qtest_add_func("/ivshmem/hotplug", test_ivshmem_hotplug); |
d9453c93 | 488 | qtest_add_func("/ivshmem/memdev", test_ivshmem_memdev); |
2048a2a4 MAL |
489 | if (g_test_slow()) { |
490 | qtest_add_func("/ivshmem/pair", test_ivshmem_pair); | |
2bf25e07 | 491 | if (strcmp(arch, "ppc64") != 0) { |
5a0e75f0 | 492 | qtest_add_func("/ivshmem/server", test_ivshmem_server); |
2bf25e07 | 493 | } |
2048a2a4 | 494 | } |
bbfc2efe | 495 | |
4848cb3d | 496 | out: |
bbfc2efe | 497 | ret = g_test_run(); |
ddef6a0d | 498 | cleanup(); |
bbfc2efe AF |
499 | return ret; |
500 | } |