[qemu.git] / hw / dma / pxa2xx_dma.c

/*
 * Intel XScale PXA255/270 DMA controller.
 *
 * Copyright (c) 2006 Openedhand Ltd.
 * Copyright (c) 2006 Thorsten Zitterell
 * Written by Andrzej Zaborowski <[email protected]>
 *
 * This code is licensed under the GPL.
 */

#include "qemu/osdep.h"
#include "hw/hw.h"
#include "hw/irq.h"
#include "hw/arm/pxa.h"
#include "hw/sysbus.h"
#include "qapi/error.h"
#include "qemu/module.h"

#define PXA255_DMA_NUM_CHANNELS 16
#define PXA27X_DMA_NUM_CHANNELS 32

#define PXA2XX_DMA_NUM_REQUESTS 75

typedef struct {
    uint32_t descr;
    uint32_t src;
    uint32_t dest;
    uint32_t cmd;
    uint32_t state;
    int request;
} PXA2xxDMAChannel;

#define TYPE_PXA2XX_DMA "pxa2xx-dma"
#define PXA2XX_DMA(obj) OBJECT_CHECK(PXA2xxDMAState, (obj), TYPE_PXA2XX_DMA)

typedef struct PXA2xxDMAState {
    SysBusDevice parent_obj;

    MemoryRegion iomem;
    qemu_irq irq;

    uint32_t stopintr;
    uint32_t eorintr;
    uint32_t rasintr;
    uint32_t startintr;
    uint32_t endintr;

    uint32_t align;
    uint32_t pio;

    int channels;
    PXA2xxDMAChannel *chan;

    uint8_t req[PXA2XX_DMA_NUM_REQUESTS];

    /* Flag to avoid recursive DMA invocations.  */
    int running;
} PXA2xxDMAState;

#define DCSR0	0x0000	/* DMA Control / Status register for Channel 0 */
#define DCSR31	0x007c	/* DMA Control / Status register for Channel 31 */
#define DALGN	0x00a0	/* DMA Alignment register */
#define DPCSR	0x00a4	/* DMA Programmed I/O Control Status register */
#define DRQSR0	0x00e0	/* DMA DREQ<0> Status register */
#define DRQSR1	0x00e4	/* DMA DREQ<1> Status register */
#define DRQSR2	0x00e8	/* DMA DREQ<2> Status register */
#define DINT	0x00f0	/* DMA Interrupt register */
#define DRCMR0	0x0100	/* Request to Channel Map register 0 */
#define DRCMR63	0x01fc	/* Request to Channel Map register 63 */
#define D_CH0	0x0200	/* Channel 0 Descriptor start */
#define DRCMR64	0x1100	/* Request to Channel Map register 64 */
#define DRCMR74	0x1128	/* Request to Channel Map register 74 */

/* Per-channel register */
#define DDADR	0x00
#define DSADR	0x01
#define DTADR	0x02
#define DCMD	0x03

/* Bit-field masks */
#define DRCMR_CHLNUM		0x1f
#define DRCMR_MAPVLD		(1 << 7)
#define DDADR_STOP		(1 << 0)
#define DDADR_BREN		(1 << 1)
#define DCMD_LEN		0x1fff
#define DCMD_WIDTH(x)		(1 << ((((x) >> 14) & 3) - 1))
#define DCMD_SIZE(x)		(4 << (((x) >> 16) & 3))
#define DCMD_FLYBYT		(1 << 19)
#define DCMD_FLYBYS		(1 << 20)
#define DCMD_ENDIRQEN		(1 << 21)
#define DCMD_STARTIRQEN		(1 << 22)
#define DCMD_CMPEN		(1 << 25)
#define DCMD_FLOWTRG		(1 << 28)
#define DCMD_FLOWSRC		(1 << 29)
#define DCMD_INCTRGADDR		(1 << 30)
#define DCMD_INCSRCADDR		(1 << 31)
#define DCSR_BUSERRINTR		(1 << 0)
#define DCSR_STARTINTR		(1 << 1)
#define DCSR_ENDINTR		(1 << 2)
#define DCSR_STOPINTR		(1 << 3)
#define DCSR_RASINTR		(1 << 4)
#define DCSR_REQPEND		(1 << 8)
#define DCSR_EORINT		(1 << 9)
#define DCSR_CMPST		(1 << 10)
#define DCSR_MASKRUN		(1 << 22)
#define DCSR_RASIRQEN		(1 << 23)
#define DCSR_CLRCMPST		(1 << 24)
#define DCSR_SETCMPST		(1 << 25)
#define DCSR_EORSTOPEN		(1 << 26)
#define DCSR_EORJMPEN		(1 << 27)
#define DCSR_EORIRQEN		(1 << 28)
#define DCSR_STOPIRQEN		(1 << 29)
#define DCSR_NODESCFETCH	(1 << 30)
#define DCSR_RUN		(1 << 31)

static inline void pxa2xx_dma_update(PXA2xxDMAState *s, int ch)
{
    if (ch >= 0) {
        if ((s->chan[ch].state & DCSR_STOPIRQEN) &&
                (s->chan[ch].state & DCSR_STOPINTR))
            s->stopintr |= 1 << ch;
        else
            s->stopintr &= ~(1 << ch);

        if ((s->chan[ch].state & DCSR_EORIRQEN) &&
                (s->chan[ch].state & DCSR_EORINT))
            s->eorintr |= 1 << ch;
        else
            s->eorintr &= ~(1 << ch);

        if ((s->chan[ch].state & DCSR_RASIRQEN) &&
                (s->chan[ch].state & DCSR_RASINTR))
            s->rasintr |= 1 << ch;
        else
            s->rasintr &= ~(1 << ch);

        if (s->chan[ch].state & DCSR_STARTINTR)
            s->startintr |= 1 << ch;
        else
            s->startintr &= ~(1 << ch);

        if (s->chan[ch].state & DCSR_ENDINTR)
            s->endintr |= 1 << ch;
        else
            s->endintr &= ~(1 << ch);
    }

    if (s->stopintr | s->eorintr | s->rasintr | s->startintr | s->endintr)
        qemu_irq_raise(s->irq);
    else
        qemu_irq_lower(s->irq);
}

static inline void pxa2xx_dma_descriptor_fetch(
                PXA2xxDMAState *s, int ch)
{
    uint32_t desc[4];
    hwaddr daddr = s->chan[ch].descr & ~0xf;
    if ((s->chan[ch].descr & DDADR_BREN) && (s->chan[ch].state & DCSR_CMPST))
        daddr += 32;

    cpu_physical_memory_read(daddr, desc, 16);
    s->chan[ch].descr = desc[DDADR];
    s->chan[ch].src = desc[DSADR];
    s->chan[ch].dest = desc[DTADR];
    s->chan[ch].cmd = desc[DCMD];

    if (s->chan[ch].cmd & DCMD_FLOWSRC)
        s->chan[ch].src &= ~3;
    if (s->chan[ch].cmd & DCMD_FLOWTRG)
        s->chan[ch].dest &= ~3;

    if (s->chan[ch].cmd & (DCMD_CMPEN | DCMD_FLYBYS | DCMD_FLYBYT))
        printf("%s: unsupported mode in channel %i\n", __func__, ch);

    if (s->chan[ch].cmd & DCMD_STARTIRQEN)
        s->chan[ch].state |= DCSR_STARTINTR;
}

static void pxa2xx_dma_run(PXA2xxDMAState *s)
{
    int c, srcinc, destinc;
    uint32_t n, size;
    uint32_t width;
    uint32_t length;
    uint8_t buffer[32];
    PXA2xxDMAChannel *ch;

    if (s->running ++)
        return;

    while (s->running) {
        s->running = 1;
        for (c = 0; c < s->channels; c ++) {
            ch = &s->chan[c];

            while ((ch->state & DCSR_RUN) && !(ch->state & DCSR_STOPINTR)) {
                /* Test for pending requests */
                if ((ch->cmd & (DCMD_FLOWSRC | DCMD_FLOWTRG)) && !ch->request)
                    break;

                length = ch->cmd & DCMD_LEN;
                size = DCMD_SIZE(ch->cmd);
                width = DCMD_WIDTH(ch->cmd);

                srcinc = (ch->cmd & DCMD_INCSRCADDR) ? width : 0;
                destinc = (ch->cmd & DCMD_INCTRGADDR) ? width : 0;

                while (length) {
                    size = MIN(length, size);

                    for (n = 0; n < size; n += width) {
                        cpu_physical_memory_read(ch->src, buffer + n, width);
                        ch->src += srcinc;
                    }

                    for (n = 0; n < size; n += width) {
                        cpu_physical_memory_write(ch->dest, buffer + n, width);
                        ch->dest += destinc;
                    }

                    length -= size;

                    if ((ch->cmd & (DCMD_FLOWSRC | DCMD_FLOWTRG)) &&
                            !ch->request) {
                        ch->state |= DCSR_EORINT;
                        if (ch->state & DCSR_EORSTOPEN)
                            ch->state |= DCSR_STOPINTR;
                        if ((ch->state & DCSR_EORJMPEN) &&
                                        !(ch->state & DCSR_NODESCFETCH))
                            pxa2xx_dma_descriptor_fetch(s, c);
                        break;
                    }
                }

                ch->cmd = (ch->cmd & ~DCMD_LEN) | length;

                /* Is the transfer complete now? */
                if (!length) {
                    if (ch->cmd & DCMD_ENDIRQEN)
                        ch->state |= DCSR_ENDINTR;

                    if ((ch->state & DCSR_NODESCFETCH) ||
                                (ch->descr & DDADR_STOP) ||
                                (ch->state & DCSR_EORSTOPEN)) {
                        ch->state |= DCSR_STOPINTR;
                        ch->state &= ~DCSR_RUN;

                        break;
                    }

                    ch->state |= DCSR_STOPINTR;
                    break;
                }
            }
        }

        s->running --;
    }
}

static uint64_t pxa2xx_dma_read(void *opaque, hwaddr offset,
                                unsigned size)
{
    PXA2xxDMAState *s = (PXA2xxDMAState *) opaque;
    unsigned int channel;

    if (size != 4) {
        hw_error("%s: Bad access width\n", __func__);
        return 5;
    }

    switch (offset) {
    case DRCMR64 ... DRCMR74:
        offset -= DRCMR64 - DRCMR0 - (64 << 2);
        /* Fall through */
    case DRCMR0 ... DRCMR63:
        channel = (offset - DRCMR0) >> 2;
        return s->req[channel];

    case DRQSR0:
    case DRQSR1:
    case DRQSR2:
        return 0;

    case DCSR0 ... DCSR31:
        channel = offset >> 2;
        if (s->chan[channel].request)
            return s->chan[channel].state | DCSR_REQPEND;
        return s->chan[channel].state;

    case DINT:
        return s->stopintr | s->eorintr | s->rasintr |
                s->startintr | s->endintr;

    case DALGN:
        return s->align;

    case DPCSR:
        return s->pio;
    }

    if (offset >= D_CH0 && offset < D_CH0 + (s->channels << 4)) {
        channel = (offset - D_CH0) >> 4;
        switch ((offset & 0x0f) >> 2) {
        case DDADR:
            return s->chan[channel].descr;
        case DSADR:
            return s->chan[channel].src;
        case DTADR:
            return s->chan[channel].dest;
        case DCMD:
            return s->chan[channel].cmd;
        }
    }

    hw_error("%s: Bad offset 0x" TARGET_FMT_plx "\n", __func__, offset);
    return 7;
}

static void pxa2xx_dma_write(void *opaque, hwaddr offset,
                             uint64_t value, unsigned size)
{
    PXA2xxDMAState *s = (PXA2xxDMAState *) opaque;
    unsigned int channel;

    if (size != 4) {
        hw_error("%s: Bad access width\n", __func__);
        return;
    }

    switch (offset) {
    case DRCMR64 ... DRCMR74:
        offset -= DRCMR64 - DRCMR0 - (64 << 2);
        /* Fall through */
    case DRCMR0 ... DRCMR63:
        channel = (offset - DRCMR0) >> 2;

        if (value & DRCMR_MAPVLD)
            if ((value & DRCMR_CHLNUM) > s->channels)
                hw_error("%s: Bad DMA channel %i\n",
                         __func__, (unsigned)value & DRCMR_CHLNUM);

        s->req[channel] = value;
        break;

    case DRQSR0:
    case DRQSR1:
    case DRQSR2:
        /* Nothing to do */
        break;

    case DCSR0 ... DCSR31:
        channel = offset >> 2;
        s->chan[channel].state &= 0x0000071f & ~(value &
                        (DCSR_EORINT | DCSR_ENDINTR |
                         DCSR_STARTINTR | DCSR_BUSERRINTR));
        s->chan[channel].state |= value & 0xfc800000;

        if (s->chan[channel].state & DCSR_STOPIRQEN)
            s->chan[channel].state &= ~DCSR_STOPINTR;

        if (value & DCSR_NODESCFETCH) {
            /* No-descriptor-fetch mode */
            if (value & DCSR_RUN) {
                s->chan[channel].state &= ~DCSR_STOPINTR;
                pxa2xx_dma_run(s);
            }
        } else {
            /* Descriptor-fetch mode */
            if (value & DCSR_RUN) {
                s->chan[channel].state &= ~DCSR_STOPINTR;
                pxa2xx_dma_descriptor_fetch(s, channel);
                pxa2xx_dma_run(s);
            }
        }

        /* Shouldn't matter as our DMA is synchronous.  */
        if (!(value & (DCSR_RUN | DCSR_MASKRUN)))
            s->chan[channel].state |= DCSR_STOPINTR;

        if (value & DCSR_CLRCMPST)
            s->chan[channel].state &= ~DCSR_CMPST;
        if (value & DCSR_SETCMPST)
            s->chan[channel].state |= DCSR_CMPST;

        pxa2xx_dma_update(s, channel);
        break;

    case DALGN:
        s->align = value;
        break;

    case DPCSR:
        s->pio = value & 0x80000001;
        break;

    default:
        if (offset >= D_CH0 && offset < D_CH0 + (s->channels << 4)) {
            channel = (offset - D_CH0) >> 4;
            switch ((offset & 0x0f) >> 2) {
            case DDADR:
                s->chan[channel].descr = value;
                break;
            case DSADR:
                s->chan[channel].src = value;
                break;
            case DTADR:
                s->chan[channel].dest = value;
                break;
            case DCMD:
                s->chan[channel].cmd = value;
                break;
            default:
                goto fail;
            }

            break;
        }
    fail:
        hw_error("%s: Bad offset " TARGET_FMT_plx "\n", __func__, offset);
    }
}

static const MemoryRegionOps pxa2xx_dma_ops = {
    .read = pxa2xx_dma_read,
    .write = pxa2xx_dma_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
};

static void pxa2xx_dma_request(void *opaque, int req_num, int on)
{
    PXA2xxDMAState *s = opaque;
    int ch;
    if (req_num < 0 || req_num >= PXA2XX_DMA_NUM_REQUESTS)
        hw_error("%s: Bad DMA request %i\n", __func__, req_num);

    if (!(s->req[req_num] & DRCMR_MAPVLD))
        return;
    ch = s->req[req_num] & DRCMR_CHLNUM;

    if (!s->chan[ch].request && on)
        s->chan[ch].state |= DCSR_RASINTR;
    else
        s->chan[ch].state &= ~DCSR_RASINTR;
    if (s->chan[ch].request && !on)
        s->chan[ch].state |= DCSR_EORINT;

    s->chan[ch].request = on;
    if (on) {
        pxa2xx_dma_run(s);
        pxa2xx_dma_update(s, ch);
    }
}

static void pxa2xx_dma_init(Object *obj)
{
    DeviceState *dev = DEVICE(obj);
    PXA2xxDMAState *s = PXA2XX_DMA(obj);
    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);

    memset(s->req, 0, sizeof(uint8_t) * PXA2XX_DMA_NUM_REQUESTS);

    qdev_init_gpio_in(dev, pxa2xx_dma_request, PXA2XX_DMA_NUM_REQUESTS);

    memory_region_init_io(&s->iomem, obj, &pxa2xx_dma_ops, s,
                          "pxa2xx.dma", 0x00010000);
    sysbus_init_mmio(sbd, &s->iomem);
    sysbus_init_irq(sbd, &s->irq);
}

static void pxa2xx_dma_realize(DeviceState *dev, Error **errp)
{
    PXA2xxDMAState *s = PXA2XX_DMA(dev);
    int i;

    if (s->channels <= 0) {
        error_setg(errp, "channels value invalid");
        return;
    }

    s->chan = g_new0(PXA2xxDMAChannel, s->channels);

    for (i = 0; i < s->channels; i ++)
        s->chan[i].state = DCSR_STOPINTR;
}

DeviceState *pxa27x_dma_init(hwaddr base, qemu_irq irq)
{
    DeviceState *dev;

    dev = qdev_create(NULL, "pxa2xx-dma");
    qdev_prop_set_int32(dev, "channels", PXA27X_DMA_NUM_CHANNELS);
    qdev_init_nofail(dev);

    sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
    sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq);

    return dev;
}

DeviceState *pxa255_dma_init(hwaddr base, qemu_irq irq)
{
    DeviceState *dev;

    dev = qdev_create(NULL, "pxa2xx-dma");
    qdev_prop_set_int32(dev, "channels", PXA27X_DMA_NUM_CHANNELS);
    qdev_init_nofail(dev);

    sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
    sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq);

    return dev;
}

static bool is_version_0(void *opaque, int version_id)
{
    return version_id == 0;
}

static VMStateDescription vmstate_pxa2xx_dma_chan = {
    .name = "pxa2xx_dma_chan",
    .version_id = 1,
    .minimum_version_id = 1,
    .fields = (VMStateField[]) {
        VMSTATE_UINT32(descr, PXA2xxDMAChannel),
        VMSTATE_UINT32(src, PXA2xxDMAChannel),
        VMSTATE_UINT32(dest, PXA2xxDMAChannel),
        VMSTATE_UINT32(cmd, PXA2xxDMAChannel),
        VMSTATE_UINT32(state, PXA2xxDMAChannel),
        VMSTATE_INT32(request, PXA2xxDMAChannel),
        VMSTATE_END_OF_LIST(),
    },
};

static VMStateDescription vmstate_pxa2xx_dma = {
    .name = "pxa2xx_dma",
    .version_id = 1,
    .minimum_version_id = 0,
    .fields = (VMStateField[]) {
        VMSTATE_UNUSED_TEST(is_version_0, 4),
        VMSTATE_UINT32(stopintr, PXA2xxDMAState),
        VMSTATE_UINT32(eorintr, PXA2xxDMAState),
        VMSTATE_UINT32(rasintr, PXA2xxDMAState),
        VMSTATE_UINT32(startintr, PXA2xxDMAState),
        VMSTATE_UINT32(endintr, PXA2xxDMAState),
        VMSTATE_UINT32(align, PXA2xxDMAState),
        VMSTATE_UINT32(pio, PXA2xxDMAState),
        VMSTATE_BUFFER(req, PXA2xxDMAState),
        VMSTATE_STRUCT_VARRAY_POINTER_INT32(chan, PXA2xxDMAState, channels,
                vmstate_pxa2xx_dma_chan, PXA2xxDMAChannel),
        VMSTATE_END_OF_LIST(),
    },
};

static Property pxa2xx_dma_properties[] = {
    DEFINE_PROP_INT32("channels", PXA2xxDMAState, channels, -1),
    DEFINE_PROP_END_OF_LIST(),
};

static void pxa2xx_dma_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);

    dc->desc = "PXA2xx DMA controller";
    dc->vmsd = &vmstate_pxa2xx_dma;
    dc->props = pxa2xx_dma_properties;
    dc->realize = pxa2xx_dma_realize;
}

static const TypeInfo pxa2xx_dma_info = {
    .name          = TYPE_PXA2XX_DMA,
    .parent        = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(PXA2xxDMAState),
    .instance_init = pxa2xx_dma_init,
    .class_init    = pxa2xx_dma_class_init,
};

static void pxa2xx_dma_register_types(void)
{
    type_register_static(&pxa2xx_dma_info);
}

type_init(pxa2xx_dma_register_types)
Commit	Line	Data
c1713132 AZ	1	/*
	2	* Intel XScale PXA255/270 DMA controller.
	3	*
	4	* Copyright (c) 2006 Openedhand Ltd.
	5	* Copyright (c) 2006 Thorsten Zitterell
	6	* Written by Andrzej Zaborowski <[email protected]>
	7	*
8e31bf38	8	* This code is licensed under the GPL.
c1713132 AZ	9	*/
c1713132 AZ	10
8ef94f0b	11	#include "qemu/osdep.h"
83c9f4ca	12	#include "hw/hw.h"
64552b6b	13	#include "hw/irq.h"
0d09e41a	14	#include "hw/arm/pxa.h"
83c9f4ca	15	#include "hw/sysbus.h"
c9796d71	16	#include "qapi/error.h"
0b8fa32f	17	#include "qemu/module.h"
2115c019 AZ	18
	19	#define PXA255_DMA_NUM_CHANNELS 16
	20	#define PXA27X_DMA_NUM_CHANNELS 32
	21
	22	#define PXA2XX_DMA_NUM_REQUESTS 75
c1713132	23
bc24a225	24	typedef struct {
a10394e1 MI	25	uint32_t descr;
	26	uint32_t src;
	27	uint32_t dest;
c1713132 AZ	28	uint32_t cmd;
	29	uint32_t state;
	30	int request;
bc24a225	31	} PXA2xxDMAChannel;
c1713132	32
358cd7ac AF	33	#define TYPE_PXA2XX_DMA "pxa2xx-dma"
	34	#define PXA2XX_DMA(obj) OBJECT_CHECK(PXA2xxDMAState, (obj), TYPE_PXA2XX_DMA)
	35
2115c019	36	typedef struct PXA2xxDMAState {
358cd7ac AF	37	SysBusDevice parent_obj;
358cd7ac AF	38
00049a12	39	MemoryRegion iomem;
c1713132 AZ	40	qemu_irq irq;
	41
	42	uint32_t stopintr;
	43	uint32_t eorintr;
	44	uint32_t rasintr;
	45	uint32_t startintr;
	46	uint32_t endintr;
	47
	48	uint32_t align;
	49	uint32_t pio;
	50
	51	int channels;
bc24a225	52	PXA2xxDMAChannel *chan;
c1713132	53
2115c019	54	uint8_t req[PXA2XX_DMA_NUM_REQUESTS];
c1713132 AZ	55
	56	/* Flag to avoid recursive DMA invocations. */
	57	int running;
2115c019	58	} PXA2xxDMAState;
c1713132 AZ	59
	60	#define DCSR0 0x0000 /* DMA Control / Status register for Channel 0 */
	61	#define DCSR31 0x007c /* DMA Control / Status register for Channel 31 */
	62	#define DALGN 0x00a0 /* DMA Alignment register */
	63	#define DPCSR 0x00a4 /* DMA Programmed I/O Control Status register */
	64	#define DRQSR0 0x00e0 /* DMA DREQ<0> Status register */
	65	#define DRQSR1 0x00e4 /* DMA DREQ<1> Status register */
	66	#define DRQSR2 0x00e8 /* DMA DREQ<2> Status register */
	67	#define DINT 0x00f0 /* DMA Interrupt register */
	68	#define DRCMR0 0x0100 /* Request to Channel Map register 0 */
	69	#define DRCMR63 0x01fc /* Request to Channel Map register 63 */
	70	#define D_CH0 0x0200 /* Channel 0 Descriptor start */
	71	#define DRCMR64 0x1100 /* Request to Channel Map register 64 */
	72	#define DRCMR74 0x1128 /* Request to Channel Map register 74 */
	73
	74	/* Per-channel register */
	75	#define DDADR 0x00
	76	#define DSADR 0x01
	77	#define DTADR 0x02
	78	#define DCMD 0x03
	79
	80	/* Bit-field masks */
	81	#define DRCMR_CHLNUM 0x1f
	82	#define DRCMR_MAPVLD (1 << 7)
	83	#define DDADR_STOP (1 << 0)
	84	#define DDADR_BREN (1 << 1)
	85	#define DCMD_LEN 0x1fff
	86	#define DCMD_WIDTH(x) (1 << ((((x) >> 14) & 3) - 1))
	87	#define DCMD_SIZE(x) (4 << (((x) >> 16) & 3))
	88	#define DCMD_FLYBYT (1 << 19)
	89	#define DCMD_FLYBYS (1 << 20)
	90	#define DCMD_ENDIRQEN (1 << 21)
	91	#define DCMD_STARTIRQEN (1 << 22)
	92	#define DCMD_CMPEN (1 << 25)
	93	#define DCMD_FLOWTRG (1 << 28)
	94	#define DCMD_FLOWSRC (1 << 29)
	95	#define DCMD_INCTRGADDR (1 << 30)
	96	#define DCMD_INCSRCADDR (1 << 31)
	97	#define DCSR_BUSERRINTR (1 << 0)
	98	#define DCSR_STARTINTR (1 << 1)
	99	#define DCSR_ENDINTR (1 << 2)
	100	#define DCSR_STOPINTR (1 << 3)
	101	#define DCSR_RASINTR (1 << 4)
	102	#define DCSR_REQPEND (1 << 8)
	103	#define DCSR_EORINT (1 << 9)
	104	#define DCSR_CMPST (1 << 10)
	105	#define DCSR_MASKRUN (1 << 22)
	106	#define DCSR_RASIRQEN (1 << 23)
	107	#define DCSR_CLRCMPST (1 << 24)
	108	#define DCSR_SETCMPST (1 << 25)
	109	#define DCSR_EORSTOPEN (1 << 26)
	110	#define DCSR_EORJMPEN (1 << 27)
	111	#define DCSR_EORIRQEN (1 << 28)
	112	#define DCSR_STOPIRQEN (1 << 29)
	113	#define DCSR_NODESCFETCH (1 << 30)
	114	#define DCSR_RUN (1 << 31)
	115
bc24a225	116	static inline void pxa2xx_dma_update(PXA2xxDMAState *s, int ch)
c1713132 AZ	117	{
	118	if (ch >= 0) {
	119	if ((s->chan[ch].state & DCSR_STOPIRQEN) &&
	120	(s->chan[ch].state & DCSR_STOPINTR))
	121	s->stopintr \|= 1 << ch;
	122	else
	123	s->stopintr &= ~(1 << ch);
	124
	125	if ((s->chan[ch].state & DCSR_EORIRQEN) &&
	126	(s->chan[ch].state & DCSR_EORINT))
	127	s->eorintr \|= 1 << ch;
	128	else
	129	s->eorintr &= ~(1 << ch);
	130
	131	if ((s->chan[ch].state & DCSR_RASIRQEN) &&
	132	(s->chan[ch].state & DCSR_RASINTR))
	133	s->rasintr \|= 1 << ch;
	134	else
	135	s->rasintr &= ~(1 << ch);
	136
	137	if (s->chan[ch].state & DCSR_STARTINTR)
	138	s->startintr \|= 1 << ch;
	139	else
	140	s->startintr &= ~(1 << ch);
	141
	142	if (s->chan[ch].state & DCSR_ENDINTR)
	143	s->endintr \|= 1 << ch;
	144	else
	145	s->endintr &= ~(1 << ch);
	146	}
	147
	148	if (s->stopintr \| s->eorintr \| s->rasintr \| s->startintr \| s->endintr)
	149	qemu_irq_raise(s->irq);
	150	else
	151	qemu_irq_lower(s->irq);
	152	}
	153
	154	static inline void pxa2xx_dma_descriptor_fetch(
bc24a225	155	PXA2xxDMAState *s, int ch)
c1713132 AZ	156	{
c1713132 AZ	157	uint32_t desc[4];
a8170e5e	158	hwaddr daddr = s->chan[ch].descr & ~0xf;
c1713132 AZ	159	if ((s->chan[ch].descr & DDADR_BREN) && (s->chan[ch].state & DCSR_CMPST))
	160	daddr += 32;
	161
e1fe50dc	162	cpu_physical_memory_read(daddr, desc, 16);
c1713132 AZ	163	s->chan[ch].descr = desc[DDADR];
	164	s->chan[ch].src = desc[DSADR];
	165	s->chan[ch].dest = desc[DTADR];
	166	s->chan[ch].cmd = desc[DCMD];
	167
	168	if (s->chan[ch].cmd & DCMD_FLOWSRC)
	169	s->chan[ch].src &= ~3;
	170	if (s->chan[ch].cmd & DCMD_FLOWTRG)
	171	s->chan[ch].dest &= ~3;
	172
	173	if (s->chan[ch].cmd & (DCMD_CMPEN \| DCMD_FLYBYS \| DCMD_FLYBYT))
a89f364a	174	printf("%s: unsupported mode in channel %i\n", __func__, ch);
c1713132 AZ	175
	176	if (s->chan[ch].cmd & DCMD_STARTIRQEN)
	177	s->chan[ch].state \|= DCSR_STARTINTR;
	178	}
	179
bc24a225	180	static void pxa2xx_dma_run(PXA2xxDMAState *s)
c1713132 AZ	181	{
	182	int c, srcinc, destinc;
	183	uint32_t n, size;
	184	uint32_t width;
	185	uint32_t length;
b55266b5	186	uint8_t buffer[32];
bc24a225	187	PXA2xxDMAChannel *ch;
c1713132 AZ	188
	189	if (s->running ++)
	190	return;
	191
	192	while (s->running) {
	193	s->running = 1;
	194	for (c = 0; c < s->channels; c ++) {
	195	ch = &s->chan[c];
	196
	197	while ((ch->state & DCSR_RUN) && !(ch->state & DCSR_STOPINTR)) {
	198	/* Test for pending requests */
	199	if ((ch->cmd & (DCMD_FLOWSRC \| DCMD_FLOWTRG)) && !ch->request)
	200	break;
	201
	202	length = ch->cmd & DCMD_LEN;
	203	size = DCMD_SIZE(ch->cmd);
	204	width = DCMD_WIDTH(ch->cmd);
	205
	206	srcinc = (ch->cmd & DCMD_INCSRCADDR) ? width : 0;
	207	destinc = (ch->cmd & DCMD_INCTRGADDR) ? width : 0;
	208
	209	while (length) {
	210	size = MIN(length, size);
	211
	212	for (n = 0; n < size; n += width) {
	213	cpu_physical_memory_read(ch->src, buffer + n, width);
	214	ch->src += srcinc;
	215	}
	216
	217	for (n = 0; n < size; n += width) {
	218	cpu_physical_memory_write(ch->dest, buffer + n, width);
	219	ch->dest += destinc;
	220	}
	221
	222	length -= size;
	223
	224	if ((ch->cmd & (DCMD_FLOWSRC \| DCMD_FLOWTRG)) &&
	225	!ch->request) {
	226	ch->state \|= DCSR_EORINT;
	227	if (ch->state & DCSR_EORSTOPEN)
	228	ch->state \|= DCSR_STOPINTR;
	229	if ((ch->state & DCSR_EORJMPEN) &&
	230	!(ch->state & DCSR_NODESCFETCH))
	231	pxa2xx_dma_descriptor_fetch(s, c);
	232	break;
7d37435b	233	}
c1713132 AZ	234	}
	235
	236	ch->cmd = (ch->cmd & ~DCMD_LEN) \| length;
	237
	238	/* Is the transfer complete now? */
	239	if (!length) {
	240	if (ch->cmd & DCMD_ENDIRQEN)
	241	ch->state \|= DCSR_ENDINTR;
	242
	243	if ((ch->state & DCSR_NODESCFETCH) \|\|
	244	(ch->descr & DDADR_STOP) \|\|
	245	(ch->state & DCSR_EORSTOPEN)) {
	246	ch->state \|= DCSR_STOPINTR;
	247	ch->state &= ~DCSR_RUN;
	248
	249	break;
	250	}
	251
	252	ch->state \|= DCSR_STOPINTR;
	253	break;
	254	}
	255	}
	256	}
	257
	258	s->running --;
	259	}
	260	}
	261
a8170e5e	262	static uint64_t pxa2xx_dma_read(void *opaque, hwaddr offset,
00049a12	263	unsigned size)
c1713132	264	{
bc24a225	265	PXA2xxDMAState s = (PXA2xxDMAState ) opaque;
c1713132	266	unsigned int channel;
c1713132	267
00049a12	268	if (size != 4) {
a89f364a	269	hw_error("%s: Bad access width\n", __func__);
00049a12 AK	270	return 5;
	271	}
	272
c1713132 AZ	273	switch (offset) {
	274	case DRCMR64 ... DRCMR74:
	275	offset -= DRCMR64 - DRCMR0 - (64 << 2);
	276	/* Fall through */
	277	case DRCMR0 ... DRCMR63:
	278	channel = (offset - DRCMR0) >> 2;
	279	return s->req[channel];
	280
	281	case DRQSR0:
	282	case DRQSR1:
	283	case DRQSR2:
	284	return 0;
	285
	286	case DCSR0 ... DCSR31:
	287	channel = offset >> 2;
7d37435b	288	if (s->chan[channel].request)
c1713132 AZ	289	return s->chan[channel].state \| DCSR_REQPEND;
	290	return s->chan[channel].state;
	291
	292	case DINT:
	293	return s->stopintr \| s->eorintr \| s->rasintr \|
	294	s->startintr \| s->endintr;
	295
	296	case DALGN:
	297	return s->align;
	298
	299	case DPCSR:
	300	return s->pio;
	301	}
	302
	303	if (offset >= D_CH0 && offset < D_CH0 + (s->channels << 4)) {
	304	channel = (offset - D_CH0) >> 4;
	305	switch ((offset & 0x0f) >> 2) {
	306	case DDADR:
	307	return s->chan[channel].descr;
	308	case DSADR:
	309	return s->chan[channel].src;
	310	case DTADR:
	311	return s->chan[channel].dest;
	312	case DCMD:
	313	return s->chan[channel].cmd;
	314	}
	315	}
	316
a89f364a	317	hw_error("%s: Bad offset 0x" TARGET_FMT_plx "\n", __func__, offset);
c1713132 AZ	318	return 7;
	319	}
	320
a8170e5e	321	static void pxa2xx_dma_write(void *opaque, hwaddr offset,
00049a12	322	uint64_t value, unsigned size)
c1713132	323	{
bc24a225	324	PXA2xxDMAState s = (PXA2xxDMAState ) opaque;
c1713132	325	unsigned int channel;
c1713132	326
00049a12	327	if (size != 4) {
a89f364a	328	hw_error("%s: Bad access width\n", __func__);
00049a12 AK	329	return;
	330	}
	331
c1713132 AZ	332	switch (offset) {
	333	case DRCMR64 ... DRCMR74:
	334	offset -= DRCMR64 - DRCMR0 - (64 << 2);
	335	/* Fall through */
	336	case DRCMR0 ... DRCMR63:
	337	channel = (offset - DRCMR0) >> 2;
	338
	339	if (value & DRCMR_MAPVLD)
	340	if ((value & DRCMR_CHLNUM) > s->channels)
2ac71179	341	hw_error("%s: Bad DMA channel %i\n",
a89f364a	342	__func__, (unsigned)value & DRCMR_CHLNUM);
c1713132 AZ	343
	344	s->req[channel] = value;
	345	break;
	346
	347	case DRQSR0:
	348	case DRQSR1:
	349	case DRQSR2:
	350	/* Nothing to do */
	351	break;
	352
	353	case DCSR0 ... DCSR31:
	354	channel = offset >> 2;
	355	s->chan[channel].state &= 0x0000071f & ~(value &
	356	(DCSR_EORINT \| DCSR_ENDINTR \|
	357	DCSR_STARTINTR \| DCSR_BUSERRINTR));
	358	s->chan[channel].state \|= value & 0xfc800000;
	359
	360	if (s->chan[channel].state & DCSR_STOPIRQEN)
	361	s->chan[channel].state &= ~DCSR_STOPINTR;
	362
	363	if (value & DCSR_NODESCFETCH) {
	364	/* No-descriptor-fetch mode */
e1dad5a6 AZ	365	if (value & DCSR_RUN) {
e1dad5a6 AZ	366	s->chan[channel].state &= ~DCSR_STOPINTR;
c1713132	367	pxa2xx_dma_run(s);
e1dad5a6	368	}
c1713132 AZ	369	} else {
	370	/* Descriptor-fetch mode */
	371	if (value & DCSR_RUN) {
	372	s->chan[channel].state &= ~DCSR_STOPINTR;
	373	pxa2xx_dma_descriptor_fetch(s, channel);
	374	pxa2xx_dma_run(s);
	375	}
	376	}
	377
	378	/* Shouldn't matter as our DMA is synchronous. */
	379	if (!(value & (DCSR_RUN \| DCSR_MASKRUN)))
	380	s->chan[channel].state \|= DCSR_STOPINTR;
	381
	382	if (value & DCSR_CLRCMPST)
	383	s->chan[channel].state &= ~DCSR_CMPST;
	384	if (value & DCSR_SETCMPST)
	385	s->chan[channel].state \|= DCSR_CMPST;
	386
	387	pxa2xx_dma_update(s, channel);
	388	break;
	389
	390	case DALGN:
	391	s->align = value;
	392	break;
	393
	394	case DPCSR:
	395	s->pio = value & 0x80000001;
	396	break;
	397
	398	default:
	399	if (offset >= D_CH0 && offset < D_CH0 + (s->channels << 4)) {
	400	channel = (offset - D_CH0) >> 4;
	401	switch ((offset & 0x0f) >> 2) {
	402	case DDADR:
	403	s->chan[channel].descr = value;
	404	break;
	405	case DSADR:
	406	s->chan[channel].src = value;
	407	break;
	408	case DTADR:
	409	s->chan[channel].dest = value;
	410	break;
	411	case DCMD:
	412	s->chan[channel].cmd = value;
	413	break;
	414	default:
	415	goto fail;
	416	}
	417
	418	break;
	419	}
	420	fail:
a89f364a	421	hw_error("%s: Bad offset " TARGET_FMT_plx "\n", __func__, offset);
c1713132 AZ	422	}
	423	}
	424
00049a12 AK	425	static const MemoryRegionOps pxa2xx_dma_ops = {
	426	.read = pxa2xx_dma_read,
	427	.write = pxa2xx_dma_write,
	428	.endianness = DEVICE_NATIVE_ENDIAN,
c1713132 AZ	429	};
c1713132 AZ	430
f114c826 AZ	431	static void pxa2xx_dma_request(void *opaque, int req_num, int on)
	432	{
	433	PXA2xxDMAState *s = opaque;
	434	int ch;
	435	if (req_num < 0 \|\| req_num >= PXA2XX_DMA_NUM_REQUESTS)
a89f364a	436	hw_error("%s: Bad DMA request %i\n", __func__, req_num);
f114c826 AZ	437
	438	if (!(s->req[req_num] & DRCMR_MAPVLD))
	439	return;
	440	ch = s->req[req_num] & DRCMR_CHLNUM;
	441
	442	if (!s->chan[ch].request && on)
	443	s->chan[ch].state \|= DCSR_RASINTR;
	444	else
	445	s->chan[ch].state &= ~DCSR_RASINTR;
	446	if (s->chan[ch].request && !on)
	447	s->chan[ch].state \|= DCSR_EORINT;
	448
	449	s->chan[ch].request = on;
	450	if (on) {
	451	pxa2xx_dma_run(s);
	452	pxa2xx_dma_update(s, ch);
	453	}
	454	}
aa941b94	455
c9796d71 XZ	456	static void pxa2xx_dma_init(Object *obj)
	457	{
	458	DeviceState *dev = DEVICE(obj);
	459	PXA2xxDMAState *s = PXA2XX_DMA(obj);
	460	SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
	461
	462	memset(s->req, 0, sizeof(uint8_t) * PXA2XX_DMA_NUM_REQUESTS);
	463
	464	qdev_init_gpio_in(dev, pxa2xx_dma_request, PXA2XX_DMA_NUM_REQUESTS);
	465
	466	memory_region_init_io(&s->iomem, obj, &pxa2xx_dma_ops, s,
	467	"pxa2xx.dma", 0x00010000);
	468	sysbus_init_mmio(sbd, &s->iomem);
	469	sysbus_init_irq(sbd, &s->irq);
	470	}
	471
	472	static void pxa2xx_dma_realize(DeviceState dev, Error *errp)
c1713132	473	{
358cd7ac	474	PXA2xxDMAState *s = PXA2XX_DMA(dev);
00049a12	475	int i;
2115c019 AZ	476
2115c019 AZ	477	if (s->channels <= 0) {
c9796d71 XZ	478	error_setg(errp, "channels value invalid");
c9796d71 XZ	479	return;
2115c019	480	}
c1713132	481
1a13b272	482	s->chan = g_new0(PXA2xxDMAChannel, s->channels);
c1713132	483
c1713132 AZ	484	for (i = 0; i < s->channels; i ++)
c1713132 AZ	485	s->chan[i].state = DCSR_STOPINTR;
c1713132 AZ	486	}
c1713132 AZ	487
a8170e5e	488	DeviceState *pxa27x_dma_init(hwaddr base, qemu_irq irq)
c1713132	489	{
2115c019 AZ	490	DeviceState *dev;
	491
	492	dev = qdev_create(NULL, "pxa2xx-dma");
	493	qdev_prop_set_int32(dev, "channels", PXA27X_DMA_NUM_CHANNELS);
	494	qdev_init_nofail(dev);
	495
1356b98d AF	496	sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
1356b98d AF	497	sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq);
2115c019 AZ	498
2115c019 AZ	499	return dev;
c1713132 AZ	500	}
c1713132 AZ	501
a8170e5e	502	DeviceState *pxa255_dma_init(hwaddr base, qemu_irq irq)
c1713132	503	{
2115c019 AZ	504	DeviceState *dev;
	505
	506	dev = qdev_create(NULL, "pxa2xx-dma");
	507	qdev_prop_set_int32(dev, "channels", PXA27X_DMA_NUM_CHANNELS);
	508	qdev_init_nofail(dev);
	509
1356b98d AF	510	sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
1356b98d AF	511	sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq);
2115c019 AZ	512
2115c019 AZ	513	return dev;
c1713132 AZ	514	}
c1713132 AZ	515
2115c019 AZ	516	static bool is_version_0(void *opaque, int version_id)
	517	{
	518	return version_id == 0;
	519	}
	520
	521	static VMStateDescription vmstate_pxa2xx_dma_chan = {
	522	.name = "pxa2xx_dma_chan",
	523	.version_id = 1,
	524	.minimum_version_id = 1,
2115c019	525	.fields = (VMStateField[]) {
a10394e1 MI	526	VMSTATE_UINT32(descr, PXA2xxDMAChannel),
	527	VMSTATE_UINT32(src, PXA2xxDMAChannel),
	528	VMSTATE_UINT32(dest, PXA2xxDMAChannel),
2115c019 AZ	529	VMSTATE_UINT32(cmd, PXA2xxDMAChannel),
	530	VMSTATE_UINT32(state, PXA2xxDMAChannel),
	531	VMSTATE_INT32(request, PXA2xxDMAChannel),
	532	VMSTATE_END_OF_LIST(),
	533	},
	534	};
	535
	536	static VMStateDescription vmstate_pxa2xx_dma = {
	537	.name = "pxa2xx_dma",
	538	.version_id = 1,
	539	.minimum_version_id = 0,
2115c019 AZ	540	.fields = (VMStateField[]) {
	541	VMSTATE_UNUSED_TEST(is_version_0, 4),
	542	VMSTATE_UINT32(stopintr, PXA2xxDMAState),
	543	VMSTATE_UINT32(eorintr, PXA2xxDMAState),
	544	VMSTATE_UINT32(rasintr, PXA2xxDMAState),
	545	VMSTATE_UINT32(startintr, PXA2xxDMAState),
	546	VMSTATE_UINT32(endintr, PXA2xxDMAState),
	547	VMSTATE_UINT32(align, PXA2xxDMAState),
	548	VMSTATE_UINT32(pio, PXA2xxDMAState),
	549	VMSTATE_BUFFER(req, PXA2xxDMAState),
	550	VMSTATE_STRUCT_VARRAY_POINTER_INT32(chan, PXA2xxDMAState, channels,
	551	vmstate_pxa2xx_dma_chan, PXA2xxDMAChannel),
	552	VMSTATE_END_OF_LIST(),
	553	},
	554	};
	555
999e12bb AL	556	static Property pxa2xx_dma_properties[] = {
	557	DEFINE_PROP_INT32("channels", PXA2xxDMAState, channels, -1),
	558	DEFINE_PROP_END_OF_LIST(),
	559	};
	560
	561	static void pxa2xx_dma_class_init(ObjectClass klass, void data)
	562	{
39bffca2	563	DeviceClass *dc = DEVICE_CLASS(klass);
999e12bb	564
39bffca2 AL	565	dc->desc = "PXA2xx DMA controller";
	566	dc->vmsd = &vmstate_pxa2xx_dma;
	567	dc->props = pxa2xx_dma_properties;
c9796d71	568	dc->realize = pxa2xx_dma_realize;
999e12bb AL	569	}
999e12bb AL	570
8c43a6f0	571	static const TypeInfo pxa2xx_dma_info = {
358cd7ac	572	.name = TYPE_PXA2XX_DMA,
39bffca2 AL	573	.parent = TYPE_SYS_BUS_DEVICE,
39bffca2 AL	574	.instance_size = sizeof(PXA2xxDMAState),
c9796d71	575	.instance_init = pxa2xx_dma_init,
39bffca2	576	.class_init = pxa2xx_dma_class_init,
2115c019 AZ	577	};
2115c019 AZ	578
83f7d43a	579	static void pxa2xx_dma_register_types(void)
2115c019	580	{
39bffca2	581	type_register_static(&pxa2xx_dma_info);
2115c019	582	}
83f7d43a AF	583
83f7d43a AF	584	type_init(pxa2xx_dma_register_types)