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[qemu.git] / hw / display / exynos4210_fimd.c
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30628cb1
MI		 1/*
2 * Samsung exynos4210 Display Controller (FIMD)
3 *
4 * Copyright (c) 2000 - 2011 Samsung Electronics Co., Ltd.
5 * All rights reserved.
6 * Based on LCD controller for Samsung S5PC1xx-based board emulation
7 * by Kirill Batuzov <[email protected]>
8 *
9 * Contributed by Mitsyanko Igor <[email protected]>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
19 * See the GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License along
22 * with this program; if not, see <http://www.gnu.org/licenses/>.
23 */
24
8ef94f0b 25#include "qemu/osdep.h"
64552b6b 26#include "hw/irq.h"
83c9f4ca 27#include "hw/sysbus.h"
28ecbaee
PB		 28#include "ui/console.h"
29#include "ui/pixel_ops.h"
1de7afc9 30#include "qemu/bswap.h"
0b8fa32f 31#include "qemu/module.h"
30628cb1
MI		 32
33/* Debug messages configuration */
34#define EXYNOS4210_FIMD_DEBUG 0
35#define EXYNOS4210_FIMD_MODE_TRACE 0
36
37#if EXYNOS4210_FIMD_DEBUG == 0
38 #define DPRINT_L1(fmt, args...) do { } while (0)
39 #define DPRINT_L2(fmt, args...) do { } while (0)
40 #define DPRINT_ERROR(fmt, args...) do { } while (0)
41#elif EXYNOS4210_FIMD_DEBUG == 1
42 #define DPRINT_L1(fmt, args...) \
43 do {fprintf(stderr, "QEMU FIMD: "fmt, ## args); } while (0)
44 #define DPRINT_L2(fmt, args...) do { } while (0)
45 #define DPRINT_ERROR(fmt, args...) \
46 do {fprintf(stderr, "QEMU FIMD ERROR: "fmt, ## args); } while (0)
47#else
48 #define DPRINT_L1(fmt, args...) \
49 do {fprintf(stderr, "QEMU FIMD: "fmt, ## args); } while (0)
50 #define DPRINT_L2(fmt, args...) \
51 do {fprintf(stderr, "QEMU FIMD: "fmt, ## args); } while (0)
52 #define DPRINT_ERROR(fmt, args...) \
53 do {fprintf(stderr, "QEMU FIMD ERROR: "fmt, ## args); } while (0)
54#endif
55
56#if EXYNOS4210_FIMD_MODE_TRACE == 0
57 #define DPRINT_TRACE(fmt, args...) do { } while (0)
58#else
59 #define DPRINT_TRACE(fmt, args...) \
60 do {fprintf(stderr, "QEMU FIMD: "fmt, ## args); } while (0)
61#endif
62
63#define NUM_OF_WINDOWS 5
64#define FIMD_REGS_SIZE 0x4114
65
66/* Video main control registers */
67#define FIMD_VIDCON0 0x0000
68#define FIMD_VIDCON1 0x0004
69#define FIMD_VIDCON2 0x0008
70#define FIMD_VIDCON3 0x000C
71#define FIMD_VIDCON0_ENVID_F (1 << 0)
72#define FIMD_VIDCON0_ENVID (1 << 1)
73#define FIMD_VIDCON0_ENVID_MASK ((1 << 0) | (1 << 1))
74#define FIMD_VIDCON1_ROMASK 0x07FFE000
75
76/* Video time control registers */
77#define FIMD_VIDTCON_START 0x10
78#define FIMD_VIDTCON_END 0x1C
79#define FIMD_VIDTCON2_SIZE_MASK 0x07FF
80#define FIMD_VIDTCON2_HOR_SHIFT 0
81#define FIMD_VIDTCON2_VER_SHIFT 11
82
83/* Window control registers */
84#define FIMD_WINCON_START 0x0020
85#define FIMD_WINCON_END 0x0030
86#define FIMD_WINCON_ROMASK 0x82200000
87#define FIMD_WINCON_ENWIN (1 << 0)
88#define FIMD_WINCON_BLD_PIX (1 << 6)
89#define FIMD_WINCON_ALPHA_MUL (1 << 7)
90#define FIMD_WINCON_ALPHA_SEL (1 << 1)
91#define FIMD_WINCON_SWAP 0x078000
92#define FIMD_WINCON_SWAP_SHIFT 15
93#define FIMD_WINCON_SWAP_WORD 0x1
94#define FIMD_WINCON_SWAP_HWORD 0x2
95#define FIMD_WINCON_SWAP_BYTE 0x4
96#define FIMD_WINCON_SWAP_BITS 0x8
97#define FIMD_WINCON_BUFSTAT_L (1 << 21)
98#define FIMD_WINCON_BUFSTAT_H (1 << 31)
99#define FIMD_WINCON_BUFSTATUS ((1 << 21) | (1 << 31))
100#define FIMD_WINCON_BUF0_STAT ((0 << 21) | (0 << 31))
101#define FIMD_WINCON_BUF1_STAT ((1 << 21) | (0 << 31))
6c549dc1 102#define FIMD_WINCON_BUF2_STAT ((0 << 21) | (1U << 31))
30628cb1
MI		 103#define FIMD_WINCON_BUFSELECT ((1 << 20) | (1 << 30))
104#define FIMD_WINCON_BUF0_SEL ((0 << 20) | (0 << 30))
105#define FIMD_WINCON_BUF1_SEL ((1 << 20) | (0 << 30))
106#define FIMD_WINCON_BUF2_SEL ((0 << 20) | (1 << 30))
107#define FIMD_WINCON_BUFMODE (1 << 14)
108#define IS_PALETTIZED_MODE(w) (w->wincon & 0xC)
109#define PAL_MODE_WITH_ALPHA(x) ((x) == 7)
110#define WIN_BPP_MODE(w) ((w->wincon >> 2) & 0xF)
111#define WIN_BPP_MODE_WITH_ALPHA(w) \
112 (WIN_BPP_MODE(w) == 0xD || WIN_BPP_MODE(w) == 0xE)
113
114/* Shadow control register */
115#define FIMD_SHADOWCON 0x0034
116#define FIMD_WINDOW_PROTECTED(s, w) ((s) & (1 << (10 + (w))))
117/* Channel mapping control register */
118#define FIMD_WINCHMAP 0x003C
119
120/* Window position control registers */
121#define FIMD_VIDOSD_START 0x0040
122#define FIMD_VIDOSD_END 0x0088
123#define FIMD_VIDOSD_COORD_MASK 0x07FF
124#define FIMD_VIDOSD_HOR_SHIFT 11
125#define FIMD_VIDOSD_VER_SHIFT 0
126#define FIMD_VIDOSD_ALPHA_AEN0 0xFFF000
127#define FIMD_VIDOSD_AEN0_SHIFT 12
128#define FIMD_VIDOSD_ALPHA_AEN1 0x000FFF
129
130/* Frame buffer address registers */
131#define FIMD_VIDWADD0_START 0x00A0
132#define FIMD_VIDWADD0_END 0x00C4
133#define FIMD_VIDWADD0_END 0x00C4
134#define FIMD_VIDWADD1_START 0x00D0
135#define FIMD_VIDWADD1_END 0x00F4
136#define FIMD_VIDWADD2_START 0x0100
137#define FIMD_VIDWADD2_END 0x0110
138#define FIMD_VIDWADD2_PAGEWIDTH 0x1FFF
139#define FIMD_VIDWADD2_OFFSIZE 0x1FFF
140#define FIMD_VIDWADD2_OFFSIZE_SHIFT 13
141#define FIMD_VIDW0ADD0_B2 0x20A0
142#define FIMD_VIDW4ADD0_B2 0x20C0
143
144/* Video interrupt control registers */
145#define FIMD_VIDINTCON0 0x130
146#define FIMD_VIDINTCON1 0x134
147
148/* Window color key registers */
149#define FIMD_WKEYCON_START 0x140
150#define FIMD_WKEYCON_END 0x15C
151#define FIMD_WKEYCON0_COMPKEY 0x00FFFFFF
152#define FIMD_WKEYCON0_CTL_SHIFT 24
153#define FIMD_WKEYCON0_DIRCON (1 << 24)
154#define FIMD_WKEYCON0_KEYEN (1 << 25)
155#define FIMD_WKEYCON0_KEYBLEN (1 << 26)
156/* Window color key alpha control register */
157#define FIMD_WKEYALPHA_START 0x160
158#define FIMD_WKEYALPHA_END 0x16C
159
160/* Dithering control register */
161#define FIMD_DITHMODE 0x170
162
163/* Window alpha control registers */
164#define FIMD_VIDALPHA_ALPHA_LOWER 0x000F0F0F
165#define FIMD_VIDALPHA_ALPHA_UPPER 0x00F0F0F0
166#define FIMD_VIDWALPHA_START 0x21C
167#define FIMD_VIDWALPHA_END 0x240
168
169/* Window color map registers */
170#define FIMD_WINMAP_START 0x180
171#define FIMD_WINMAP_END 0x190
172#define FIMD_WINMAP_EN (1 << 24)
173#define FIMD_WINMAP_COLOR_MASK 0x00FFFFFF
174
175/* Window palette control registers */
176#define FIMD_WPALCON_HIGH 0x019C
177#define FIMD_WPALCON_LOW 0x01A0
178#define FIMD_WPALCON_UPDATEEN (1 << 9)
179#define FIMD_WPAL_W0PAL_L 0x07
180#define FIMD_WPAL_W0PAL_L_SHT 0
181#define FIMD_WPAL_W1PAL_L 0x07
182#define FIMD_WPAL_W1PAL_L_SHT 3
183#define FIMD_WPAL_W2PAL_L 0x01
184#define FIMD_WPAL_W2PAL_L_SHT 6
185#define FIMD_WPAL_W2PAL_H 0x06
186#define FIMD_WPAL_W2PAL_H_SHT 8
187#define FIMD_WPAL_W3PAL_L 0x01
188#define FIMD_WPAL_W3PAL_L_SHT 7
189#define FIMD_WPAL_W3PAL_H 0x06
190#define FIMD_WPAL_W3PAL_H_SHT 12
191#define FIMD_WPAL_W4PAL_L 0x01
192#define FIMD_WPAL_W4PAL_L_SHT 8
193#define FIMD_WPAL_W4PAL_H 0x06
194#define FIMD_WPAL_W4PAL_H_SHT 16
195
196/* Trigger control registers */
197#define FIMD_TRIGCON 0x01A4
198#define FIMD_TRIGCON_ROMASK 0x00000004
199
200/* LCD I80 Interface Control */
201#define FIMD_I80IFCON_START 0x01B0
202#define FIMD_I80IFCON_END 0x01BC
203/* Color gain control register */
204#define FIMD_COLORGAINCON 0x01C0
205/* LCD i80 Interface Command Control */
206#define FIMD_LDI_CMDCON0 0x01D0
207#define FIMD_LDI_CMDCON1 0x01D4
208/* I80 System Interface Manual Command Control */
209#define FIMD_SIFCCON0 0x01E0
210#define FIMD_SIFCCON2 0x01E8
211
212/* Hue Control Registers */
213#define FIMD_HUECOEFCR_START 0x01EC
214#define FIMD_HUECOEFCR_END 0x01F4
215#define FIMD_HUECOEFCB_START 0x01FC
216#define FIMD_HUECOEFCB_END 0x0208
217#define FIMD_HUEOFFSET 0x020C
218
219/* Video interrupt control registers */
220#define FIMD_VIDINT_INTFIFOPEND (1 << 0)
221#define FIMD_VIDINT_INTFRMPEND (1 << 1)
222#define FIMD_VIDINT_INTI80PEND (1 << 2)
223#define FIMD_VIDINT_INTEN (1 << 0)
224#define FIMD_VIDINT_INTFIFOEN (1 << 1)
225#define FIMD_VIDINT_INTFRMEN (1 << 12)
226#define FIMD_VIDINT_I80IFDONE (1 << 17)
227
228/* Window blend equation control registers */
229#define FIMD_BLENDEQ_START 0x0244
230#define FIMD_BLENDEQ_END 0x0250
231#define FIMD_BLENDCON 0x0260
232#define FIMD_ALPHA_8BIT (1 << 0)
233#define FIMD_BLENDEQ_COEF_MASK 0xF
234
235/* Window RTQOS Control Registers */
236#define FIMD_WRTQOSCON_START 0x0264
237#define FIMD_WRTQOSCON_END 0x0274
238
239/* LCD I80 Interface Command */
240#define FIMD_I80IFCMD_START 0x0280
241#define FIMD_I80IFCMD_END 0x02AC
242
243/* Shadow windows control registers */
244#define FIMD_SHD_ADD0_START 0x40A0
245#define FIMD_SHD_ADD0_END 0x40C0
246#define FIMD_SHD_ADD1_START 0x40D0
247#define FIMD_SHD_ADD1_END 0x40F0
248#define FIMD_SHD_ADD2_START 0x4100
249#define FIMD_SHD_ADD2_END 0x4110
250
251/* Palette memory */
252#define FIMD_PAL_MEM_START 0x2400
253#define FIMD_PAL_MEM_END 0x37FC
254/* Palette memory aliases for windows 0 and 1 */
255#define FIMD_PALMEM_AL_START 0x0400
256#define FIMD_PALMEM_AL_END 0x0BFC
257
258typedef struct {
259 uint8_t r, g, b;
260 /* D[31..24]dummy, D[23..16]rAlpha, D[15..8]gAlpha, D[7..0]bAlpha */
261 uint32_t a;
262} rgba;
263#define RGBA_SIZE 7
264
265typedef void pixel_to_rgb_func(uint32_t pixel, rgba *p);
266typedef struct Exynos4210fimdWindow Exynos4210fimdWindow;
267
268struct Exynos4210fimdWindow {
269 uint32_t wincon; /* Window control register */
270 uint32_t buf_start[3]; /* Start address for video frame buffer */
271 uint32_t buf_end[3]; /* End address for video frame buffer */
272 uint32_t keycon[2]; /* Window color key registers */
273 uint32_t keyalpha; /* Color key alpha control register */
274 uint32_t winmap; /* Window color map register */
275 uint32_t blendeq; /* Window blending equation control register */
276 uint32_t rtqoscon; /* Window RTQOS Control Registers */
277 uint32_t palette[256]; /* Palette RAM */
278 uint32_t shadow_buf_start; /* Start address of shadow frame buffer */
279 uint32_t shadow_buf_end; /* End address of shadow frame buffer */
280 uint32_t shadow_buf_size; /* Virtual shadow screen width */
281
282 pixel_to_rgb_func *pixel_to_rgb;
283 void (*draw_line)(Exynos4210fimdWindow *w, uint8_t *src, uint8_t *dst,
284 bool blend);
285 uint32_t (*get_alpha)(Exynos4210fimdWindow *w, uint32_t pix_a);
286 uint16_t lefttop_x, lefttop_y; /* VIDOSD0 register */
287 uint16_t rightbot_x, rightbot_y; /* VIDOSD1 register */
288 uint32_t osdsize; /* VIDOSD2&3 register */
289 uint32_t alpha_val[2]; /* VIDOSD2&3, VIDWALPHA registers */
290 uint16_t virtpage_width; /* VIDWADD2 register */
291 uint16_t virtpage_offsize; /* VIDWADD2 register */
292 MemoryRegionSection mem_section; /* RAM fragment containing framebuffer */
293 uint8_t *host_fb_addr; /* Host pointer to window's framebuffer */
a8170e5e 294 hwaddr fb_len; /* Framebuffer length */
30628cb1
MI		 295};
296
f27321aa
AF		 297#define TYPE_EXYNOS4210_FIMD "exynos4210.fimd"
298#define EXYNOS4210_FIMD(obj) \
299 OBJECT_CHECK(Exynos4210fimdState, (obj), TYPE_EXYNOS4210_FIMD)
300
30628cb1 301typedef struct {
f27321aa
AF		 302 SysBusDevice parent_obj;
303
30628cb1 304 MemoryRegion iomem;
c78f7137 305 QemuConsole *console;
30628cb1
MI		 306 qemu_irq irq[3];
307
308 uint32_t vidcon[4]; /* Video main control registers 0-3 */
309 uint32_t vidtcon[4]; /* Video time control registers 0-3 */
310 uint32_t shadowcon; /* Window shadow control register */
311 uint32_t winchmap; /* Channel mapping control register */
312 uint32_t vidintcon[2]; /* Video interrupt control registers */
313 uint32_t dithmode; /* Dithering control register */
314 uint32_t wpalcon[2]; /* Window palette control registers */
315 uint32_t trigcon; /* Trigger control register */
316 uint32_t i80ifcon[4]; /* I80 interface control registers */
317 uint32_t colorgaincon; /* Color gain control register */
318 uint32_t ldi_cmdcon[2]; /* LCD I80 interface command control */
319 uint32_t sifccon[3]; /* I80 System Interface Manual Command Control */
320 uint32_t huecoef_cr[4]; /* Hue control registers */
321 uint32_t huecoef_cb[4]; /* Hue control registers */
322 uint32_t hueoffset; /* Hue offset control register */
323 uint32_t blendcon; /* Blending control register */
324 uint32_t i80ifcmd[12]; /* LCD I80 Interface Command */
325
326 Exynos4210fimdWindow window[5]; /* Window-specific registers */
327 uint8_t *ifb; /* Internal frame buffer */
328 bool invalidate; /* Image needs to be redrawn */
329 bool enabled; /* Display controller is enabled */
330} Exynos4210fimdState;
331
332/* Perform byte/halfword/word swap of data according to WINCON */
333static inline void fimd_swap_data(unsigned int swap_ctl, uint64_t *data)
334{
335 int i;
336 uint64_t res;
337 uint64_t x = *data;
338
339 if (swap_ctl & FIMD_WINCON_SWAP_BITS) {
340 res = 0;
341 for (i = 0; i < 64; i++) {
644ead5b 342 if (x & (1ULL << (63 - i))) {
30628cb1
MI		 343 res |= (1ULL << i);
344 }
345 }
346 x = res;
347 }
348
349 if (swap_ctl & FIMD_WINCON_SWAP_BYTE) {
350 x = bswap64(x);
351 }
352
353 if (swap_ctl & FIMD_WINCON_SWAP_HWORD) {
354 x = ((x & 0x000000000000FFFFULL) << 48) |
355 ((x & 0x00000000FFFF0000ULL) << 16) |
356 ((x & 0x0000FFFF00000000ULL) >> 16) |
357 ((x & 0xFFFF000000000000ULL) >> 48);
358 }
359
360 if (swap_ctl & FIMD_WINCON_SWAP_WORD) {
361 x = ((x & 0x00000000FFFFFFFFULL) << 32) |
362 ((x & 0xFFFFFFFF00000000ULL) >> 32);
363 }
364
365 *data = x;
366}
367
368/* Conversion routines of Pixel data from frame buffer area to internal RGBA
369 * pixel representation.
370 * Every color component internally represented as 8-bit value. If original
371 * data has less than 8 bit for component, data is extended to 8 bit. For
372 * example, if blue component has only two possible values 0 and 1 it will be
373 * extended to 0 and 0xFF */
374
375/* One bit for alpha representation */
376#define DEF_PIXEL_TO_RGB_A1(N, R, G, B) \
377static void N(uint32_t pixel, rgba *p) \
378{ \
379 p->b = ((pixel & ((1 << (B)) - 1)) << (8 - (B))) | \
380 ((pixel >> (2 * (B) - 8)) & ((1 << (8 - (B))) - 1)); \
381 pixel >>= (B); \
382 p->g = (pixel & ((1 << (G)) - 1)) << (8 - (G)) | \
383 ((pixel >> (2 * (G) - 8)) & ((1 << (8 - (G))) - 1)); \
384 pixel >>= (G); \
385 p->r = (pixel & ((1 << (R)) - 1)) << (8 - (R)) | \
386 ((pixel >> (2 * (R) - 8)) & ((1 << (8 - (R))) - 1)); \
387 pixel >>= (R); \
388 p->a = (pixel & 0x1); \
389}
390
391DEF_PIXEL_TO_RGB_A1(pixel_a444_to_rgb, 4, 4, 4)
392DEF_PIXEL_TO_RGB_A1(pixel_a555_to_rgb, 5, 5, 5)
393DEF_PIXEL_TO_RGB_A1(pixel_a666_to_rgb, 6, 6, 6)
394DEF_PIXEL_TO_RGB_A1(pixel_a665_to_rgb, 6, 6, 5)
395DEF_PIXEL_TO_RGB_A1(pixel_a888_to_rgb, 8, 8, 8)
396DEF_PIXEL_TO_RGB_A1(pixel_a887_to_rgb, 8, 8, 7)
397
398/* Alpha component is always zero */
399#define DEF_PIXEL_TO_RGB_A0(N, R, G, B) \
400static void N(uint32_t pixel, rgba *p) \
401{ \
402 p->b = ((pixel & ((1 << (B)) - 1)) << (8 - (B))) | \
403 ((pixel >> (2 * (B) - 8)) & ((1 << (8 - (B))) - 1)); \
404 pixel >>= (B); \
405 p->g = (pixel & ((1 << (G)) - 1)) << (8 - (G)) | \
406 ((pixel >> (2 * (G) - 8)) & ((1 << (8 - (G))) - 1)); \
407 pixel >>= (G); \
408 p->r = (pixel & ((1 << (R)) - 1)) << (8 - (R)) | \
409 ((pixel >> (2 * (R) - 8)) & ((1 << (8 - (R))) - 1)); \
410 p->a = 0x0; \
411}
412
413DEF_PIXEL_TO_RGB_A0(pixel_565_to_rgb, 5, 6, 5)
414DEF_PIXEL_TO_RGB_A0(pixel_555_to_rgb, 5, 5, 5)
415DEF_PIXEL_TO_RGB_A0(pixel_666_to_rgb, 6, 6, 6)
416DEF_PIXEL_TO_RGB_A0(pixel_888_to_rgb, 8, 8, 8)
417
418/* Alpha component has some meaningful value */
419#define DEF_PIXEL_TO_RGB_A(N, R, G, B, A) \
420static void N(uint32_t pixel, rgba *p) \
421{ \
422 p->b = ((pixel & ((1 << (B)) - 1)) << (8 - (B))) | \
423 ((pixel >> (2 * (B) - 8)) & ((1 << (8 - (B))) - 1)); \
424 pixel >>= (B); \
425 p->g = (pixel & ((1 << (G)) - 1)) << (8 - (G)) | \
426 ((pixel >> (2 * (G) - 8)) & ((1 << (8 - (G))) - 1)); \
427 pixel >>= (G); \
428 p->r = (pixel & ((1 << (R)) - 1)) << (8 - (R)) | \
429 ((pixel >> (2 * (R) - 8)) & ((1 << (8 - (R))) - 1)); \
430 pixel >>= (R); \
431 p->a = (pixel & ((1 << (A)) - 1)) << (8 - (A)) | \
432 ((pixel >> (2 * (A) - 8)) & ((1 << (8 - (A))) - 1)); \
433 p->a = p->a | (p->a << 8) | (p->a << 16); \
434}
435
436DEF_PIXEL_TO_RGB_A(pixel_4444_to_rgb, 4, 4, 4, 4)
437DEF_PIXEL_TO_RGB_A(pixel_8888_to_rgb, 8, 8, 8, 8)
438
439/* Lookup table to extent 2-bit color component to 8 bit */
440static const uint8_t pixel_lutable_2b[4] = {
441 0x0, 0x55, 0xAA, 0xFF
442};
443/* Lookup table to extent 3-bit color component to 8 bit */
444static const uint8_t pixel_lutable_3b[8] = {
445 0x0, 0x24, 0x49, 0x6D, 0x92, 0xB6, 0xDB, 0xFF
446};
447/* Special case for a232 bpp mode */
448static void pixel_a232_to_rgb(uint32_t pixel, rgba *p)
449{
450 p->b = pixel_lutable_2b[(pixel & 0x3)];
451 pixel >>= 2;
452 p->g = pixel_lutable_3b[(pixel & 0x7)];
453 pixel >>= 3;
454 p->r = pixel_lutable_2b[(pixel & 0x3)];
455 pixel >>= 2;
456 p->a = (pixel & 0x1);
457}
458
459/* Special case for (5+1, 5+1, 5+1) mode. Data bit 15 is common LSB
460 * for all three color components */
461static void pixel_1555_to_rgb(uint32_t pixel, rgba *p)
462{
463 uint8_t comm = (pixel >> 15) & 1;
464 p->b = ((((pixel & 0x1F) << 1) | comm) << 2) | ((pixel >> 3) & 0x3);
465 pixel >>= 5;
466 p->g = ((((pixel & 0x1F) << 1) | comm) << 2) | ((pixel >> 3) & 0x3);
467 pixel >>= 5;
468 p->r = ((((pixel & 0x1F) << 1) | comm) << 2) | ((pixel >> 3) & 0x3);
469 p->a = 0x0;
470}
471
472/* Put/get pixel to/from internal LCD Controller framebuffer */
473
474static int put_pixel_ifb(const rgba p, uint8_t *d)
475{
476 *(uint8_t *)d++ = p.r;
477 *(uint8_t *)d++ = p.g;
478 *(uint8_t *)d++ = p.b;
479 *(uint32_t *)d = p.a;
480 return RGBA_SIZE;
481}
482
483static int get_pixel_ifb(const uint8_t *s, rgba *p)
484{
485 p->r = *(uint8_t *)s++;
486 p->g = *(uint8_t *)s++;
487 p->b = *(uint8_t *)s++;
488 p->a = (*(uint32_t *)s) & 0x00FFFFFF;
489 return RGBA_SIZE;
490}
491
492static pixel_to_rgb_func *palette_data_format[8] = {
493 [0] = pixel_565_to_rgb,
494 [1] = pixel_a555_to_rgb,
495 [2] = pixel_666_to_rgb,
496 [3] = pixel_a665_to_rgb,
497 [4] = pixel_a666_to_rgb,
498 [5] = pixel_888_to_rgb,
499 [6] = pixel_a888_to_rgb,
500 [7] = pixel_8888_to_rgb
501};
502
503/* Returns Index in palette data formats table for given window number WINDOW */
504static uint32_t
505exynos4210_fimd_palette_format(Exynos4210fimdState *s, int window)
506{
507 uint32_t ret;
508
509 switch (window) {
510 case 0:
511 ret = (s->wpalcon[1] >> FIMD_WPAL_W0PAL_L_SHT) & FIMD_WPAL_W0PAL_L;
512 if (ret != 7) {
513 ret = 6 - ret;
514 }
515 break;
516 case 1:
517 ret = (s->wpalcon[1] >> FIMD_WPAL_W1PAL_L_SHT) & FIMD_WPAL_W1PAL_L;
518 if (ret != 7) {
519 ret = 6 - ret;
520 }
521 break;
522 case 2:
523 ret = ((s->wpalcon[0] >> FIMD_WPAL_W2PAL_H_SHT) & FIMD_WPAL_W2PAL_H) |
524 ((s->wpalcon[1] >> FIMD_WPAL_W2PAL_L_SHT) & FIMD_WPAL_W2PAL_L);
525 break;
526 case 3:
527 ret = ((s->wpalcon[0] >> FIMD_WPAL_W3PAL_H_SHT) & FIMD_WPAL_W3PAL_H) |
528 ((s->wpalcon[1] >> FIMD_WPAL_W3PAL_L_SHT) & FIMD_WPAL_W3PAL_L);
529 break;
530 case 4:
531 ret = ((s->wpalcon[0] >> FIMD_WPAL_W4PAL_H_SHT) & FIMD_WPAL_W4PAL_H) |
532 ((s->wpalcon[1] >> FIMD_WPAL_W4PAL_L_SHT) & FIMD_WPAL_W4PAL_L);
533 break;
534 default:
535 hw_error("exynos4210.fimd: incorrect window number %d\n", window);
536 ret = 0;
537 break;
538 }
539 return ret;
540}
541
542#define FIMD_1_MINUS_COLOR(x) \
543 ((0xFF - ((x) & 0xFF)) | (0xFF00 - ((x) & 0xFF00)) | \
544 (0xFF0000 - ((x) & 0xFF0000)))
545#define EXTEND_LOWER_HALFBYTE(x) (((x) & 0xF0F0F) | (((x) << 4) & 0xF0F0F0))
546#define EXTEND_UPPER_HALFBYTE(x) (((x) & 0xF0F0F0) | (((x) >> 4) & 0xF0F0F))
547
548/* Multiply three lower bytes of two 32-bit words with each other.
549 * Each byte with values 0-255 is considered as a number with possible values
550 * in a range [0 - 1] */
551static inline uint32_t fimd_mult_each_byte(uint32_t a, uint32_t b)
552{
553 uint32_t tmp;
554 uint32_t ret;
555
556 ret = ((tmp = (((a & 0xFF) * (b & 0xFF)) / 0xFF)) > 0xFF) ? 0xFF : tmp;
557 ret |= ((tmp = ((((a >> 8) & 0xFF) * ((b >> 8) & 0xFF)) / 0xFF)) > 0xFF) ?
558 0xFF00 : tmp << 8;
559 ret |= ((tmp = ((((a >> 16) & 0xFF) * ((b >> 16) & 0xFF)) / 0xFF)) > 0xFF) ?
560 0xFF0000 : tmp << 16;
561 return ret;
562}
563
564/* For each corresponding bytes of two 32-bit words: (a*b + c*d)
565 * Byte values 0-255 are mapped to a range [0 .. 1] */
566static inline uint32_t
567fimd_mult_and_sum_each_byte(uint32_t a, uint32_t b, uint32_t c, uint32_t d)
568{
569 uint32_t tmp;
570 uint32_t ret;
571
572 ret = ((tmp = (((a & 0xFF) * (b & 0xFF) + (c & 0xFF) * (d & 0xFF)) / 0xFF))
573 > 0xFF) ? 0xFF : tmp;
574 ret |= ((tmp = ((((a >> 8) & 0xFF) * ((b >> 8) & 0xFF) + ((c >> 8) & 0xFF) *
575 ((d >> 8) & 0xFF)) / 0xFF)) > 0xFF) ? 0xFF00 : tmp << 8;
576 ret |= ((tmp = ((((a >> 16) & 0xFF) * ((b >> 16) & 0xFF) +
577 ((c >> 16) & 0xFF) * ((d >> 16) & 0xFF)) / 0xFF)) > 0xFF) ?
578 0xFF0000 : tmp << 16;
579 return ret;
580}
581
582/* These routines cover all possible sources of window's transparent factor
583 * used in blending equation. Choice of routine is affected by WPALCON
584 * registers, BLENDCON register and window's WINCON register */
585
586static uint32_t fimd_get_alpha_pix(Exynos4210fimdWindow *w, uint32_t pix_a)
587{
588 return pix_a;
589}
590
591static uint32_t
592fimd_get_alpha_pix_extlow(Exynos4210fimdWindow *w, uint32_t pix_a)
593{
594 return EXTEND_LOWER_HALFBYTE(pix_a);
595}
596
597static uint32_t
598fimd_get_alpha_pix_exthigh(Exynos4210fimdWindow *w, uint32_t pix_a)
599{
600 return EXTEND_UPPER_HALFBYTE(pix_a);
601}
602
603static uint32_t fimd_get_alpha_mult(Exynos4210fimdWindow *w, uint32_t pix_a)
604{
605 return fimd_mult_each_byte(pix_a, w->alpha_val[0]);
606}
607
608static uint32_t fimd_get_alpha_mult_ext(Exynos4210fimdWindow *w, uint32_t pix_a)
609{
610 return fimd_mult_each_byte(EXTEND_LOWER_HALFBYTE(pix_a),
611 EXTEND_UPPER_HALFBYTE(w->alpha_val[0]));
612}
613
614static uint32_t fimd_get_alpha_aen(Exynos4210fimdWindow *w, uint32_t pix_a)
615{
616 return w->alpha_val[pix_a];
617}
618
619static uint32_t fimd_get_alpha_aen_ext(Exynos4210fimdWindow *w, uint32_t pix_a)
620{
621 return EXTEND_UPPER_HALFBYTE(w->alpha_val[pix_a]);
622}
623
624static uint32_t fimd_get_alpha_sel(Exynos4210fimdWindow *w, uint32_t pix_a)
625{
626 return w->alpha_val[(w->wincon & FIMD_WINCON_ALPHA_SEL) ? 1 : 0];
627}
628
629static uint32_t fimd_get_alpha_sel_ext(Exynos4210fimdWindow *w, uint32_t pix_a)
630{
631 return EXTEND_UPPER_HALFBYTE(w->alpha_val[(w->wincon &
632 FIMD_WINCON_ALPHA_SEL) ? 1 : 0]);
633}
634
635/* Updates currently active alpha value get function for specified window */
636static void fimd_update_get_alpha(Exynos4210fimdState *s, int win)
637{
638 Exynos4210fimdWindow *w = &s->window[win];
639 const bool alpha_is_8bit = s->blendcon & FIMD_ALPHA_8BIT;
640
641 if (w->wincon & FIMD_WINCON_BLD_PIX) {
642 if ((w->wincon & FIMD_WINCON_ALPHA_SEL) && WIN_BPP_MODE_WITH_ALPHA(w)) {
643 /* In this case, alpha component contains meaningful value */
644 if (w->wincon & FIMD_WINCON_ALPHA_MUL) {
645 w->get_alpha = alpha_is_8bit ?
646 fimd_get_alpha_mult : fimd_get_alpha_mult_ext;
647 } else {
648 w->get_alpha = alpha_is_8bit ?
649 fimd_get_alpha_pix : fimd_get_alpha_pix_extlow;
650 }
651 } else {
652 if (IS_PALETTIZED_MODE(w) &&
653 PAL_MODE_WITH_ALPHA(exynos4210_fimd_palette_format(s, win))) {
654 /* Alpha component has 8-bit numeric value */
655 w->get_alpha = alpha_is_8bit ?
656 fimd_get_alpha_pix : fimd_get_alpha_pix_exthigh;
657 } else {
658 /* Alpha has only two possible values (AEN) */
659 w->get_alpha = alpha_is_8bit ?
660 fimd_get_alpha_aen : fimd_get_alpha_aen_ext;
661 }
662 }
663 } else {
664 w->get_alpha = alpha_is_8bit ? fimd_get_alpha_sel :
665 fimd_get_alpha_sel_ext;
666 }
667}
668
669/* Blends current window's (w) pixel (foreground pixel *ret) with background
670 * window (w_blend) pixel p_bg according to formula:
671 * NEW_COLOR = a_coef x FG_PIXEL_COLOR + b_coef x BG_PIXEL_COLOR
672 * NEW_ALPHA = p_coef x FG_ALPHA + q_coef x BG_ALPHA
673 */
674static void
675exynos4210_fimd_blend_pixel(Exynos4210fimdWindow *w, rgba p_bg, rgba *ret)
676{
677 rgba p_fg = *ret;
678 uint32_t bg_color = ((p_bg.r & 0xFF) << 16) | ((p_bg.g & 0xFF) << 8) |
679 (p_bg.b & 0xFF);
680 uint32_t fg_color = ((p_fg.r & 0xFF) << 16) | ((p_fg.g & 0xFF) << 8) |
681 (p_fg.b & 0xFF);
682 uint32_t alpha_fg = p_fg.a;
683 int i;
684 /* It is possible that blending equation parameters a and b do not
685 * depend on window BLENEQ register. Account for this with first_coef */
686 enum { A_COEF = 0, B_COEF = 1, P_COEF = 2, Q_COEF = 3, COEF_NUM = 4};
687 uint32_t first_coef = A_COEF;
688 uint32_t blend_param[COEF_NUM];
689
690 if (w->keycon[0] & FIMD_WKEYCON0_KEYEN) {
691 uint32_t colorkey = (w->keycon[1] &
692 ~(w->keycon[0] & FIMD_WKEYCON0_COMPKEY)) & FIMD_WKEYCON0_COMPKEY;
693
694 if ((w->keycon[0] & FIMD_WKEYCON0_DIRCON) &&
695 (bg_color & ~(w->keycon[0] & FIMD_WKEYCON0_COMPKEY)) == colorkey) {
696 /* Foreground pixel is displayed */
697 if (w->keycon[0] & FIMD_WKEYCON0_KEYBLEN) {
698 alpha_fg = w->keyalpha;
699 blend_param[A_COEF] = alpha_fg;
700 blend_param[B_COEF] = FIMD_1_MINUS_COLOR(alpha_fg);
701 } else {
702 alpha_fg = 0;
703 blend_param[A_COEF] = 0xFFFFFF;
704 blend_param[B_COEF] = 0x0;
705 }
706 first_coef = P_COEF;
707 } else if ((w->keycon[0] & FIMD_WKEYCON0_DIRCON) == 0 &&
708 (fg_color & ~(w->keycon[0] & FIMD_WKEYCON0_COMPKEY)) == colorkey) {
709 /* Background pixel is displayed */
710 if (w->keycon[0] & FIMD_WKEYCON0_KEYBLEN) {
711 alpha_fg = w->keyalpha;
712 blend_param[A_COEF] = alpha_fg;
713 blend_param[B_COEF] = FIMD_1_MINUS_COLOR(alpha_fg);
714 } else {
715 alpha_fg = 0;
716 blend_param[A_COEF] = 0x0;
717 blend_param[B_COEF] = 0xFFFFFF;
718 }
719 first_coef = P_COEF;
720 }
721 }
722
723 for (i = first_coef; i < COEF_NUM; i++) {
724 switch ((w->blendeq >> i * 6) & FIMD_BLENDEQ_COEF_MASK) {
725 case 0:
726 blend_param[i] = 0;
727 break;
728 case 1:
729 blend_param[i] = 0xFFFFFF;
730 break;
731 case 2:
732 blend_param[i] = alpha_fg;
733 break;
734 case 3:
735 blend_param[i] = FIMD_1_MINUS_COLOR(alpha_fg);
736 break;
737 case 4:
738 blend_param[i] = p_bg.a;
739 break;
740 case 5:
741 blend_param[i] = FIMD_1_MINUS_COLOR(p_bg.a);
742 break;
743 case 6:
744 blend_param[i] = w->alpha_val[0];
745 break;
746 case 10:
747 blend_param[i] = fg_color;
748 break;
749 case 11:
750 blend_param[i] = FIMD_1_MINUS_COLOR(fg_color);
751 break;
752 case 12:
753 blend_param[i] = bg_color;
754 break;
755 case 13:
756 blend_param[i] = FIMD_1_MINUS_COLOR(bg_color);
757 break;
758 default:
759 hw_error("exynos4210.fimd: blend equation coef illegal value\n");
760 break;
761 }
762 }
763
764 fg_color = fimd_mult_and_sum_each_byte(bg_color, blend_param[B_COEF],
765 fg_color, blend_param[A_COEF]);
766 ret->b = fg_color & 0xFF;
767 fg_color >>= 8;
768 ret->g = fg_color & 0xFF;
769 fg_color >>= 8;
770 ret->r = fg_color & 0xFF;
771 ret->a = fimd_mult_and_sum_each_byte(alpha_fg, blend_param[P_COEF],
772 p_bg.a, blend_param[Q_COEF]);
773}
774
775/* These routines read data from video frame buffer in system RAM, convert
776 * this data to display controller internal representation, if necessary,
777 * perform pixel blending with data, currently presented in internal buffer.
778 * Result is stored in display controller internal frame buffer. */
779
780/* Draw line with index in palette table in RAM frame buffer data */
781#define DEF_DRAW_LINE_PALETTE(N) \
782static void glue(draw_line_palette_, N)(Exynos4210fimdWindow *w, uint8_t *src, \
783 uint8_t *dst, bool blend) \
784{ \
785 int width = w->rightbot_x - w->lefttop_x + 1; \
786 uint8_t *ifb = dst; \
787 uint8_t swap = (w->wincon & FIMD_WINCON_SWAP) >> FIMD_WINCON_SWAP_SHIFT; \
788 uint64_t data; \
789 rgba p, p_old; \
790 int i; \
791 do { \
fc97bb5b 792 memcpy(&data, src, sizeof(data)); \
30628cb1
MI		 793 src += 8; \
794 fimd_swap_data(swap, &data); \
795 for (i = (64 / (N) - 1); i >= 0; i--) { \
796 w->pixel_to_rgb(w->palette[(data >> ((N) * i)) & \
797 ((1ULL << (N)) - 1)], &p); \
798 p.a = w->get_alpha(w, p.a); \
799 if (blend) { \
800 ifb += get_pixel_ifb(ifb, &p_old); \
801 exynos4210_fimd_blend_pixel(w, p_old, &p); \
802 } \
803 dst += put_pixel_ifb(p, dst); \
804 } \
805 width -= (64 / (N)); \
806 } while (width > 0); \
807}
808
809/* Draw line with direct color value in RAM frame buffer data */
810#define DEF_DRAW_LINE_NOPALETTE(N) \
811static void glue(draw_line_, N)(Exynos4210fimdWindow *w, uint8_t *src, \
812 uint8_t *dst, bool blend) \
813{ \
814 int width = w->rightbot_x - w->lefttop_x + 1; \
815 uint8_t *ifb = dst; \
816 uint8_t swap = (w->wincon & FIMD_WINCON_SWAP) >> FIMD_WINCON_SWAP_SHIFT; \
817 uint64_t data; \
818 rgba p, p_old; \
819 int i; \
820 do { \
fc97bb5b 821 memcpy(&data, src, sizeof(data)); \
30628cb1
MI		 822 src += 8; \
823 fimd_swap_data(swap, &data); \
824 for (i = (64 / (N) - 1); i >= 0; i--) { \
825 w->pixel_to_rgb((data >> ((N) * i)) & ((1ULL << (N)) - 1), &p); \
826 p.a = w->get_alpha(w, p.a); \
827 if (blend) { \
828 ifb += get_pixel_ifb(ifb, &p_old); \
829 exynos4210_fimd_blend_pixel(w, p_old, &p); \
830 } \
831 dst += put_pixel_ifb(p, dst); \
832 } \
833 width -= (64 / (N)); \
834 } while (width > 0); \
835}
836
837DEF_DRAW_LINE_PALETTE(1)
838DEF_DRAW_LINE_PALETTE(2)
839DEF_DRAW_LINE_PALETTE(4)
840DEF_DRAW_LINE_PALETTE(8)
841DEF_DRAW_LINE_NOPALETTE(8) /* 8bpp mode has palette and non-palette versions */
842DEF_DRAW_LINE_NOPALETTE(16)
843DEF_DRAW_LINE_NOPALETTE(32)
844
845/* Special draw line routine for window color map case */
846static void draw_line_mapcolor(Exynos4210fimdWindow *w, uint8_t *src,
847 uint8_t *dst, bool blend)
848{
849 rgba p, p_old;
850 uint8_t *ifb = dst;
851 int width = w->rightbot_x - w->lefttop_x + 1;
852 uint32_t map_color = w->winmap & FIMD_WINMAP_COLOR_MASK;
853
854 do {
855 pixel_888_to_rgb(map_color, &p);
856 p.a = w->get_alpha(w, p.a);
857 if (blend) {
858 ifb += get_pixel_ifb(ifb, &p_old);
859 exynos4210_fimd_blend_pixel(w, p_old, &p);
860 }
861 dst += put_pixel_ifb(p, dst);
862 } while (--width);
863}
864
865/* Write RGB to QEMU's GraphicConsole framebuffer */
866
867static int put_to_qemufb_pixel8(const rgba p, uint8_t *d)
868{
869 uint32_t pixel = rgb_to_pixel8(p.r, p.g, p.b);
870 *(uint8_t *)d = pixel;
871 return 1;
872}
873
874static int put_to_qemufb_pixel15(const rgba p, uint8_t *d)
875{
876 uint32_t pixel = rgb_to_pixel15(p.r, p.g, p.b);
877 *(uint16_t *)d = pixel;
878 return 2;
879}
880
881static int put_to_qemufb_pixel16(const rgba p, uint8_t *d)
882{
883 uint32_t pixel = rgb_to_pixel16(p.r, p.g, p.b);
884 *(uint16_t *)d = pixel;
885 return 2;
886}
887
888static int put_to_qemufb_pixel24(const rgba p, uint8_t *d)
889{
890 uint32_t pixel = rgb_to_pixel24(p.r, p.g, p.b);
891 *(uint8_t *)d++ = (pixel >> 0) & 0xFF;
892 *(uint8_t *)d++ = (pixel >> 8) & 0xFF;
893 *(uint8_t *)d++ = (pixel >> 16) & 0xFF;
894 return 3;
895}
896
897static int put_to_qemufb_pixel32(const rgba p, uint8_t *d)
898{
899 uint32_t pixel = rgb_to_pixel24(p.r, p.g, p.b);
900 *(uint32_t *)d = pixel;
901 return 4;
902}
903
904/* Routine to copy pixel from internal buffer to QEMU buffer */
905static int (*put_pixel_toqemu)(const rgba p, uint8_t *pixel);
906static inline void fimd_update_putpix_qemu(int bpp)
907{
908 switch (bpp) {
909 case 8:
910 put_pixel_toqemu = put_to_qemufb_pixel8;
911 break;
912 case 15:
913 put_pixel_toqemu = put_to_qemufb_pixel15;
914 break;
915 case 16:
916 put_pixel_toqemu = put_to_qemufb_pixel16;
917 break;
918 case 24:
919 put_pixel_toqemu = put_to_qemufb_pixel24;
920 break;
921 case 32:
922 put_pixel_toqemu = put_to_qemufb_pixel32;
923 break;
924 default:
925 hw_error("exynos4210.fimd: unsupported BPP (%d)", bpp);
926 break;
927 }
928}
929
930/* Routine to copy a line from internal frame buffer to QEMU display */
931static void fimd_copy_line_toqemu(int width, uint8_t *src, uint8_t *dst)
932{
933 rgba p;
934
935 do {
936 src += get_pixel_ifb(src, &p);
937 dst += put_pixel_toqemu(p, dst);
938 } while (--width);
939}
940
941/* Parse BPPMODE_F = WINCON1[5:2] bits */
942static void exynos4210_fimd_update_win_bppmode(Exynos4210fimdState *s, int win)
943{
944 Exynos4210fimdWindow *w = &s->window[win];
945
946 if (w->winmap & FIMD_WINMAP_EN) {
947 w->draw_line = draw_line_mapcolor;
948 return;
949 }
950
951 switch (WIN_BPP_MODE(w)) {
952 case 0:
953 w->draw_line = draw_line_palette_1;
954 w->pixel_to_rgb =
955 palette_data_format[exynos4210_fimd_palette_format(s, win)];
956 break;
957 case 1:
958 w->draw_line = draw_line_palette_2;
959 w->pixel_to_rgb =
960 palette_data_format[exynos4210_fimd_palette_format(s, win)];
961 break;
962 case 2:
963 w->draw_line = draw_line_palette_4;
964 w->pixel_to_rgb =
965 palette_data_format[exynos4210_fimd_palette_format(s, win)];
966 break;
967 case 3:
968 w->draw_line = draw_line_palette_8;
969 w->pixel_to_rgb =
970 palette_data_format[exynos4210_fimd_palette_format(s, win)];
971 break;
972 case 4:
973 w->draw_line = draw_line_8;
974 w->pixel_to_rgb = pixel_a232_to_rgb;
975 break;
976 case 5:
977 w->draw_line = draw_line_16;
978 w->pixel_to_rgb = pixel_565_to_rgb;
979 break;
980 case 6:
981 w->draw_line = draw_line_16;
982 w->pixel_to_rgb = pixel_a555_to_rgb;
983 break;
984 case 7:
985 w->draw_line = draw_line_16;
986 w->pixel_to_rgb = pixel_1555_to_rgb;
987 break;
988 case 8:
989 w->draw_line = draw_line_32;
990 w->pixel_to_rgb = pixel_666_to_rgb;
991 break;
992 case 9:
993 w->draw_line = draw_line_32;
994 w->pixel_to_rgb = pixel_a665_to_rgb;
995 break;
996 case 10:
997 w->draw_line = draw_line_32;
998 w->pixel_to_rgb = pixel_a666_to_rgb;
999 break;
1000 case 11:
1001 w->draw_line = draw_line_32;
1002 w->pixel_to_rgb = pixel_888_to_rgb;
1003 break;
1004 case 12:
1005 w->draw_line = draw_line_32;
1006 w->pixel_to_rgb = pixel_a887_to_rgb;
1007 break;
1008 case 13:
1009 w->draw_line = draw_line_32;
1010 if ((w->wincon & FIMD_WINCON_BLD_PIX) && (w->wincon &
1011 FIMD_WINCON_ALPHA_SEL)) {
1012 w->pixel_to_rgb = pixel_8888_to_rgb;
1013 } else {
1014 w->pixel_to_rgb = pixel_a888_to_rgb;
1015 }
1016 break;
1017 case 14:
1018 w->draw_line = draw_line_16;
1019 if ((w->wincon & FIMD_WINCON_BLD_PIX) && (w->wincon &
1020 FIMD_WINCON_ALPHA_SEL)) {
1021 w->pixel_to_rgb = pixel_4444_to_rgb;
1022 } else {
1023 w->pixel_to_rgb = pixel_a444_to_rgb;
1024 }
1025 break;
1026 case 15:
1027 w->draw_line = draw_line_16;
1028 w->pixel_to_rgb = pixel_555_to_rgb;
1029 break;
1030 }
1031}
1032
1033#if EXYNOS4210_FIMD_MODE_TRACE > 0
1034static const char *exynos4210_fimd_get_bppmode(int mode_code)
1035{
1036 switch (mode_code) {
1037 case 0:
1038 return "1 bpp";
1039 case 1:
1040 return "2 bpp";
1041 case 2:
1042 return "4 bpp";
1043 case 3:
1044 return "8 bpp (palettized)";
1045 case 4:
1046 return "8 bpp (non-palettized, A: 1-R:2-G:3-B:2)";
1047 case 5:
1048 return "16 bpp (non-palettized, R:5-G:6-B:5)";
1049 case 6:
1050 return "16 bpp (non-palettized, A:1-R:5-G:5-B:5)";
1051 case 7:
1052 return "16 bpp (non-palettized, I :1-R:5-G:5-B:5)";
1053 case 8:
1054 return "Unpacked 18 bpp (non-palettized, R:6-G:6-B:6)";
1055 case 9:
1056 return "Unpacked 18bpp (non-palettized,A:1-R:6-G:6-B:5)";
1057 case 10:
1058 return "Unpacked 19bpp (non-palettized,A:1-R:6-G:6-B:6)";
1059 case 11:
1060 return "Unpacked 24 bpp (non-palettized R:8-G:8-B:8)";
1061 case 12:
1062 return "Unpacked 24 bpp (non-palettized A:1-R:8-G:8-B:7)";
1063 case 13:
1064 return "Unpacked 25 bpp (non-palettized A:1-R:8-G:8-B:8)";
1065 case 14:
1066 return "Unpacked 13 bpp (non-palettized A:1-R:4-G:4-B:4)";
1067 case 15:
1068 return "Unpacked 15 bpp (non-palettized R:5-G:5-B:5)";
1069 default:
1070 return "Non-existing bpp mode";
1071 }
1072}
1073
1074static inline void exynos4210_fimd_trace_bppmode(Exynos4210fimdState *s,
1075 int win_num, uint32_t val)
1076{
1077 Exynos4210fimdWindow *w = &s->window[win_num];
1078
1079 if (w->winmap & FIMD_WINMAP_EN) {
1080 printf("QEMU FIMD: Window %d is mapped with MAPCOLOR=0x%x\n",
1081 win_num, w->winmap & 0xFFFFFF);
1082 return;
1083 }
1084
1085 if ((val != 0xFFFFFFFF) && ((w->wincon >> 2) & 0xF) == ((val >> 2) & 0xF)) {
1086 return;
1087 }
1088 printf("QEMU FIMD: Window %d BPP mode set to %s\n", win_num,
1089 exynos4210_fimd_get_bppmode((val >> 2) & 0xF));
1090}
1091#else
1092static inline void exynos4210_fimd_trace_bppmode(Exynos4210fimdState *s,
1093 int win_num, uint32_t val)
1094{
1095
1096}
1097#endif
1098
1099static inline int fimd_get_buffer_id(Exynos4210fimdWindow *w)
1100{
1101 switch (w->wincon & FIMD_WINCON_BUFSTATUS) {
1102 case FIMD_WINCON_BUF0_STAT:
1103 return 0;
1104 case FIMD_WINCON_BUF1_STAT:
1105 return 1;
1106 case FIMD_WINCON_BUF2_STAT:
1107 return 2;
1108 default:
1109 DPRINT_ERROR("Non-existent buffer index\n");
1110 return 0;
1111 }
1112}
1113
74259ae5
PB		 1114static void exynos4210_fimd_invalidate(void *opaque)
1115{
1116 Exynos4210fimdState *s = (Exynos4210fimdState *)opaque;
1117 s->invalidate = true;
1118}
1119
30628cb1
MI		 1120/* Updates specified window's MemorySection based on values of WINCON,
1121 * VIDOSDA, VIDOSDB, VIDWADDx and SHADOWCON registers */
1122static void fimd_update_memory_section(Exynos4210fimdState *s, unsigned win)
1123{
f27321aa 1124 SysBusDevice *sbd = SYS_BUS_DEVICE(s);
30628cb1 1125 Exynos4210fimdWindow *w = &s->window[win];
a8170e5e 1126 hwaddr fb_start_addr, fb_mapped_len;
30628cb1
MI		 1127
1128 if (!s->enabled || !(w->wincon & FIMD_WINCON_ENWIN) ||
1129 FIMD_WINDOW_PROTECTED(s->shadowcon, win)) {
1130 return;
1131 }
1132
1133 if (w->host_fb_addr) {
1134 cpu_physical_memory_unmap(w->host_fb_addr, w->fb_len, 0, 0);
1135 w->host_fb_addr = NULL;
1136 w->fb_len = 0;
1137 }
1138
1139 fb_start_addr = w->buf_start[fimd_get_buffer_id(w)];
1140 /* Total number of bytes of virtual screen used by current window */
1141 w->fb_len = fb_mapped_len = (w->virtpage_width + w->virtpage_offsize) *
1142 (w->rightbot_y - w->lefttop_y + 1);
dfde4e6e
PB		 1143
1144 /* TODO: add .exit and unref the region there. Not needed yet since sysbus
1145 * does not support hot-unplug.
1146 */
74259ae5
PB		 1147 if (w->mem_section.mr) {
1148 memory_region_set_log(w->mem_section.mr, false, DIRTY_MEMORY_VGA);
1149 memory_region_unref(w->mem_section.mr);
1150 }
1151
f27321aa
AF		 1152 w->mem_section = memory_region_find(sysbus_address_space(sbd),
1153 fb_start_addr, w->fb_len);
30628cb1
MI		 1154 assert(w->mem_section.mr);
1155 assert(w->mem_section.offset_within_address_space == fb_start_addr);
1156 DPRINT_TRACE("Window %u framebuffer changed: address=0x%08x, len=0x%x\n",
1157 win, fb_start_addr, w->fb_len);
1158
052e87b0 1159 if (int128_get64(w->mem_section.size) != w->fb_len ||
30628cb1
MI		 1160 !memory_region_is_ram(w->mem_section.mr)) {
1161 DPRINT_ERROR("Failed to find window %u framebuffer region\n", win);
1162 goto error_return;
1163 }
1164
1165 w->host_fb_addr = cpu_physical_memory_map(fb_start_addr, &fb_mapped_len, 0);
1166 if (!w->host_fb_addr) {
1167 DPRINT_ERROR("Failed to map window %u framebuffer\n", win);
1168 goto error_return;
1169 }
1170
1171 if (fb_mapped_len != w->fb_len) {
1172 DPRINT_ERROR("Window %u mapped framebuffer length is less then "
1173 "expected\n", win);
1174 cpu_physical_memory_unmap(w->host_fb_addr, fb_mapped_len, 0, 0);
1175 goto error_return;
1176 }
74259ae5
PB		 1177 memory_region_set_log(w->mem_section.mr, true, DIRTY_MEMORY_VGA);
1178 exynos4210_fimd_invalidate(s);
30628cb1
MI		 1179 return;
1180
1181error_return:
dfde4e6e 1182 memory_region_unref(w->mem_section.mr);
30628cb1 1183 w->mem_section.mr = NULL;
052e87b0 1184 w->mem_section.size = int128_zero();
30628cb1
MI		 1185 w->host_fb_addr = NULL;
1186 w->fb_len = 0;
1187}
1188
1189static void exynos4210_fimd_enable(Exynos4210fimdState *s, bool enabled)
1190{
1191 if (enabled && !s->enabled) {
1192 unsigned w;
1193 s->enabled = true;
1194 for (w = 0; w < NUM_OF_WINDOWS; w++) {
1195 fimd_update_memory_section(s, w);
1196 }
1197 }
1198 s->enabled = enabled;
1199 DPRINT_TRACE("display controller %s\n", enabled ? "enabled" : "disabled");
1200}
1201
1202static inline uint32_t unpack_upper_4(uint32_t x)
1203{
1204 return ((x & 0xF00) << 12) | ((x & 0xF0) << 8) | ((x & 0xF) << 4);
1205}
1206
1207static inline uint32_t pack_upper_4(uint32_t x)
1208{
1209 return (((x & 0xF00000) >> 12) | ((x & 0xF000) >> 8) |
1210 ((x & 0xF0) >> 4)) & 0xFFF;
1211}
1212
1213static void exynos4210_fimd_update_irq(Exynos4210fimdState *s)
1214{
1215 if (!(s->vidintcon[0] & FIMD_VIDINT_INTEN)) {
1216 qemu_irq_lower(s->irq[0]);
1217 qemu_irq_lower(s->irq[1]);
1218 qemu_irq_lower(s->irq[2]);
1219 return;
1220 }
1221 if ((s->vidintcon[0] & FIMD_VIDINT_INTFIFOEN) &&
1222 (s->vidintcon[1] & FIMD_VIDINT_INTFIFOPEND)) {
1223 qemu_irq_raise(s->irq[0]);
1224 } else {
1225 qemu_irq_lower(s->irq[0]);
1226 }
1227 if ((s->vidintcon[0] & FIMD_VIDINT_INTFRMEN) &&
1228 (s->vidintcon[1] & FIMD_VIDINT_INTFRMPEND)) {
1229 qemu_irq_raise(s->irq[1]);
1230 } else {
1231 qemu_irq_lower(s->irq[1]);
1232 }
1233 if ((s->vidintcon[0] & FIMD_VIDINT_I80IFDONE) &&
1234 (s->vidintcon[1] & FIMD_VIDINT_INTI80PEND)) {
1235 qemu_irq_raise(s->irq[2]);
1236 } else {
1237 qemu_irq_lower(s->irq[2]);
1238 }
1239}
1240
30628cb1
MI		 1241static void exynos4210_update_resolution(Exynos4210fimdState *s)
1242{
c78f7137
GH		 1243 DisplaySurface *surface = qemu_console_surface(s->console);
1244
30628cb1
MI		 1245 /* LCD resolution is stored in VIDEO TIME CONTROL REGISTER 2 */
1246 uint32_t width = ((s->vidtcon[2] >> FIMD_VIDTCON2_HOR_SHIFT) &
1247 FIMD_VIDTCON2_SIZE_MASK) + 1;
1248 uint32_t height = ((s->vidtcon[2] >> FIMD_VIDTCON2_VER_SHIFT) &
1249 FIMD_VIDTCON2_SIZE_MASK) + 1;
1250
c78f7137
GH		 1251 if (s->ifb == NULL || surface_width(surface) != width ||
1252 surface_height(surface) != height) {
30628cb1 1253 DPRINT_L1("Resolution changed from %ux%u to %ux%u\n",
c78f7137 1254 surface_width(surface), surface_height(surface), width, height);
30628cb1
MI		 1255 qemu_console_resize(s->console, width, height);
1256 s->ifb = g_realloc(s->ifb, width * height * RGBA_SIZE + 1);
1257 memset(s->ifb, 0, width * height * RGBA_SIZE + 1);
1258 exynos4210_fimd_invalidate(s);
1259 }
1260}
1261
1262static void exynos4210_fimd_update(void *opaque)
1263{
1264 Exynos4210fimdState *s = (Exynos4210fimdState *)opaque;
522fccbe 1265 DisplaySurface *surface;
30628cb1 1266 Exynos4210fimdWindow *w;
553bcce5 1267 DirtyBitmapSnapshot *snap;
30628cb1 1268 int i, line;
a8170e5e 1269 hwaddr fb_line_addr, inc_size;
30628cb1
MI		 1270 int scrn_height;
1271 int first_line = -1, last_line = -1, scrn_width;
1272 bool blend = false;
1273 uint8_t *host_fb_addr;
1274 bool is_dirty = false;
1275 const int global_width = (s->vidtcon[2] & FIMD_VIDTCON2_SIZE_MASK) + 1;
30628cb1 1276
522fccbe
IM		 1277 if (!s || !s->console || !s->enabled ||
1278 surface_bits_per_pixel(qemu_console_surface(s->console)) == 0) {
30628cb1
MI		 1279 return;
1280 }
1281 exynos4210_update_resolution(s);
522fccbe 1282 surface = qemu_console_surface(s->console);
30628cb1
MI		 1283
1284 for (i = 0; i < NUM_OF_WINDOWS; i++) {
1285 w = &s->window[i];
1286 if ((w->wincon & FIMD_WINCON_ENWIN) && w->host_fb_addr) {
1287 scrn_height = w->rightbot_y - w->lefttop_y + 1;
1288 scrn_width = w->virtpage_width;
1289 /* Total width of virtual screen page in bytes */
1290 inc_size = scrn_width + w->virtpage_offsize;
30628cb1
MI		 1291 host_fb_addr = w->host_fb_addr;
1292 fb_line_addr = w->mem_section.offset_within_region;
553bcce5
GH		 1293 snap = memory_region_snapshot_and_clear_dirty(w->mem_section.mr,
1294 fb_line_addr, inc_size * scrn_height, DIRTY_MEMORY_VGA);
30628cb1
MI		 1295
1296 for (line = 0; line < scrn_height; line++) {
553bcce5
GH		 1297 is_dirty = memory_region_snapshot_get_dirty(w->mem_section.mr,
1298 snap, fb_line_addr, scrn_width);
30628cb1
MI		 1299
1300 if (s->invalidate || is_dirty) {
1301 if (first_line == -1) {
1302 first_line = line;
1303 }
1304 last_line = line;
1305 w->draw_line(w, host_fb_addr, s->ifb +
1306 w->lefttop_x * RGBA_SIZE + (w->lefttop_y + line) *
1307 global_width * RGBA_SIZE, blend);
1308 }
1309 host_fb_addr += inc_size;
1310 fb_line_addr += inc_size;
1311 is_dirty = false;
1312 }
553bcce5 1313 g_free(snap);
30628cb1
MI		 1314 blend = true;
1315 }
1316 }
1317
1318 /* Copy resulting image to QEMU_CONSOLE. */
1319 if (first_line >= 0) {
1320 uint8_t *d;
1321 int bpp;
1322
c78f7137 1323 bpp = surface_bits_per_pixel(surface);
30628cb1
MI		 1324 fimd_update_putpix_qemu(bpp);
1325 bpp = (bpp + 1) >> 3;
c78f7137 1326 d = surface_data(surface);
30628cb1
MI		 1327 for (line = first_line; line <= last_line; line++) {
1328 fimd_copy_line_toqemu(global_width, s->ifb + global_width * line *
1329 RGBA_SIZE, d + global_width * line * bpp);
1330 }
91155f8b 1331 dpy_gfx_update_full(s->console);
30628cb1
MI		 1332 }
1333 s->invalidate = false;
1334 s->vidintcon[1] |= FIMD_VIDINT_INTFRMPEND;
1335 if ((s->vidcon[0] & FIMD_VIDCON0_ENVID_F) == 0) {
1336 exynos4210_fimd_enable(s, false);
1337 }
1338 exynos4210_fimd_update_irq(s);
1339}
1340
1341static void exynos4210_fimd_reset(DeviceState *d)
1342{
f27321aa 1343 Exynos4210fimdState *s = EXYNOS4210_FIMD(d);
30628cb1
MI		 1344 unsigned w;
1345
1346 DPRINT_TRACE("Display controller reset\n");
1347 /* Set all display controller registers to 0 */
1348 memset(&s->vidcon, 0, (uint8_t *)&s->window - (uint8_t *)&s->vidcon);
1349 for (w = 0; w < NUM_OF_WINDOWS; w++) {
1350 memset(&s->window[w], 0, sizeof(Exynos4210fimdWindow));
1351 s->window[w].blendeq = 0xC2;
1352 exynos4210_fimd_update_win_bppmode(s, w);
1353 exynos4210_fimd_trace_bppmode(s, w, 0xFFFFFFFF);
1354 fimd_update_get_alpha(s, w);
1355 }
1356
ef1e1e07 1357 g_free(s->ifb);
30628cb1
MI		 1358 s->ifb = NULL;
1359
1360 exynos4210_fimd_invalidate(s);
1361 exynos4210_fimd_enable(s, false);
1362 /* Some registers have non-zero initial values */
1363 s->winchmap = 0x7D517D51;
1364 s->colorgaincon = 0x10040100;
1365 s->huecoef_cr[0] = s->huecoef_cr[3] = 0x01000100;
1366 s->huecoef_cb[0] = s->huecoef_cb[3] = 0x01000100;
1367 s->hueoffset = 0x01800080;
1368}
1369
a8170e5e 1370static void exynos4210_fimd_write(void *opaque, hwaddr offset,
30628cb1
MI		 1371 uint64_t val, unsigned size)
1372{
1373 Exynos4210fimdState *s = (Exynos4210fimdState *)opaque;
1374 unsigned w, i;
1375 uint32_t old_value;
1376
1377 DPRINT_L2("write offset 0x%08x, value=%llu(0x%08llx)\n", offset,
1378 (long long unsigned int)val, (long long unsigned int)val);
1379
1380 switch (offset) {
1381 case FIMD_VIDCON0:
1382 if ((val & FIMD_VIDCON0_ENVID_MASK) == FIMD_VIDCON0_ENVID_MASK) {
1383 exynos4210_fimd_enable(s, true);
1384 } else {
1385 if ((val & FIMD_VIDCON0_ENVID) == 0) {
1386 exynos4210_fimd_enable(s, false);
1387 }
1388 }
1389 s->vidcon[0] = val;
1390 break;
1391 case FIMD_VIDCON1:
1392 /* Leave read-only bits as is */
1393 val = (val & (~FIMD_VIDCON1_ROMASK)) |
1394 (s->vidcon[1] & FIMD_VIDCON1_ROMASK);
1395 s->vidcon[1] = val;
1396 break;
1397 case FIMD_VIDCON2 ... FIMD_VIDCON3:
1398 s->vidcon[(offset) >> 2] = val;
1399 break;
1400 case FIMD_VIDTCON_START ... FIMD_VIDTCON_END:
1401 s->vidtcon[(offset - FIMD_VIDTCON_START) >> 2] = val;
1402 break;
1403 case FIMD_WINCON_START ... FIMD_WINCON_END:
1404 w = (offset - FIMD_WINCON_START) >> 2;
1405 /* Window's current buffer ID */
1406 i = fimd_get_buffer_id(&s->window[w]);
1407 old_value = s->window[w].wincon;
1408 val = (val & ~FIMD_WINCON_ROMASK) |
1409 (s->window[w].wincon & FIMD_WINCON_ROMASK);
1410 if (w == 0) {
1411 /* Window 0 wincon ALPHA_MUL bit must always be 0 */
1412 val &= ~FIMD_WINCON_ALPHA_MUL;
1413 }
1414 exynos4210_fimd_trace_bppmode(s, w, val);
1415 switch (val & FIMD_WINCON_BUFSELECT) {
1416 case FIMD_WINCON_BUF0_SEL:
1417 val &= ~FIMD_WINCON_BUFSTATUS;
1418 break;
1419 case FIMD_WINCON_BUF1_SEL:
1420 val = (val & ~FIMD_WINCON_BUFSTAT_H) | FIMD_WINCON_BUFSTAT_L;
1421 break;
1422 case FIMD_WINCON_BUF2_SEL:
1423 if (val & FIMD_WINCON_BUFMODE) {
1424 val = (val & ~FIMD_WINCON_BUFSTAT_L) | FIMD_WINCON_BUFSTAT_H;
1425 }
1426 break;
1427 default:
1428 break;
1429 }
1430 s->window[w].wincon = val;
1431 exynos4210_fimd_update_win_bppmode(s, w);
1432 fimd_update_get_alpha(s, w);
1433 if ((i != fimd_get_buffer_id(&s->window[w])) ||
1434 (!(old_value & FIMD_WINCON_ENWIN) && (s->window[w].wincon &
1435 FIMD_WINCON_ENWIN))) {
1436 fimd_update_memory_section(s, w);
1437 }
1438 break;
1439 case FIMD_SHADOWCON:
1440 old_value = s->shadowcon;
1441 s->shadowcon = val;
1442 for (w = 0; w < NUM_OF_WINDOWS; w++) {
1443 if (FIMD_WINDOW_PROTECTED(old_value, w) &&
1444 !FIMD_WINDOW_PROTECTED(s->shadowcon, w)) {
1445 fimd_update_memory_section(s, w);
1446 }
1447 }
1448 break;
1449 case FIMD_WINCHMAP:
1450 s->winchmap = val;
1451 break;
1452 case FIMD_VIDOSD_START ... FIMD_VIDOSD_END:
1453 w = (offset - FIMD_VIDOSD_START) >> 4;
1454 i = ((offset - FIMD_VIDOSD_START) & 0xF) >> 2;
1455 switch (i) {
1456 case 0:
1457 old_value = s->window[w].lefttop_y;
1458 s->window[w].lefttop_x = (val >> FIMD_VIDOSD_HOR_SHIFT) &
1459 FIMD_VIDOSD_COORD_MASK;
1460 s->window[w].lefttop_y = (val >> FIMD_VIDOSD_VER_SHIFT) &
1461 FIMD_VIDOSD_COORD_MASK;
1462 if (s->window[w].lefttop_y != old_value) {
1463 fimd_update_memory_section(s, w);
1464 }
1465 break;
1466 case 1:
1467 old_value = s->window[w].rightbot_y;
1468 s->window[w].rightbot_x = (val >> FIMD_VIDOSD_HOR_SHIFT) &
1469 FIMD_VIDOSD_COORD_MASK;
1470 s->window[w].rightbot_y = (val >> FIMD_VIDOSD_VER_SHIFT) &
1471 FIMD_VIDOSD_COORD_MASK;
1472 if (s->window[w].rightbot_y != old_value) {
1473 fimd_update_memory_section(s, w);
1474 }
1475 break;
1476 case 2:
1477 if (w == 0) {
1478 s->window[w].osdsize = val;
1479 } else {
1480 s->window[w].alpha_val[0] =
1481 unpack_upper_4((val & FIMD_VIDOSD_ALPHA_AEN0) >>
1482 FIMD_VIDOSD_AEN0_SHIFT) |
1483 (s->window[w].alpha_val[0] & FIMD_VIDALPHA_ALPHA_LOWER);
1484 s->window[w].alpha_val[1] =
1485 unpack_upper_4(val & FIMD_VIDOSD_ALPHA_AEN1) |
1486 (s->window[w].alpha_val[1] & FIMD_VIDALPHA_ALPHA_LOWER);
1487 }
1488 break;
1489 case 3:
1490 if (w != 1 && w != 2) {
1491 DPRINT_ERROR("Bad write offset 0x%08x\n", offset);
1492 return;
1493 }
1494 s->window[w].osdsize = val;
1495 break;
1496 }
1497 break;
1498 case FIMD_VIDWADD0_START ... FIMD_VIDWADD0_END:
1499 w = (offset - FIMD_VIDWADD0_START) >> 3;
1500 i = ((offset - FIMD_VIDWADD0_START) >> 2) & 1;
1501 if (i == fimd_get_buffer_id(&s->window[w]) &&
1502 s->window[w].buf_start[i] != val) {
1503 s->window[w].buf_start[i] = val;
1504 fimd_update_memory_section(s, w);
1505 break;
1506 }
1507 s->window[w].buf_start[i] = val;
1508 break;
1509 case FIMD_VIDWADD1_START ... FIMD_VIDWADD1_END:
1510 w = (offset - FIMD_VIDWADD1_START) >> 3;
1511 i = ((offset - FIMD_VIDWADD1_START) >> 2) & 1;
1512 s->window[w].buf_end[i] = val;
1513 break;
1514 case FIMD_VIDWADD2_START ... FIMD_VIDWADD2_END:
1515 w = (offset - FIMD_VIDWADD2_START) >> 2;
1516 if (((val & FIMD_VIDWADD2_PAGEWIDTH) != s->window[w].virtpage_width) ||
1517 (((val >> FIMD_VIDWADD2_OFFSIZE_SHIFT) & FIMD_VIDWADD2_OFFSIZE) !=
1518 s->window[w].virtpage_offsize)) {
1519 s->window[w].virtpage_width = val & FIMD_VIDWADD2_PAGEWIDTH;
1520 s->window[w].virtpage_offsize =
1521 (val >> FIMD_VIDWADD2_OFFSIZE_SHIFT) & FIMD_VIDWADD2_OFFSIZE;
1522 fimd_update_memory_section(s, w);
1523 }
1524 break;
1525 case FIMD_VIDINTCON0:
1526 s->vidintcon[0] = val;
1527 break;
1528 case FIMD_VIDINTCON1:
1529 s->vidintcon[1] &= ~(val & 7);
1530 exynos4210_fimd_update_irq(s);
1531 break;
1532 case FIMD_WKEYCON_START ... FIMD_WKEYCON_END:
1533 w = ((offset - FIMD_WKEYCON_START) >> 3) + 1;
1534 i = ((offset - FIMD_WKEYCON_START) >> 2) & 1;
1535 s->window[w].keycon[i] = val;
1536 break;
1537 case FIMD_WKEYALPHA_START ... FIMD_WKEYALPHA_END:
1538 w = ((offset - FIMD_WKEYALPHA_START) >> 2) + 1;
1539 s->window[w].keyalpha = val;
1540 break;
1541 case FIMD_DITHMODE:
1542 s->dithmode = val;
1543 break;
1544 case FIMD_WINMAP_START ... FIMD_WINMAP_END:
1545 w = (offset - FIMD_WINMAP_START) >> 2;
1546 old_value = s->window[w].winmap;
1547 s->window[w].winmap = val;
1548 if ((val & FIMD_WINMAP_EN) ^ (old_value & FIMD_WINMAP_EN)) {
1549 exynos4210_fimd_invalidate(s);
1550 exynos4210_fimd_update_win_bppmode(s, w);
1551 exynos4210_fimd_trace_bppmode(s, w, 0xFFFFFFFF);
1552 exynos4210_fimd_update(s);
1553 }
1554 break;
1555 case FIMD_WPALCON_HIGH ... FIMD_WPALCON_LOW:
1556 i = (offset - FIMD_WPALCON_HIGH) >> 2;
1557 s->wpalcon[i] = val;
1558 if (s->wpalcon[1] & FIMD_WPALCON_UPDATEEN) {
1559 for (w = 0; w < NUM_OF_WINDOWS; w++) {
1560 exynos4210_fimd_update_win_bppmode(s, w);
1561 fimd_update_get_alpha(s, w);
1562 }
1563 }
1564 break;
1565 case FIMD_TRIGCON:
1566 val = (val & ~FIMD_TRIGCON_ROMASK) | (s->trigcon & FIMD_TRIGCON_ROMASK);
1567 s->trigcon = val;
1568 break;
1569 case FIMD_I80IFCON_START ... FIMD_I80IFCON_END:
1570 s->i80ifcon[(offset - FIMD_I80IFCON_START) >> 2] = val;
1571 break;
1572 case FIMD_COLORGAINCON:
1573 s->colorgaincon = val;
1574 break;
1575 case FIMD_LDI_CMDCON0 ... FIMD_LDI_CMDCON1:
1576 s->ldi_cmdcon[(offset - FIMD_LDI_CMDCON0) >> 2] = val;
1577 break;
1578 case FIMD_SIFCCON0 ... FIMD_SIFCCON2:
1579 i = (offset - FIMD_SIFCCON0) >> 2;
1580 if (i != 2) {
1581 s->sifccon[i] = val;
1582 }
1583 break;
1584 case FIMD_HUECOEFCR_START ... FIMD_HUECOEFCR_END:
1585 i = (offset - FIMD_HUECOEFCR_START) >> 2;
1586 s->huecoef_cr[i] = val;
1587 break;
1588 case FIMD_HUECOEFCB_START ... FIMD_HUECOEFCB_END:
1589 i = (offset - FIMD_HUECOEFCB_START) >> 2;
1590 s->huecoef_cb[i] = val;
1591 break;
1592 case FIMD_HUEOFFSET:
1593 s->hueoffset = val;
1594 break;
1595 case FIMD_VIDWALPHA_START ... FIMD_VIDWALPHA_END:
1596 w = ((offset - FIMD_VIDWALPHA_START) >> 3);
1597 i = ((offset - FIMD_VIDWALPHA_START) >> 2) & 1;
1598 if (w == 0) {
1599 s->window[w].alpha_val[i] = val;
1600 } else {
1601 s->window[w].alpha_val[i] = (val & FIMD_VIDALPHA_ALPHA_LOWER) |
1602 (s->window[w].alpha_val[i] & FIMD_VIDALPHA_ALPHA_UPPER);
1603 }
1604 break;
1605 case FIMD_BLENDEQ_START ... FIMD_BLENDEQ_END:
1606 s->window[(offset - FIMD_BLENDEQ_START) >> 2].blendeq = val;
1607 break;
1608 case FIMD_BLENDCON:
1609 old_value = s->blendcon;
1610 s->blendcon = val;
1611 if ((s->blendcon & FIMD_ALPHA_8BIT) != (old_value & FIMD_ALPHA_8BIT)) {
1612 for (w = 0; w < NUM_OF_WINDOWS; w++) {
1613 fimd_update_get_alpha(s, w);
1614 }
1615 }
1616 break;
1617 case FIMD_WRTQOSCON_START ... FIMD_WRTQOSCON_END:
1618 s->window[(offset - FIMD_WRTQOSCON_START) >> 2].rtqoscon = val;
1619 break;
1620 case FIMD_I80IFCMD_START ... FIMD_I80IFCMD_END:
1621 s->i80ifcmd[(offset - FIMD_I80IFCMD_START) >> 2] = val;
1622 break;
1623 case FIMD_VIDW0ADD0_B2 ... FIMD_VIDW4ADD0_B2:
1624 if (offset & 0x0004) {
1625 DPRINT_ERROR("bad write offset 0x%08x\n", offset);
1626 break;
1627 }
1628 w = (offset - FIMD_VIDW0ADD0_B2) >> 3;
1629 if (fimd_get_buffer_id(&s->window[w]) == 2 &&
1630 s->window[w].buf_start[2] != val) {
1631 s->window[w].buf_start[2] = val;
1632 fimd_update_memory_section(s, w);
1633 break;
1634 }
1635 s->window[w].buf_start[2] = val;
1636 break;
1637 case FIMD_SHD_ADD0_START ... FIMD_SHD_ADD0_END:
1638 if (offset & 0x0004) {
1639 DPRINT_ERROR("bad write offset 0x%08x\n", offset);
1640 break;
1641 }
1642 s->window[(offset - FIMD_SHD_ADD0_START) >> 3].shadow_buf_start = val;
1643 break;
1644 case FIMD_SHD_ADD1_START ... FIMD_SHD_ADD1_END:
1645 if (offset & 0x0004) {
1646 DPRINT_ERROR("bad write offset 0x%08x\n", offset);
1647 break;
1648 }
1649 s->window[(offset - FIMD_SHD_ADD1_START) >> 3].shadow_buf_end = val;
1650 break;
1651 case FIMD_SHD_ADD2_START ... FIMD_SHD_ADD2_END:
1652 s->window[(offset - FIMD_SHD_ADD2_START) >> 2].shadow_buf_size = val;
1653 break;
1654 case FIMD_PAL_MEM_START ... FIMD_PAL_MEM_END:
1655 w = (offset - FIMD_PAL_MEM_START) >> 10;
1656 i = ((offset - FIMD_PAL_MEM_START) >> 2) & 0xFF;
1657 s->window[w].palette[i] = val;
1658 break;
1659 case FIMD_PALMEM_AL_START ... FIMD_PALMEM_AL_END:
1660 /* Palette memory aliases for windows 0 and 1 */
1661 w = (offset - FIMD_PALMEM_AL_START) >> 10;
1662 i = ((offset - FIMD_PALMEM_AL_START) >> 2) & 0xFF;
1663 s->window[w].palette[i] = val;
1664 break;
1665 default:
1666 DPRINT_ERROR("bad write offset 0x%08x\n", offset);
1667 break;
1668 }
1669}
1670
a8170e5e 1671static uint64_t exynos4210_fimd_read(void *opaque, hwaddr offset,
30628cb1
MI		 1672 unsigned size)
1673{
1674 Exynos4210fimdState *s = (Exynos4210fimdState *)opaque;
1675 int w, i;
1676 uint32_t ret = 0;
1677
1678 DPRINT_L2("read offset 0x%08x\n", offset);
1679
1680 switch (offset) {
1681 case FIMD_VIDCON0 ... FIMD_VIDCON3:
1682 return s->vidcon[(offset - FIMD_VIDCON0) >> 2];
1683 case FIMD_VIDTCON_START ... FIMD_VIDTCON_END:
1684 return s->vidtcon[(offset - FIMD_VIDTCON_START) >> 2];
1685 case FIMD_WINCON_START ... FIMD_WINCON_END:
1686 return s->window[(offset - FIMD_WINCON_START) >> 2].wincon;
1687 case FIMD_SHADOWCON:
1688 return s->shadowcon;
1689 case FIMD_WINCHMAP:
1690 return s->winchmap;
1691 case FIMD_VIDOSD_START ... FIMD_VIDOSD_END:
1692 w = (offset - FIMD_VIDOSD_START) >> 4;
1693 i = ((offset - FIMD_VIDOSD_START) & 0xF) >> 2;
1694 switch (i) {
1695 case 0:
1696 ret = ((s->window[w].lefttop_x & FIMD_VIDOSD_COORD_MASK) <<
1697 FIMD_VIDOSD_HOR_SHIFT) |
1698 (s->window[w].lefttop_y & FIMD_VIDOSD_COORD_MASK);
1699 break;
1700 case 1:
1701 ret = ((s->window[w].rightbot_x & FIMD_VIDOSD_COORD_MASK) <<
1702 FIMD_VIDOSD_HOR_SHIFT) |
1703 (s->window[w].rightbot_y & FIMD_VIDOSD_COORD_MASK);
1704 break;
1705 case 2:
1706 if (w == 0) {
1707 ret = s->window[w].osdsize;
1708 } else {
1709 ret = (pack_upper_4(s->window[w].alpha_val[0]) <<
1710 FIMD_VIDOSD_AEN0_SHIFT) |
1711 pack_upper_4(s->window[w].alpha_val[1]);
1712 }
1713 break;
1714 case 3:
1715 if (w != 1 && w != 2) {
1716 DPRINT_ERROR("bad read offset 0x%08x\n", offset);
1717 return 0xBAADBAAD;
1718 }
1719 ret = s->window[w].osdsize;
1720 break;
1721 }
1722 return ret;
1723 case FIMD_VIDWADD0_START ... FIMD_VIDWADD0_END:
1724 w = (offset - FIMD_VIDWADD0_START) >> 3;
1725 i = ((offset - FIMD_VIDWADD0_START) >> 2) & 1;
1726 return s->window[w].buf_start[i];
1727 case FIMD_VIDWADD1_START ... FIMD_VIDWADD1_END:
1728 w = (offset - FIMD_VIDWADD1_START) >> 3;
1729 i = ((offset - FIMD_VIDWADD1_START) >> 2) & 1;
1730 return s->window[w].buf_end[i];
1731 case FIMD_VIDWADD2_START ... FIMD_VIDWADD2_END:
1732 w = (offset - FIMD_VIDWADD2_START) >> 2;
1733 return s->window[w].virtpage_width | (s->window[w].virtpage_offsize <<
1734 FIMD_VIDWADD2_OFFSIZE_SHIFT);
1735 case FIMD_VIDINTCON0 ... FIMD_VIDINTCON1:
1736 return s->vidintcon[(offset - FIMD_VIDINTCON0) >> 2];
1737 case FIMD_WKEYCON_START ... FIMD_WKEYCON_END:
1738 w = ((offset - FIMD_WKEYCON_START) >> 3) + 1;
1739 i = ((offset - FIMD_WKEYCON_START) >> 2) & 1;
1740 return s->window[w].keycon[i];
1741 case FIMD_WKEYALPHA_START ... FIMD_WKEYALPHA_END:
1742 w = ((offset - FIMD_WKEYALPHA_START) >> 2) + 1;
1743 return s->window[w].keyalpha;
1744 case FIMD_DITHMODE:
1745 return s->dithmode;
1746 case FIMD_WINMAP_START ... FIMD_WINMAP_END:
1747 return s->window[(offset - FIMD_WINMAP_START) >> 2].winmap;
1748 case FIMD_WPALCON_HIGH ... FIMD_WPALCON_LOW:
1749 return s->wpalcon[(offset - FIMD_WPALCON_HIGH) >> 2];
1750 case FIMD_TRIGCON:
1751 return s->trigcon;
1752 case FIMD_I80IFCON_START ... FIMD_I80IFCON_END:
1753 return s->i80ifcon[(offset - FIMD_I80IFCON_START) >> 2];
1754 case FIMD_COLORGAINCON:
1755 return s->colorgaincon;
1756 case FIMD_LDI_CMDCON0 ... FIMD_LDI_CMDCON1:
1757 return s->ldi_cmdcon[(offset - FIMD_LDI_CMDCON0) >> 2];
1758 case FIMD_SIFCCON0 ... FIMD_SIFCCON2:
1759 i = (offset - FIMD_SIFCCON0) >> 2;
1760 return s->sifccon[i];
1761 case FIMD_HUECOEFCR_START ... FIMD_HUECOEFCR_END:
1762 i = (offset - FIMD_HUECOEFCR_START) >> 2;
1763 return s->huecoef_cr[i];
1764 case FIMD_HUECOEFCB_START ... FIMD_HUECOEFCB_END:
1765 i = (offset - FIMD_HUECOEFCB_START) >> 2;
1766 return s->huecoef_cb[i];
1767 case FIMD_HUEOFFSET:
1768 return s->hueoffset;
1769 case FIMD_VIDWALPHA_START ... FIMD_VIDWALPHA_END:
1770 w = ((offset - FIMD_VIDWALPHA_START) >> 3);
1771 i = ((offset - FIMD_VIDWALPHA_START) >> 2) & 1;
1772 return s->window[w].alpha_val[i] &
1773 (w == 0 ? 0xFFFFFF : FIMD_VIDALPHA_ALPHA_LOWER);
1774 case FIMD_BLENDEQ_START ... FIMD_BLENDEQ_END:
1775 return s->window[(offset - FIMD_BLENDEQ_START) >> 2].blendeq;
1776 case FIMD_BLENDCON:
1777 return s->blendcon;
1778 case FIMD_WRTQOSCON_START ... FIMD_WRTQOSCON_END:
1779 return s->window[(offset - FIMD_WRTQOSCON_START) >> 2].rtqoscon;
1780 case FIMD_I80IFCMD_START ... FIMD_I80IFCMD_END:
1781 return s->i80ifcmd[(offset - FIMD_I80IFCMD_START) >> 2];
1782 case FIMD_VIDW0ADD0_B2 ... FIMD_VIDW4ADD0_B2:
1783 if (offset & 0x0004) {
1784 break;
1785 }
1786 return s->window[(offset - FIMD_VIDW0ADD0_B2) >> 3].buf_start[2];
1787 case FIMD_SHD_ADD0_START ... FIMD_SHD_ADD0_END:
1788 if (offset & 0x0004) {
1789 break;
1790 }
1791 return s->window[(offset - FIMD_SHD_ADD0_START) >> 3].shadow_buf_start;
1792 case FIMD_SHD_ADD1_START ... FIMD_SHD_ADD1_END:
1793 if (offset & 0x0004) {
1794 break;
1795 }
1796 return s->window[(offset - FIMD_SHD_ADD1_START) >> 3].shadow_buf_end;
1797 case FIMD_SHD_ADD2_START ... FIMD_SHD_ADD2_END:
1798 return s->window[(offset - FIMD_SHD_ADD2_START) >> 2].shadow_buf_size;
1799 case FIMD_PAL_MEM_START ... FIMD_PAL_MEM_END:
1800 w = (offset - FIMD_PAL_MEM_START) >> 10;
1801 i = ((offset - FIMD_PAL_MEM_START) >> 2) & 0xFF;
1802 return s->window[w].palette[i];
1803 case FIMD_PALMEM_AL_START ... FIMD_PALMEM_AL_END:
1804 /* Palette aliases for win 0,1 */
1805 w = (offset - FIMD_PALMEM_AL_START) >> 10;
1806 i = ((offset - FIMD_PALMEM_AL_START) >> 2) & 0xFF;
1807 return s->window[w].palette[i];
1808 }
1809
1810 DPRINT_ERROR("bad read offset 0x%08x\n", offset);
1811 return 0xBAADBAAD;
1812}
1813
1814static const MemoryRegionOps exynos4210_fimd_mmio_ops = {
1815 .read = exynos4210_fimd_read,
1816 .write = exynos4210_fimd_write,
1817 .valid = {
1818 .min_access_size = 4,
1819 .max_access_size = 4,
1820 .unaligned = false
1821 },
1822 .endianness = DEVICE_NATIVE_ENDIAN,
1823};
1824
1825static int exynos4210_fimd_load(void *opaque, int version_id)
1826{
1827 Exynos4210fimdState *s = (Exynos4210fimdState *)opaque;
1828 int w;
1829
1830 if (version_id != 1) {
1831 return -EINVAL;
1832 }
1833
1834 for (w = 0; w < NUM_OF_WINDOWS; w++) {
1835 exynos4210_fimd_update_win_bppmode(s, w);
1836 fimd_update_get_alpha(s, w);
1837 fimd_update_memory_section(s, w);
1838 }
1839
1840 /* Redraw the whole screen */
1841 exynos4210_update_resolution(s);
1842 exynos4210_fimd_invalidate(s);
1843 exynos4210_fimd_enable(s, (s->vidcon[0] & FIMD_VIDCON0_ENVID_MASK) ==
1844 FIMD_VIDCON0_ENVID_MASK);
1845 return 0;
1846}
1847
1848static const VMStateDescription exynos4210_fimd_window_vmstate = {
1849 .name = "exynos4210.fimd_window",
1850 .version_id = 1,
1851 .minimum_version_id = 1,
8f1e884b 1852 .fields = (VMStateField[]) {
30628cb1
MI		 1853 VMSTATE_UINT32(wincon, Exynos4210fimdWindow),
1854 VMSTATE_UINT32_ARRAY(buf_start, Exynos4210fimdWindow, 3),
1855 VMSTATE_UINT32_ARRAY(buf_end, Exynos4210fimdWindow, 3),
1856 VMSTATE_UINT32_ARRAY(keycon, Exynos4210fimdWindow, 2),
1857 VMSTATE_UINT32(keyalpha, Exynos4210fimdWindow),
1858 VMSTATE_UINT32(winmap, Exynos4210fimdWindow),
1859 VMSTATE_UINT32(blendeq, Exynos4210fimdWindow),
1860 VMSTATE_UINT32(rtqoscon, Exynos4210fimdWindow),
1861 VMSTATE_UINT32_ARRAY(palette, Exynos4210fimdWindow, 256),
1862 VMSTATE_UINT32(shadow_buf_start, Exynos4210fimdWindow),
1863 VMSTATE_UINT32(shadow_buf_end, Exynos4210fimdWindow),
1864 VMSTATE_UINT32(shadow_buf_size, Exynos4210fimdWindow),
1865 VMSTATE_UINT16(lefttop_x, Exynos4210fimdWindow),
1866 VMSTATE_UINT16(lefttop_y, Exynos4210fimdWindow),
1867 VMSTATE_UINT16(rightbot_x, Exynos4210fimdWindow),
1868 VMSTATE_UINT16(rightbot_y, Exynos4210fimdWindow),
1869 VMSTATE_UINT32(osdsize, Exynos4210fimdWindow),
1870 VMSTATE_UINT32_ARRAY(alpha_val, Exynos4210fimdWindow, 2),
1871 VMSTATE_UINT16(virtpage_width, Exynos4210fimdWindow),
1872 VMSTATE_UINT16(virtpage_offsize, Exynos4210fimdWindow),
1873 VMSTATE_END_OF_LIST()
1874 }
1875};
1876
1877static const VMStateDescription exynos4210_fimd_vmstate = {
1878 .name = "exynos4210.fimd",
1879 .version_id = 1,
1880 .minimum_version_id = 1,
1881 .post_load = exynos4210_fimd_load,
8f1e884b 1882 .fields = (VMStateField[]) {
30628cb1
MI		 1883 VMSTATE_UINT32_ARRAY(vidcon, Exynos4210fimdState, 4),
1884 VMSTATE_UINT32_ARRAY(vidtcon, Exynos4210fimdState, 4),
1885 VMSTATE_UINT32(shadowcon, Exynos4210fimdState),
1886 VMSTATE_UINT32(winchmap, Exynos4210fimdState),
1887 VMSTATE_UINT32_ARRAY(vidintcon, Exynos4210fimdState, 2),
1888 VMSTATE_UINT32(dithmode, Exynos4210fimdState),
1889 VMSTATE_UINT32_ARRAY(wpalcon, Exynos4210fimdState, 2),
1890 VMSTATE_UINT32(trigcon, Exynos4210fimdState),
1891 VMSTATE_UINT32_ARRAY(i80ifcon, Exynos4210fimdState, 4),
1892 VMSTATE_UINT32(colorgaincon, Exynos4210fimdState),
1893 VMSTATE_UINT32_ARRAY(ldi_cmdcon, Exynos4210fimdState, 2),
1894 VMSTATE_UINT32_ARRAY(sifccon, Exynos4210fimdState, 3),
1895 VMSTATE_UINT32_ARRAY(huecoef_cr, Exynos4210fimdState, 4),
1896 VMSTATE_UINT32_ARRAY(huecoef_cb, Exynos4210fimdState, 4),
1897 VMSTATE_UINT32(hueoffset, Exynos4210fimdState),
1898 VMSTATE_UINT32_ARRAY(i80ifcmd, Exynos4210fimdState, 12),
1899 VMSTATE_UINT32(blendcon, Exynos4210fimdState),
1900 VMSTATE_STRUCT_ARRAY(window, Exynos4210fimdState, 5, 1,
1901 exynos4210_fimd_window_vmstate, Exynos4210fimdWindow),
1902 VMSTATE_END_OF_LIST()
1903 }
1904};
1905
380cd056
GH		 1906static const GraphicHwOps exynos4210_fimd_ops = {
1907 .invalidate = exynos4210_fimd_invalidate,
1908 .gfx_update = exynos4210_fimd_update,
1909};
1910
3c09d6ca 1911static void exynos4210_fimd_init(Object *obj)
30628cb1 1912{
3c09d6ca
XZ		 1913 Exynos4210fimdState *s = EXYNOS4210_FIMD(obj);
1914 SysBusDevice *dev = SYS_BUS_DEVICE(obj);
30628cb1
MI		 1915
1916 s->ifb = NULL;
1917
1918 sysbus_init_irq(dev, &s->irq[0]);
1919 sysbus_init_irq(dev, &s->irq[1]);
1920 sysbus_init_irq(dev, &s->irq[2]);
1921
3c09d6ca 1922 memory_region_init_io(&s->iomem, obj, &exynos4210_fimd_mmio_ops, s,
30628cb1
MI		 1923 "exynos4210.fimd", FIMD_REGS_SIZE);
1924 sysbus_init_mmio(dev, &s->iomem);
3c09d6ca 1925}
30628cb1 1926
3c09d6ca
XZ		 1927static void exynos4210_fimd_realize(DeviceState *dev, Error **errp)
1928{
1929 Exynos4210fimdState *s = EXYNOS4210_FIMD(dev);
1930
1931 s->console = graphic_console_init(dev, 0, &exynos4210_fimd_ops, s);
30628cb1
MI		 1932}
1933
1934static void exynos4210_fimd_class_init(ObjectClass *klass, void *data)
1935{
1936 DeviceClass *dc = DEVICE_CLASS(klass);
30628cb1
MI		 1937
1938 dc->vmsd = &exynos4210_fimd_vmstate;
1939 dc->reset = exynos4210_fimd_reset;
3c09d6ca 1940 dc->realize = exynos4210_fimd_realize;
30628cb1
MI		 1941}
1942
8c43a6f0 1943static const TypeInfo exynos4210_fimd_info = {
f27321aa 1944 .name = TYPE_EXYNOS4210_FIMD,
30628cb1
MI		 1945 .parent = TYPE_SYS_BUS_DEVICE,
1946 .instance_size = sizeof(Exynos4210fimdState),
3c09d6ca 1947 .instance_init = exynos4210_fimd_init,
30628cb1
MI		 1948 .class_init = exynos4210_fimd_class_init,
1949};
1950
1951static void exynos4210_fimd_register_types(void)
1952{
1953 type_register_static(&exynos4210_fimd_info);
1954}
1955
1956type_init(exynos4210_fimd_register_types)
Empty description
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